JP2000196331A - Phased array antenna and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a relatively compact and inexpensive phased array antenna even at the time of increasing the number of radiating elements for improving a gain. SOLUTION: A phased array antenna 1 is obtained as a multi-layer structure in which plural radiating elements 15, phase shifting units 16 for changing the phase of a high frequency signal transmitted and received by each radiating element, and a distributing and synthesizing part 14 are formed in different layers so that inter-element intervals can be reduced. Also, a phase control layer is constituted of plural inner wiring layers according to the number of necessary driving lines 19, and signal wiring for controlling each phase shifting unit 16 is formed in the inner wiring layers so that an area necessary for the wiring can be reduced, and the inter-element intervals can be reduced. Moreover, the repeatedly constituted circuit part of each phase shifting unit 16 is constituted by using chips integrated and mounted on another substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phased array antenna used for transmitting and receiving high-frequency signals such as microwaves and millimeter waves, and adjusting a beam radiation direction by controlling a phase supplied to each radiating element. is there.

[0002]

2. Description of the Related Art Conventionally, a phased array antenna composed of a large number of radiating elements arranged in an array has been proposed as a satellite tracking on-vehicle antenna or a satellite-mounted antenna (for example, Technical Report AP90- of the Institute of Electronics, Information and Communication Engineers). 7
5 and JP-A-1-290301). This type of phased array antenna has a function of arbitrarily changing the direction of a beam by electronically changing the phase fed to each radiating element. Usually, a phase shifter is used as a means for changing the feed phase of each radiating element.

As this phase shifter, a digital phase shifter (hereinafter, a digital phase shifter is simply referred to as a phase shifter) composed of a plurality of phase shift circuits each having a fixed different phase shift amount is used. Is done. Each phase shift circuit is on / off controlled by a 1-bit digital control signal, and by combining the phase shift amounts of the respective phase shift circuits, the power supply phase of 0 ° to 360 ° in the entire phase shifter is adjusted. can get.

In particular, in a conventional phased array antenna, a PI is used as a switching element in each phase shift circuit.
A large number of semiconductor devices such as N diodes and GaAs FETs, and a large number of drive circuit components for driving these devices are used. Then, a direct current or a direct current voltage is applied to these switching elements to turn them on / off, and a predetermined phase shift amount is generated by changing a transmission line length, a susceptance, a reflection coefficient, and the like.

On the other hand, in recent years, in the field of low-orbit satellite communication, communication at a high data rate has been demanded due to the expansion of the use of the Internet and the spread of multimedia communication. It has become. In addition, in order to realize communication at a high data rate, it is necessary to increase a transmission bandwidth, and further, due to a lack of frequency resources in a low frequency band, a Ka band (about 20 G
(Hz-) or higher.

Specifically, as an antenna of a low-Earth orbit satellite tracking terminal (ground station), for example, a frequency: 30 GHz,
There is a demand for technical performance such as an antenna gain of 36 dBi and a beam scanning range of 50 ° from the front. In order to realize this with a phased array antenna, first, an opening area: about 0.13 m ² (360 mm × 3
60 mm).

Furthermore, in order to suppress side lobes, it is necessary to arrange the radiating elements at intervals of about 1/2 wavelength (about 5 mm at 30 GHz) to avoid the generation of grating lobes. Further, in order to make the beam scanning step fine and to suppress the side lobe deterioration due to the quantization error of the digital phase shifter, the phase shift circuit used for each phase shifter has 4 bits (the minimum bit phase shifter 22). .5 ゜)
It is desirable that this is the case.

The total number of radiating elements and the number of phase shift circuit bits used in the phased array antenna satisfying the above conditions are: the number of phase shift circuit elements: 72 × 72 = about 5,000, the number of phase shift circuit bits: 72 × 72 × 4 = about 20,000 bits.

[0009]

Here, a phased array antenna having such a high gain and applicable to a high frequency band is disclosed in the above-mentioned prior art, for example, in Japanese Unexamined Patent Application Publication No.
However, when the phased array antenna described in Japanese Unexamined Patent Application Publication No. 290301 is used, the following problems arise.
That is, in such a conventional phased array antenna, as shown in FIG. 18, a single driver circuit controls each phase shift circuit in each phase shifter. It is necessary to connect the phase shift circuits individually.

Therefore, the number of wirings for the connection is required by the number of radiating elements × the number of bits of the phase shift circuit. If the above-described numerical values are applied, one line is arranged in an array of 72 × 72 radiating elements. The number of wires for each phase shift circuit (4 bits) for each (72 radiating elements) is 72.times.4 = 288. When such wiring is formed on the same plane,
Even if the wiring width / interval (L / S) = 50/50 μm, the width of the wiring bundle for one row (72 radiating elements) is 0.1.
mm × 288 = 28.8 mm.

On the other hand, as described above, the frequency 3
In a phased array antenna applicable to 0 GHz,
It is necessary to arrange the radiating elements at intervals of about 5 mm. However, in the prior art, the width of the wiring bundle is too large to physically arrange the radiating elements. Therefore, in such prior art,
There is a problem that a phased array antenna having a high gain and applicable to a high frequency band cannot be realized. An object of the present invention is to solve such a problem, and an object of the present invention is to provide a phased array antenna having a high gain and applicable to a high frequency band.

[0012]

In order to achieve such an object, a phased array antenna according to the present invention comprises:
The radiating element and the phase control means are formed in separate radiating element layers and phase control layers, respectively, to form a multilayer structure as a whole. A plurality of driving means, and a plurality of phase shift means for controlling the phase of each of the radiating elements in response to the control signal. Then, this is mounted on the second substrate on which the phase control layer is formed.

Therefore, at least the radiating elements are removed from the phase control layer, and the area occupied by these elements on the phase control layer is reduced. Also, the number of components and the number of connection points are reduced as compared with the case where individual circuit components are individually mounted as in the related art.

[0014]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a phased array antenna 1 according to one embodiment of the present invention. In the following, a case where a phased array antenna is used as a transmitting antenna for a high-frequency signal will be described as an example, but the present invention is not limited to this. It is also possible. Further, when the entire antenna is composed of a plurality of subarrays, the present invention may be applied to a phased array antenna of each subarray.

FIG. 1 is a diagram for explaining the configuration of the phased array antenna 1. As shown in FIG. In FIG. 1, a phased array antenna 1 includes a multilayer substrate unit 2 in which a radiating element, a phase control circuit, and the like are mounted on a multilayer substrate, a power supply unit 13 that supplies high-frequency power to the multilayer substrate unit 2, and a multilayer substrate unit 2. It comprises a control device 11 for controlling the phase of each radiating element.

In FIG. 1, m × n (m, n is an integer of 2 or more) radiating elements 15 are arranged in an array.
A high-frequency signal is supplied via A (the thick line in the figure). The arrangement of the radiating elements 15 may be arranged in a square lattice arrangement, or may be arranged in another arrangement such as a triangular arrangement.

Each radiating element 15 has a phase shifter 17
Is provided. Hereinafter, the phase shifter 17 provided for each radiating element 15 and a part of the strip line connected to the phase shifter 17 are collectively referred to as a phase shift unit 16.

Here, in the circuit constituting each phase shift unit 16, a circuit portion repeatedly formed between the phase shift units 16 or within the same phase shift unit 16 is integrated on another substrate and formed into a chip. And a phase control layer 3 described later.
5 is implemented. Further, as will be described later, there are various types of circuit regions to be chipped, but FIG. 1 shows a case where the entire phase shift unit 16 is chipped.

In the present specification, a small piece (first substrate) cut out for each unit after forming a large number of identical or similar unit circuits on a substrate by a semiconductor process or the like is referred to as a bare chip, and is further referred to as another substrate ( A device in which processing for mounting and mounting on a second substrate is performed on a bare chip is referred to as a chip. Also, in order to obtain a final chip, cutting out a large number of circuits formed collectively for each unit or performing processing for mounting and mounting on another substrate (second substrate) is called chip formation. .

The control device 11 is a device for calculating a feed phase shift amount of each radiation element 15 based on a desired beam radiation direction. The calculated phase shift amount of each radiating element 15 is the control signal 1
The control device 11 distributes the signals to the p drive units 12 as 11 to 11p (one of these signals is sometimes referred to as a control signal 11i). Also, one drive unit 12
, The phase shift amounts of the q radiating elements are serially input. Here, p × q is basically the total number of radiating elements m × n
, But slightly larger depending on the number of output terminals of the drive unit 12.

FIG. 2 is a block diagram of the drive unit 12. Each drive unit 12 is provided with a data distribution unit 53
And q phase control units 5 provided for each phase shifter 17
4. The phase shift amount of q radiating elements is serially input to one drive unit 12.

The data distribution unit 53 calculates the phase shift amount of the q radiating elements 15 included in the control signal 11i by using the phase shifter 17
To the q number of phase control units 54 connected to the respective sections. Accordingly, the phase shift amount of the corresponding radiating element 15 is set for each phase control unit 54.

On the other hand, as shown in FIG. 1, the control device 11 outputs a trigger signal Trg 'to each drive unit 12.
The trigger signal Trg 'is input to the phase control unit 54 of each drive unit 12, as shown in FIG.

The trigger signal Trg ′ is transmitted to each phase control unit 54
Is a signal for determining the timing at which the phase shift amount set to the above is instructed and output to each phase shifter 17. Therefore,
After setting the amount of phase shift for each phase control unit 54, by outputting this trigger signal Trg 'from the control device 11, the amount of phase shift for power supply to each radiating element 15 can be updated simultaneously.
The beam emission direction can be changed instantaneously.

Next, the phase shifter 17 provided for each radiating element 15 and the phase control unit 54 of the drive unit 12 will be described with reference to FIG. FIG. 3 is a block diagram of the phase shifter 17 and the phase control unit 54. Here, the phase shifter 17 includes four phase shift circuits 17A to 17D each having a different phase shift amount of 22.5 °, 45 °, 90 °, and 180 °. Each of the phase shift circuits 17A to 17D is connected to a strip line 16A for transmitting a high-frequency signal from the distribution / combination unit 14 to the radiating element 15.

In particular, each of the phase shift circuits 17A to 17D is provided with a switch 17S. By switching the switch 17S, a predetermined power supply phase shift amount is given as described later.

The phase control unit 54 for individually controlling the switches 17S of the phase shift circuits 17A to 17D includes latches 55A to 55A provided for each of the phase shift circuits 17A to 17D.
D. The data distribution unit 53 of the drive unit 12 includes the latches 55 </ b> A
By outputting the control signals 53 </ b> A to 53 </ b> D to 55 </ b> D, the phase shift amount of the radiating element 15 is given to the phase control unit 54. Therefore, control signals 53A to 53D are input to the inputs D of the latches 55A to 55D, respectively.

The input CL of each of the latches 55A to 55D
K is a trigger signal Tr output from the control device 11
g 'is input. Each of the latches 55A to 55D latches the control signal 53A to 53D at the rising (or falling) of the trigger signal Trg ', and via the drive line 19 that individually connects these latches and each phase shift circuit. Output Q (Cnt) corresponding to each phase shift circuit 1
It outputs to the switch 17S of 7A-17D.

At this time, the latched control signals 53A to 53A-5
On / off of the switch 17S of each of the phase shift circuits 17A to 17D is determined according to the 3D state. In this way, the phase shift amounts of the phase shift circuits 17A to 17D are set, and the phase shift amounts of the entire phase shifter 17 are set. Thus, a predetermined power supply phase shift amount is given to the high-frequency signal propagating through the strip line 16A. Can be

The switch 17S may be sequentially switched by keeping the trigger signal Trg 'at H level (or L level) at all times. In this case, since the phase shifters 17 are switched one by one without switching at the same time, instantaneous interruption of the radiation beam can be avoided. The output voltage or current of the latches 55A to 55D is
If not enough to drive S, latches 55A-55
A voltage amplifier or a current amplifier may be provided on the output side of D.

Next, the substrate configuration of the phased array antenna according to the present embodiment will be described with reference to FIG. FIG. 4 is an explanatory view showing the multilayer substrate unit 2, and shows a perspective view and a schematic cross-sectional view of each layer.

Each of these layers is formed by a photolithography technique,
After a pattern is formed by an etching technique and a printing technique, they are laminated and integrated into a multilayer (first multilayer structure). Note that the stacking order of each layer is not necessarily limited to the form shown in FIG. 4. The stacking order may be changed or deleted or the stacking order may be partially changed depending on the conditions of electrical and mechanical requirements. The invention is valid.

In the distribution / combination layer 39, a branch strip line 23 for distributing a high-frequency signal from the power supply unit 13 (not shown in FIG. 4) is formed. This strip line 2
As 3, the tournament system in which two branches are repeated or a series distribution system in which the main line is gradually branched in a comb shape can be used.

A dielectric layer 38A and a ground layer 39A made of a conductor are further provided outside the distribution / combination layer 39 in accordance with mechanical design conditions such as mechanical strength or electrical design conditions such as suppression of unnecessary radiation. You.

Above the distribution / combination layer 39, a coupling layer 37 (second coupling layer) is provided via a dielectric layer 38. The coupling layer 37 is formed of a conductor pattern in which a hole, that is, the coupling slot 22 is formed in the ground plane.

Above this, a phase control layer 35 is provided via a dielectric layer 36. The phase control layer 35 is provided with each phase shifter 17, a drive unit 12 for individually controlling these phase shifters 17, and a drive line 19 for connecting each phase shifter 17 to the drive unit 12. Have been.

Since the number of the radiating elements 15 is large, the number of the driving lines 19 is large, and all the driving lines 19 are formed in one layer.
In the present invention, when the phase control layer 35 cannot be wired, the phase control layer 35 is composed of a plurality of wiring layers, and a layer different from the layer on which the phase shift unit 16 is mounted and formed, that is, the phase control layer 3 is formed.
A large number of drive lines 19 are provided in a wiring layer (internal wiring layer) inside 5 (second multilayer structure). Then, these drive lines 19 are individually driven by the drive unit 12, and a desired phase shift amount is set in the corresponding phase control unit 54.

Above the phase control layer 35, a coupling layer 33 (first coupling layer) having the same coupling slot 21 as the coupling layer 37 is provided via a dielectric layer 34. Above it, the radiating element 15 is interposed via a dielectric layer 32.
Is provided. Further above the parasitic element 15 via a dielectric layer 31B.
A parasitic element layer 31A on which A is formed is provided.
However, the parasitic element 15A is added for widening the band, and may be configured as needed.

The dielectric layers 31B, 32, 38, 38
A is a low dielectric constant substrate having a relative dielectric constant of about 1 to 4;
For example, materials such as a printed board, a glass substrate, and a foam material are used. In addition, these dielectric layers may be spaces (air layers). As the dielectric layer 36, a high dielectric constant substrate having a relative dielectric constant of about 5 to 30, for example, a ceramic substrate such as alumina, a glass substrate, a high dielectric constant printed board, or the like is used. The dielectric layer 34 has a relative dielectric constant of 1
A material such as about 11 to about 11 substrates, for example, a printed substrate, a ceramic substrate, a glass substrate, or a foam material is used. In particular, since a circuit portion formed into a chip is mounted on the phase control layer 35, a space (air layer) may be formed as the dielectric layer 34.

In FIG. 4, each layer constituting the multilayer substrate portion 2 has been separately described for simplicity.
A layer adjacent to 1B, 32, 34, 36, 38, 38A;
For example, the radiating element layer 31, the coupling layer 33, and the like can be realized by forming a pattern on one surface or both surfaces of the dielectric layer. Further, the dielectric layer does not necessarily need to be formed of a single material, and may have a configuration in which a plurality of materials are stacked.

In the multi-layer substrate section 2 described above, a high-frequency signal from the power supply section 13 (not shown in FIG. 2) is transmitted from the strip line 23 of the distribution / combination layer 39 via the coupling slot 22 of the coupling layer 37. , Propagate to the strip line of the phase control layer 35. Then, a predetermined feed phase shift amount is given by the phase shifter 17, propagates through the coupling slot 21 of the coupling layer 33 to the radiating elements 15 of the radiating element layer 31, and has a predetermined beam direction from each radiating element 15. Is radiated.

Here, as described above, the circuit constituting each phase shift unit 16 (ie, a phase shifter 17 provided for each radiating element 15 and a part of a strip line connected to the phase shifter 17) In each of the phase shift units 16
The circuit portion repeatedly formed between the same or the same phase shift unit 16 is integrated and formed on another substrate to form a chip,
The chip 67 is mounted on the phase control layer 35.

As a result, in the present invention, a defect inspection can be performed on a single chip, and the yield of the entire phased array antenna can be improved. In particular, a high gain phased array antenna composed of thousands of phase shift units can be achieved. Then, the manufacturing cost can be greatly reduced.

When the number of drive lines 19 is large, in the present invention, the phase control layer 35 is composed of a plurality of wiring layers (second multi-layer structure), of which the phase shift unit 16 is formed. Drive unit 12 on a different wiring layer from
Drive line 1 for individually connecting the phase shift controller 18 to the
9 was wired. Thereby, the drive line 19 for controlling each phase shifter 17 can be reduced from the layer on which the phase shift unit 16 is formed, and the area required for these wirings can be greatly reduced.

Further, according to the present invention, the radiating element 15 and the phase shift unit 16 are formed on the individual radiating element layer 31 and the phase control layer 35, respectively. (First multilayer structure).
Further, the distributing / combining unit 14 is formed in each distributing / combining layer 39, and the phase control layer 35 and the distributing / combining layer 39 are connected by a connecting layer 37, so that the whole has a multilayer structure. Thereby, the area occupied by the radiating element 15 and the distribution / combination unit 14 on the phase control layer 35 can be reduced, and the occupied area per radiating element can be reduced.

Therefore, since one phase shift unit 16 can be constructed with a relatively small area in this way,
For example, each radiating element 15 can be arranged at an optimum interval of about 5 mm for a high-frequency signal of about 30 GHz, and a phased array antenna having a high gain and applicable to a high frequency band can be realized. Further, by realizing the optimum element spacing, the beam scanning angle at which the grating lobe is generated is widened, so that the beam can be scanned over a wide range centering on the front direction of the antenna.

Each of the strip lines used in the present invention may be a microstrip type, a triplate type,
A distributed constant line such as a coplanar waveguide type or a slot type can be used. In addition to the patch antenna, a printed dipole antenna, a slot antenna, an aperture element, and the like can be used as the radiating element 15, and particularly, by increasing the opening of the slot 21 of the coupling layer 33, the radiating element 15 can be used as a slot antenna. In this case, the radiating element layer 31 is also used as the coupling layer 33, and the radiating element layer 31 and the parasitic element layer 31A become unnecessary.

Note that, instead of the coupling slot 21, a high-frequency signal may be coupled using a conductive feed pin that connects the strip line 16A of the phase control layer 35 and the radiating element 15. Further, instead of the coupling slot 22, a high-frequency signal is transmitted using a conductive power supply pin protruding from the strip line of the phase control layer 35 through the hole provided in the coupling layer 37 into the dielectric layer 38. They may be combined.

The same function as that of the distribution / combination layer 39 can also be realized by using a radial waveguide. FIG. 16 is an explanatory diagram showing a configuration example of the present invention when a radial waveguide is used. In this case, the distribution / synthesis function is realized by the dielectric layer 38, the ground layer 39A, and the probe 25 in the multilayer substrate unit 2 shown in FIG. 16, and the composite distribution layer 39 required in the embodiment of FIG. It has become.

In this case as well, the dielectric layer 38 is composed of a printed circuit board, a foaming agent, or a space (air layer). Further, as the ground layer 39A, a copper foil on a printed board may be used as it is, or a metal plate or a metal housing surrounding the entire side surface of the dielectric 38 may be separately provided.

Further, the present invention is also applicable to a space-fed phased array antenna. As one example, FIG. 17 shows a configuration example of a reflection-type space-fed phased array antenna. The phased array antenna 1 shown in FIG. 17 includes a feeder 13, a radiation feeder 27 including a primary radiator 26, the multilayer substrate 2, and the controller 11 (not shown).

Here, different from the embodiment shown in FIG. 4, the multilayer substrate section 2 is composed of a radiating element layer 31, a dielectric layer 32, a coupling layer 33, a dielectric layer 34, and a phase control layer 35. Further, since the function of the distribution / combination unit 14 shown in FIG. 1 is realized by the primary radiating unit 26, the distribution / combination layer 39 is excluded from the multilayer substrate unit 2.

In this phased array antenna 1, the high-frequency signal radiated from the radiation feeder 27 is received once by each radiating element 15 on the radiating element layer 31, and transferred to the phase control layer 35 via the coupling layer 33. Each is connected to a phase unit 16. Here, the high-frequency signal is phase-controlled by each phase shift unit 16, propagates again to each radiating element 15 via the coupling layer 33, and is radiated from each radiating element 15 in a predetermined beam direction. The present invention is also effective in a mode in which the multi-layer substrate section 2 does not include the combined distribution layer 39 as in the space-fed phased array antenna described above.

Next, a configuration example of the phase control layer 35 will be described with reference to FIG. FIG. 5 is an explanatory diagram schematically showing the arrangement of the phase control layer 35. In the multilayer structure region of the phase control layer 35, a number of phase shifters 17 are arranged in an array, and a wiring pattern of the drive line 19 is formed. In addition, a plurality of drive units 12 each composed of a flip chip 51 are arranged outside the multilayer structure region of the phase control layer 35.

The flip chip 51 is a chip that is bonded (ie, face-down bonded) using connection terminals provided on a chip or a substrate without using lead wires such as wire leads or beam leads. When the flip chip 51 is mounted by using the bump method, a bump 52 is formed as a connection terminal on each of the chip electrodes, and the bump 52 and the wiring of the phase control layer 35 are directly or via an anisotropic conductive sheet. Connect.

When the driving unit 12 is constituted by the flip chip 51, an input electrode of the control signal 11i inputted to the data distribution unit 53, a common electrode of an input CLK of each latch 55 constituting each phase control unit 54, The bump 52 is formed on each electrode of the output Q of each latch 55. In particular,
The bump 52 serving as the output Q of each latch 55 is individually connected to one of the phase shift circuits 17A to 17D constituting the phase shifter 17 by the drive line 19 formed on the phase control layer 35.

The bumps 52 are formed not only at the periphery of the chip but also at the periphery of the chip.
Since it is formed on the entire surface of the chip, the size of the chip does not always increase even if the number of electrodes increases, and the mounting density of the IC can be increased. Therefore, by increasing the number of radiating elements 15 to improve the antenna gain, even if the total number of bits of the phase shifter 17 to be controlled increases, the drive unit 12 for driving the phase shifter 17 is increased. With the configuration using the flip chip 51, the size of the phased array antenna can be suppressed.

Further, since the number of chips mounted on the phase control layer 35 can be reduced, the time required for arranging the chips at predetermined positions can be reduced, and the production lead time can be suppressed from being lengthened.

As an example, in constructing a phased array antenna, the number of radiating elements 15 is set to 5000 in order to obtain a gain of 36 dBi, and the phase shifter 17 is used for each phase shifter 17 in order to reduce the beam scanning step. Assuming that four bits are provided for the phase circuit, the total number of phase shift circuit bits is 20,000 bits. In this case, a chip for 20,000 terminals is required to form the drive unit 12, but a flip chip 51 having 2,000 terminals is required.
, All the phase shifters 17 can be driven by the ten flip chips 51.

Each flip chip 51 is arranged in the column direction on both sides of the phase control layer 35. Then, the flip chip 51 arranged on the left side controls the left half of each of the phase shifters 17 arranged in the row direction,
The flip chip 51 arranged on the right side controls the right half of each of the phase shifters 17 arranged in the row direction.

When the number of drive lines 19 is large, the phase control layer 35 has a multilayer structure composed of a plurality of internal wiring layers, and the bumps 52 of the flip chip 51 and the phase shift circuits 17A to 17D are connected to each other. Each drive line 19 to be connected
Are wired separately for each layer of the phase control layer 35. The drive line 19 formed on a different layer from the flip chip 51 or the phase shift circuits 17A to 17D is connected to the flip chip 51 or the phase shift circuit 17A via a via hole formed in the substrate.
Needless to say, it is connected to .about.17D.

As a result, the maximum width of the bundle of the drive lines 19 is reduced, so that the area prepared for the drive lines 19 in the phase control layer 35 can be reduced. Therefore, the phased array antenna can be downsized, and the radiating element 15
Can be narrowed, so that the radiation beam range can be widened. When the number of the driving lines 19 is small or when the wiring width of the driving lines 19 is narrowed, all the driving lines 19 may be wired in one layer without forming the phase control layer 35 in multiple layers. it can.

Here, the flip chip 5 of the bump type is used.
1 has been described, but instead of forming the bump 52 on the chip, a bump is formed on the substrate (here, the phase control layer 35) on which the flip chip 51 is mounted, and the flip chip 51 is mounted in the same manner as described above. You may. Further, as the phase control layer 35, a method of forming a multilayered substrate (build-up substrate) by laminating a plurality of sheet-like substrates on which a predetermined wiring pattern is formed may be applied.

Next, an example of the configuration of the switch 17S will be described with reference to FIG. FIG. 6 is a perspective view showing a configuration example of the switch. This switch is constituted by a micromachine switch for short-circuiting / opening the strip lines 62 and 63 by a contact (micro contact portion) 64.

The strip lines 62 and 63 (about 1 μm in height) are formed on the substrate 61 with a slight gap, and a contact 64 (about 2 μm in height) is formed above the gap. It is supported by a support member 65 so as to be able to freely contact with and separate from 63. Here, the distance between the lower surface of the contact 64 and the upper surfaces of the strip lines 62 and 63 is about 4 μm, and the height of the upper surface of the contact 64 with respect to the upper surface of the substrate 61, that is, the height of the entire micromachine switch is about 7 μm. It is.

On the other hand, strip lines 62,
A conductor electrode 66 (having a height of about 0.2 μm) is formed in the gap 63, and the height of the electrode 66 is lower than the height of the strip lines 62 and 63.

The operation of this switch will be described below. Output voltages (for example, about 10 to 100 V) of the drive circuits 19A to 19D are individually supplied to the electrodes 66.
Here, when a positive output voltage is applied to the electrode 66,
As a result, a positive charge is generated on the surface of the electrode 66, and a negative charge appears on the surface of the opposing contact 64 due to electrostatic induction.
It is drawn to the 2,63 side.

At this time, since the length of the contact 64 is longer than the gap between the strip lines 62 and 63, the contact 64 contacts both the strip lines 62 and 63, and the strip lines 62 and 63 It becomes electrically conductive. When the application of the output voltage to the electrode 66 is stopped, the suction force is lost and the support member 6
5, the contact 64 is restored to the original separated position, and the strip lines 62 and 63 are opened.

In the above description, the case where the output voltage is applied to the electrode 66 without applying the voltage to the contact 64 has been described, but the reverse is also possible. That is, the output voltage of the drive circuit may be applied to the contact 64 via the support member 65 made of a conductor without applying a voltage to the electrode 66, and the same operation as described above can be obtained.
The contact 64 has at least a lower surface formed of a conductor and is in ohmic contact with the strip lines 62 and 63, but has an insulating thin film formed on the lower surface of the conductor member and is capacitively coupled to the strip lines 62 and 63. It may be.

Here, in the micromachine switch, since the contact 64 is a movable portion, when the phase control layer 35 is provided in a multilayer substrate as in the present phased array antenna, the space where the contact 64 can freely move is provided. It is necessary to provide.

As described above, since the micromachine switch is used as the switching element for controlling the power supply phase, power consumption at the semiconductor junction surface is reduced as compared with the case where a semiconductor device such as a PIN diode is used. Power consumption can be reduced to about one tenth.

Next, a configuration example of the chip will be described.
FIGS. 7A and 7B are explanatory diagrams showing a configuration example when the bare chip 68 is flip-chip mounted. FIG. 7A is a cross-sectional view of the chip 67A, FIG. 7B is a top view of the chip 67A, and FIG. Sectional view of mounting example (solder method)
(D) shows a cross-sectional view of a face-down mounting example (adhesion method) of the chip 67A. The range of the circuit included in the chip 67A may be various as described later with reference to FIG. 9, but hereinafter, the circuit portion shown in FIG. 9B, that is, the drive circuit and the switch are formed into chips. The case will be described as an example.

As shown in FIGS. 7A and 7B, a bare chip 68 includes a switch 82A composed of a micromachine switch and a thin film transistor (TF) on a glass substrate 81.
T) is formed. On the bare chip 68, bumps 83 made of solder, gold, or the like are formed on signal connection pads to obtain a chip 67A.

FIG. 7C shows a case where the chip 67A is mounted face-down on another substrate 84 by a soldering method or the like, and the signal connection whose periphery is covered with an insulating protective film 85A on the substrate 84 is shown. Pads 85 are formed. Then, the pad 85 and the bump 83 are fixed by solder or the like via the bump 85B and are electrically connected.

Here, the height after the formation of the pad 85, the bump 85B, and the bump 83 is, for example, 10 μm and 20 μm, respectively.
By setting the thickness to 20 μm, a space 87 having a height of 40 μm is formed around the switch 82A where the movable portion exists, after the final mounting, and the micromachine switch operates stably. The entire periphery of the substrate 81 or a part thereof is
Is fixed to the substrate 84. Thereby, the substrate 8
Even when mechanical stress is applied to the bumps 8, the bumps 8
5B is protected.

On the other hand, FIG. 7D shows a case where the chip 67A is mounted face-down on another substrate 84 by the bonding method, and a signal whose periphery is covered with an insulating protective film 85A on the substrate 84 is shown. A connection pad 85 is formed.
Then, the glass substrate 81 and the substrate 84 are
And the pad 85 and the bump 83 are in direct contact and electrically connected.

In this case, the adhesive 88 is applied to the switch 82A.
And the glass substrate 81 and the substrate 84
And are glued. As a result, a space 87 is formed around the switch 82A where the movable part exists, and the micromachine switch operates stably.

Further, since the glass substrate 81 and the substrate 84 are bonded to each other over a relatively wide range by the adhesive 88,
Even when a mechanical stress is applied to the substrate 84, the bonding portion of the bump 83 is protected. As described above, the predetermined circuit section including the switching element in the phase shift unit 16 is chipped and mounted on the phase control layer 35, so that the switching element can be mounted with a relatively simple configuration.

Further, before mounting on the phase control layer 35, a defect inspection can be performed on a single chip, and the yield of the entire device can be improved. In particular, since the bare chip is flip-chip mounted, the height required for the phase control layer 35 can be suppressed, and the coupling efficiency with the radiating element 15 coupled via the slot 21 can be improved.

The case where the bare chip is flip-chip mounted on the phase control layer 35 has been described above. If there is no problem even if the dielectric layer 34 in FIG. 4 is relatively thick, an LCC (Leadless Chip Carrier) or BGA
(Ball Grid Array) may be used. In this case, the SMD (Surface Mount De
vice), it can be automatically mounted on the phase control layer 35 quickly and easily, and the number of assembly steps can be greatly reduced.

Next, a circuit included in the chip will be described with reference to FIG. The phase shift unit 16 (that is, the phase shifter 17 and a part of the strip line connected to the phase shifter 17) provided for each radiating element 15 has a circuit portion that is used repeatedly. For example, FIG.
, The drive circuits 19A to 19D have the same circuit configuration.

The phase shift circuit 17A is connected to each radiating element 15
Circuit configuration common to the phase shifters 17 provided for
The same applies to the other phase shift circuits 17B to 17D. Therefore, of these circuit parts, a chip that is repeated for each of the radiating elements 15 or each of the phase shift circuits 17A to 17D can be made into a chip, so that a chip can be shared in each circuit part.

For example, FIG. 8A shows an example in which two switches 17S used in each phase circuit are chipped. Here, two switches 73 constituting the switch 17S, a strip line 74 for supplying a high-frequency signal to the switch 73, and a pad 72 are provided. Thereby, these chips can be shared by all the phase shift circuits 17A to 17D.

FIG. 8B shows the phase shift circuits 17A to 17A.
An example in which a chip is formed in units of 17D is shown. In particular, a portion surrounded by a broken line in the figure corresponds to FIG. 8A, and in addition, a strip line 75 for connecting the switch 17S to the strip line 16A, and a strip line 75 connected to the opposite side to the strip line. A distributed constant line 76 and a main line 70 having lengths corresponding to the respective phase shift amounts are provided. Thus, these chips can be shared for each of the phase shift circuits 17A to 17D of each phase shift unit 16.

FIG. 8C shows each phase shift unit 1.
6 shows an example in which all the phase shift circuits 17A to 17D in 6 are chipped. In particular, a portion surrounded by a broken line in the drawing corresponds to FIG. 8B, and in addition, a strip line 16A connecting the phase shift circuits 17A to 17D is formed. Thereby, these chips can be shared for each phase shift unit 16.

FIG. 8D shows each phase shift unit 1.
An example is shown in which a chip is formed in units of six. In particular,
The part surrounded by the broken line in the figure corresponds to FIG.
In addition, a strip line 77 connecting the slot 22 and the strip line 16A and a strip line 78 connecting the strip line 16A and the slot 21 are formed. Thereby, each chip is connected to each phase shift unit 16.
Can be shared.

As described above, the predetermined circuit portion including the switching element in the phase shift unit 16 is chipped and mounted on the phase control layer 35, so that the switching element can be mounted with a relatively simple configuration. it can. Therefore, the number of parts and the number of connection points can be reduced, and the number of assembly steps can be reduced.

7 and 8, the strip line 16
For A, a description has been given of an example of a rotated-line type phase shift circuit that controls a power supply phase by branch-connecting a predetermined distributed constant line via a switch 17S, but the present invention is not limited to this. Other phase shift circuits such as a line switching type and a reflection type may be used.

In general, when the phase shift amount is relatively small, better characteristics are obtained with the rotated line type, and when the phase shift amount is relatively large, better characteristics are obtained with the line switching type. For example, in the embodiment described later, 22.5 °, 45
Each of the phase shift circuits 17A to 17C of {, 90} is constituted by a loaded line type, and the phase shift circuit 17D of 180 ° is constituted by a line switching type.

Although the case where a micromachine switch is formed on a glass substrate as the switch 17S has been described as an example with reference to FIGS. 7 and 8, the substrate is not necessarily a glass substrate. Or a ceramic substrate. Further, a transistor circuit or a diode on a semiconductor substrate may be used instead of the micromachine switch.

[0091]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
First to fourth embodiments (configuration examples per radiation element) when applied to a GHz phased array antenna will be described. However, hereinafter, an example will be described in which the phase shifter 17 includes four phase shift circuits 17A to 17D having different phase shift amounts of 22.5 °, 45 °, 90 °, and 180 °.

It is assumed that a micromachine switch is used as a switching element of the phase shift circuit.
The dimensions described below are merely examples of the dimensions of each part of the antenna at 30 GHz, and the dimensions can be changed if the frequency changes, and other dimensions can be realized even at 30 GHz. I refuse that in advance.

First, a first embodiment will be described with reference to FIG. 9A and 9B are circuit layout diagrams showing the first embodiment, FIG. 9A is a circuit layout diagram of a phase control layer showing the entire phase shift unit, and FIG. 9B is a schematic diagram showing a multilayer structure. In the following, an example will be described in which the circuit unit shown in FIG. 8A, that is, a switch used in each phase shift circuit is formed into a chip.

As shown in FIG. 9A, the phase shift unit 1
Numerals 6 are provided corresponding to the respective radiating elements 15 arranged in an array, and are formed in a substantially square (5 mm × 5 mm) area (see the broken line square in the figure). Inside this region, there is provided a strip line 16A connecting the upper position of the via hole 16B to the lower position of the slot 21.

Further, 22.5 °, 45 °, 90 °, and 180 ° phase shift circuits are arranged in the middle of the strip line 16A. A part of these phase shift circuits is mounted on a chip 67 as a chip. The radiating element layer 31 above the slot 21 includes:
A circular radiating element 15 (thin broken line in the figure) having a diameter of 2.5 mm to 4 mm is arranged.

FIG. 10 is a circuit layout diagram showing each chip used in the first and second embodiments.
Chips used in phase shift circuits of ゜, 45 ゜ and 90 ゜,
(B) shows a chip used in a 180 ° phase shift circuit. In particular, FIG. 10A can be shared for a rotated line type phase shift circuit, and FIG. 10B can be shared for a line switching type phase shift circuit. Note that these chip configurations are the same as those in FIG. 7 and FIG. 8A described above, and description thereof will be omitted.

FIG. 9B shows a multilayer structure according to the first embodiment, and the same parts as those in FIG. 2 are denoted by the same reference numerals. Note that this figure schematically shows a multilayer structure, and does not show a specific cross section of FIG.

FIG. 9B shows a multilayer structure in this embodiment.
From bottom to top, the ground layer 39A, the dielectric layer 38 (thickness 1 mm) forming the radial waveguide, the coupling layer 37, the dielectric layer 36 (0.2 mm thickness), and the phase control layer 35 (thickness) 1
mm), a dielectric layer 34 (0.2 mm in thickness), a coupling layer 33 in which coupling slots 21 are formed, a dielectric layer 32 (0.3 mm in thickness), a radiating element layer 31, and a dielectric layer 31B (thickness). 1 mm), and the parasitic element layer 31A is laminated.

In this embodiment, the phase control layer 3
Reference numeral 5 denotes a plurality of wiring layers and dielectric layers, that is, a wiring layer 45, a multilayer wiring layer 44 including a plurality of internal wiring layers 44A, a wiring layer 43, a dielectric layer 42, and a chip 6 in order from bottom to top.
7 is mounted on the chip mounting layer 41.
However, in this embodiment, a ground conductor for electrically separating the high-frequency circuit on the chip mounting layer 41 from the drive line 19 in the internal wiring layer 44A is formed in the wiring layer 43.

The drive line 19 from the drive unit 12 is formed in the internal wiring layer 44A in the multilayer wiring layer 44, and is connected to the chip 67 on the chip mounting layer 41, ie, the phase circuits 17A to 17D via the via hole 36B. It is connected. In addition, as the multilayer wiring layer 44, for example, a build-up substrate in which a sheet-like thin substrate on which a wiring layer is formed may be used.

The dielectric layer 34 between the phase control layer 35 and the coupling layer 33 is a spacer 34 having a thickness (height) of 0.2 mm.
A chip 67 is mounted on the chip mounting layer 44 on the surface of the phase control layer 35.

In this case, the spacer 34A is
May be arranged below, so that the lower part of the slot 21, which is usually a vacant area, can also be used as the area where the spacer 34A is arranged, and the area occupied by the spacer 34A can be reduced. Furthermore, if a material having a high dielectric constant of about 5 to 30 such as alumina is used as the spacer 34A,
Slot 21 and strip line 16 on phase control layer 35
A is efficiently combined.

In this embodiment, the strip line 16A on the phase control layer 35 and the coupling slot 2 on the coupling layer 37 are used.
As a means for coupling the two, a coupling means (hereinafter simply referred to as a pseudo coaxial line) 46 having the same function as the coaxial line is used. The pseudo coaxial line 46 includes a via hole 16B through which a high-frequency signal flows, and a plurality of via holes 16D of a ground potential arranged around the via hole 16B to shield the high-frequency signal flowing through the via hole 16B.

The via holes 16D are connected to ground planes of the coupling layer 37 and the wiring layer 43, respectively. In the wiring layer 45, the strip line 16C connected to the via hole 16B is provided with the coupling slot 22 of the coupling layer 37.
Above. Thereby, the high-frequency signal from the coupling slot 22 is efficiently supplied to the strip line 16A via the strip line 16C and the via hole 16B.

FIG. 11 is an explanatory diagram showing a configuration example of a pseudo coaxial line. FIG. 11A shows a wiring pattern on the chip mounting layer 41 and the wiring layer 45 on the surface of the phase control layer 35, and the strip line 16A or 1A is formed in the via hole 16B.
6C is connected. In FIG. 11B schematically showing a cross section AA ′, a via hole 16B through which a high-frequency signal flows is shown.
, Six shield via holes 16D are arranged at substantially equal intervals.

On the other hand, FIG. 11C shows a pattern on the wiring layer 43. As described above, in this embodiment, the wiring layer 43 is used as a ground conductor, and the ground plane 43A is formed in this layer. This figure and FIG.
As shown in FIG. 1B, each via hole 16D is connected to the ground plane 43A at the same time as being connected to the ground plane 43A, and maintains the ground potential.

As shown in FIGS. 11D and 11E, a pattern 16E may be provided in the internal wiring layer 44A, and the via holes 16D may be connected by the pattern 16E.
This improves the shielding effect of the via hole 16D.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 12 is a circuit layout diagram showing the second embodiment, in which (a) is a circuit layout diagram of a phase control layer showing the entire phase shift unit, and (b) is a schematic diagram showing a multilayer structure. Hereinafter, an example in which the circuit unit shown in FIG. 7B, that is, all the phase shift circuits in the phase shift unit are integrated into one chip will be described.

Here, the dielectric layer 34 and the phase control layer 35
And the dielectric layer 36 is configured to be upside down from that of the first embodiment shown in FIG.
5, the wiring layer 45, the multilayer wiring layer 4
4, wiring layer 43, dielectric layer 42, and chip mounting layer 4
1 is also configured upside down. Therefore, the chip 67 is mounted from the chip mounting layer 41 on the surface of the phase control layer 35 to the dielectric layer 34 thereunder.

In this embodiment, as the spacer for forming the dielectric layer 34, a spacer 34B made of a conductor is used instead of the spacer 34A having a high dielectric constant.
In particular, the spacer 34B may be arranged below the via hole 42A to be electrically connected to a ground pattern, for example, the ground plane 43A of the wiring layer 43. Thereby, the unnecessary mode between the ground plates (parallel plate mode) can be suppressed without providing a means for coupling the ground potential separately.

FIGS. 13A and 13B are circuit layout diagrams showing the third embodiment, in which FIG. 13A is a circuit layout diagram of a phase control layer showing the entire phase shift unit, and FIG. 13B is a schematic diagram showing a multilayer structure. In the following, as in the first embodiment, an example will be described in which the circuit unit shown in FIG. 7A, that is, a switch used in each phase shift circuit is formed into a chip.

In this embodiment, the dielectric layer 34 is constituted by a dielectric substrate 34C. A chip 67 mounted on the phase control layer 35 is provided on the substrate 34C.
In the position, a cavity (space) 34 having a height of 0.2 mm
S is formed, and the chip 67 is placed in the cavity 34S when the substrate is in close contact.

As a method of forming the cavity 34S in the substrate 34C, a mechanical process of cutting the surface of the substrate 34C with a router or the like, or a mechanical process of forming a through hole by die cutting or the like may be used. After the photosensitive resin is applied to the organic substrate, the cavity 3 is exposed and exposed to light.
The resin of the 4S portion may be peeled off, and various forming methods can be used.

In the present embodiment, the wiring layer 45 on the surface of the multilayer wiring layer 44 is used as the coupling layer 37,
In the first embodiment, the separately formed layers are integrated, and at the same time, the required dielectric layer 36 and strip line 16C are deleted in the first embodiment.

Further, in this embodiment, instead of the pseudo coaxial line 46 used in the first embodiment, coupling means (hereinafter simply referred to as a pseudo slot) 47 having the same function as a coupling slot. Is used. The pseudo slot 47 includes a plurality of via holes 16 </ b> F having a ground potential arranged around the coupling slot 22. These via holes 16F are connected to the ground plane 37A of the coupling layer 37 in which the coupling slots 22 are provided and the strip line 1
It is connected to the ground plane 43A of the wiring layer 43 stacked one layer below the chip mounting layer 41 on which 6A is formed.

In each of the coupling layer 37 (wiring layer 45), the wiring layer 43, and the internal wiring layer 44A, since the conductor pattern is excluded from the region surrounded by the via hole 16F, the region surrounded by the via hole 16F is removed. Is composed of a dielectric in the multilayer wiring layer 44. Thus, the high-frequency signal from the coupling slot 22 is efficiently coupled to the strip line 16A on the chip mounting layer 41 via the pseudo slot 47.

FIG. 14 is an explanatory diagram showing a configuration example of a pseudo slot. FIG. 14A shows a wiring pattern on the chip mounting layer 41, in which a strip line 16A is arranged above a via hole 16F terminated by the wiring layer 43. In FIG. 14B schematically showing a cross section AA ′, around the coupling slot 22 of the coupling layer 37 (wiring layer 45),
Twelve shield via holes 16F are arranged at substantially equal intervals.

FIG. 14C shows a wiring pattern on the wiring layer 43 and the coupling layer 37 (wiring layer 45). The ground plane 43A or the ground plane 37A is connected to each via hole 16F. In addition, FIG.
As shown in (e), the pattern 16 is formed on the internal wiring layer 44A.
G may be provided to connect between the via holes 16F by the pattern 16G. In this case, the shielding effect by the via holes 16F is improved.

Next, a fourth embodiment of the present invention will be described with reference to FIG. 15A and 15B are circuit layout diagrams showing a fourth embodiment, in which FIG. 15A is a circuit layout diagram of a phase shift control layer showing the entire phase shift unit, and FIG. 15B is a schematic diagram showing a multilayer structure. In the following, as in the second embodiment, an example in which the circuit unit shown in FIG. 7C, that is, all the phase shift circuits in the phase shift unit are integrated into one chip will be described.

Here, as in the second embodiment, the phase shift control layer 35 and the dielectric layer 36 are arranged upside down, and as in the third embodiment, the pseudo coaxial line 46 is
, A pseudo slot 47 is used.

As described above, with reference to FIGS.
Although the case where a radial waveguide is adopted as 4 has been described, it goes without saying that the form shown in FIG. 4, that is, the distribution / combination layer 39 using a branch strip line may be used.

Further, as described above, the present invention can be applied to a different stacking order from the embodiment shown in FIGS. For example, the order of lamination is from bottom to top,
The phase control layer 35, the dielectric layer 36, the coupling layer 37, the dielectric layer 38, the distribution / combination layer 39, the dielectric layer 38A, the coupling layer 33,
As the dielectric layer 32 and the radiating element layer 31, the distribution / combination layer 39
May be arranged on the inner layer, and the phase control layer 35 may be arranged on the outer layer.

In this case, as an interlayer coupling means of the high frequency signal, for example, a power supply pin or a pseudo coaxial line penetrating a hole provided on the coupling layer 37 between the distribution / combination layer 39 and the phase control layer 35 is used. And the phase control layer 3
5 and the radiating element 15 also on the coupling layer 37 and the coupling layer 33.
The connection may be made at a high frequency by a feed pin or a pseudo coaxial line penetrating therethrough. By arranging the phase control layer 35 on the outside in this manner, a stacked configuration can be achieved regardless of the height of the chip 67.

Further, as shown in FIG. 17, if the radiation feeding section 27 is separately provided in addition to the multilayer substrate section 2 and the space feeding method is used, a layer functioning as the distribution / combination section 14 (FIG. 4).
9 and the radial waveguide in the embodiments of FIGS. 9 to 15) can be omitted from the multilayer substrate portion 2.

[0125]

As described above, according to the present invention, since the radiating element and the phase control means are formed in separate radiating element layers and phase controlling layers, respectively, and the entire structure is a multi-layer structure, at least the radiating element is radiated from the phase controlling layer. The elements are removed, reducing the area occupied by them on the phase control layer. Furthermore, by using a micromachine switch as the switching element used in the phase shift circuit, the area occupied by the switching element can be reduced as compared with the conventional case. Therefore, since a single phase shift unit can be configured with a relatively small area, a large number of radiating elements can be arranged in thousands at intervals (approximately 5 mm) optimal for a high-frequency signal of about 30 GHz. A phased array antenna applicable to the present invention can be realized.

Further, the circuit portion of each phase means which is repeatedly formed is mounted on the first substrate, and is mounted on the second substrate on which the phase control layer is formed. The number of components and the number of connection points are reduced as compared with the case where individual circuit components are individually mounted. Therefore, the number of assembling steps can be reduced, defect inspection can be performed on a single chip, and the yield of the entire phased array antenna can be improved. Particularly, in a high gain phased array antenna composed of thousands of phase shift units, , Can greatly reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phased array antenna according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration example of a multilayer substrate.

FIG. 3 is a block diagram showing a phase shift unit.

FIG. 4 is a timing chart illustrating an operation of a phase control unit.

FIG. 5 is a timing chart showing another operation of the phase control unit.

FIG. 6 is a perspective view illustrating a configuration example of a switch.

FIG. 7 is an explanatory diagram showing a bare chip mounting example.

FIG. 8 is an explanatory diagram showing an example of chip formation.

FIG. 9 is a circuit layout diagram showing the first embodiment.

FIG. 10 is a circuit layout diagram showing a configuration example inside a chip.

FIG. 11 is an explanatory diagram illustrating a configuration example of a pseudo coaxial line.

FIG. 12 is a circuit layout diagram showing a second embodiment.

FIG. 13 is a circuit layout diagram showing a third embodiment.

FIG. 14 is an explanatory diagram showing a configuration example of a pseudo slot.

FIG. 15 is a circuit layout diagram showing a fourth embodiment.

FIG. 16 is a diagram illustrating a configuration example of the present invention using a radial waveguide.

FIG. 17 is a diagram illustrating a configuration example of the present invention using a reflective space-fed phased array antenna.

FIG. 18 is a diagram illustrating a configuration example of a conventional phased array antenna.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Phased array antenna, 2 ... Multilayer board part, 11
... Control device, 12 ... Drive unit, 13 ... Power supply unit, 14
... Distributing and combining unit, 15 ... Radiation element, 15A parasitic element, 1
6: phase shift unit, 16A: strip line, 17: phase shifter, 17A to 17D phase shift circuit, 17S: switch, 1
9 drive line, 21, 22 coupling slot, 23 strip line, 31 radiating element layer, 31A parasitic element layer,
31B, 36: dielectric layer, 32, 34, 38: dielectric layer, 33: coupling layer (first coupling layer), 35: phase control layer, 37: coupling layer (second coupling layer), 39 ... Distribution synthesis layer, 67 ... chips.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01Q 21/06 H01Q 21/06 23/00 23/00 (72) Inventor Youichi Ara Shibago, Minato-ku, Tokyo 7-1-1, NEC Corporation (72) Inventor Hideki Soumitsu 5-7-1, Shiba, Minato-ku, Tokyo 7-1 No. F term in NEC Corporation (reference) 5J012 BA02 GA13 HA03 5J021 AA05 AA09 AA11 AB05 AB06 CA03 DB02 DB03 FA02 FA06 FA20 FA29 FA31 FA32 GA02 GA08 HA05 HA07 JA07 JA08 5J045 AA05 AB05 AB06 DA05 DA06 DA09 EA07 EA08 FA GA02 HA03 JA12 JA17 LA01 MA07 NA01 NA02

Claims (38)

[Claims] 1. A phased array antenna used for transmitting and receiving high-frequency signals such as microwaves and millimeter waves and adjusting the beam direction by controlling the phase of the high-frequency signals transmitted and received by each radiating element. A radiating element layer on which a radiating element is disposed, and a phase control layer on which phase control means for controlling the phase of a signal transmitted and received from each of the radiating elements is mounted. The means comprises: a plurality of driving means for outputting a control signal so as to give a predetermined amount of phase shift for each of the radiating elements; and a plurality of phase shifting means for receiving the control signal and controlling the phase of each of the radiating elements. Wherein a circuit portion of the circuit of each of the phase shifting means, which is configured repeatedly, is mounted on a first substrate, and the first substrate is mounted on a second substrate constituting the phase control layer. This And a phased array antenna. 2. The phased array antenna according to claim 1, wherein the phased array antenna includes a first coupling layer for coupling a high-frequency signal between the phase control layer and the radiation element layer. 3. A phased array antenna used for transmitting and receiving high-frequency signals such as microwaves and millimeter waves and adjusting the beam direction by controlling the phase of high-frequency signals transmitted and received by each radiating element. A phase control layer on which each phase control means for controlling the phase of a signal transmitted and received from the first unit is mounted, a first coupling layer for coupling high-frequency signals, a radiating element layer on which a large number of radiating elements are arranged, A first multilayer structure in which element layers are sequentially stacked, wherein the phase control means outputs a control signal to give a predetermined phase shift amount to each of the radiating elements, and the control signal And a plurality of phase shifting means for controlling the phase of each of the radiating elements upon receipt of the phase control layer. Configure A phased array antenna, wherein the first substrate is mounted on a second substrate. 4. The phased array antenna according to claim 1, wherein said phase control layer has a space of a predetermined height above a surface on which said phase control means is mounted. 5. The semiconductor device according to claim 1, wherein the phase control layer has a second multilayer structure including a plurality of wiring layers.
3. The phased array antenna according to 3. 6. The phased array antenna according to claim 1, further comprising a dielectric layer between each layer constituting said first multilayer structure. 7. The phased array antenna further comprises a distribution / combination unit that distributes a transmission signal to each of the phase control units and combines a reception signal from each of the phase control units. 3. The phased array antenna according to 3. 8. Each of the phase shift means is a plurality of phase shift circuits capable of receiving the output of the drive means and switching a distributed constant line having a length corresponding to a different phase shift amount by a high frequency switch. 4. The phased array antenna according to claim 1, wherein: 9. Each of the driving means receives a control data from a control device and distributes the control data to each of the predetermined radiating elements, and transmits the control signal to the predetermined radiating element. The phased array antenna according to any one of claims 1 to 3, comprising a plurality of phase control units for outputting. 10. The phased array antenna according to claim 9, wherein said driving means uses a flip chip. 11. The high-frequency switch electrically or magnetically operates a contact supported at a distance from a strip line to electrically connect the strip line to another strip line via the contact. 9. The phased array antenna according to claim 8, comprising a micromachine switch for connecting / disconnecting. 12. A second substrate on which a circuit portion of each of the phase shift means which is repeatedly formed is mounted, wherein a plurality of circuit portions of each of the phase shift means which are repeatedly formed are collectively formed on a unit basis. The phased array antenna according to any one of claims 1 to 3, wherein the first substrate is cut into a first substrate, and the first substrate is mounted as a chip on the second substrate. 13. The phased array antenna according to claim 12, wherein said chip mounts at least one high-frequency switch in said phase shift circuit. 14. The phased array antenna according to claim 12, wherein said chip mounts at least one of said phase shift circuits. 15. The chip is flip-chip mounted on a phase control layer in the form of a bare chip with an active element surface exposed, and a part or the entire periphery of the bare chip is adhered to the phase control layer with an adhesive. 13. The phased array antenna according to claim 12, wherein: 16. The chip is flip-chip mounted on a phase control layer in the form of a bare chip having an active element surface exposed, and is bonded to the phase control layer with an adhesive in a region other than the high-frequency switch on the active element surface. 13. The phased array antenna according to claim 12, wherein: 17. The phased array according to claim 12, wherein a bare chip having an active element surface exposed is stored in an LCC type or BGA type package and mounted on the phase control layer. antenna. 18. The radiating element according to claim 1, wherein the radiating element is a patch antenna or a slot antenna.
4. A phased array antenna according to any one of claims 1 to 3. 19. The distributing / combining unit includes a distributing / combining layer including a branch circuit using a strip line or a radial waveguide using a metal housing having an internal space, and the distributing / combining layer includes a second coupling. The phased array antenna according to claim 7, wherein the first multilayer structure is formed by being coupled to the phase control layer via a layer. 20. The phased array antenna according to claim 7, wherein said distribution / combination unit is a radiation feed unit provided separately from said first multilayer structure. 21. The phased array antenna according to claim 19, wherein the distributing / combining layers are coupled using coupling slots or conductive feed pins, respectively. 22. The phased array antenna according to claim 1, wherein a material of said second substrate is glass. 23. The phased array antenna according to claim 4, wherein the predetermined height is higher than a maximum height of a contact from a bottom surface of the micromachine switch. 24. The phased array antenna according to claim 4, wherein the predetermined height is secured by a dielectric spacer formed on the phase control layer. 25. The phased array antenna according to claim 24, wherein the dielectric spacer is provided below a coupling slot of the first coupling layer. 26. The phased array antenna according to claim 4, wherein said predetermined height is secured by a spacer of a conductor formed on said phase control layer. 27. The phased array antenna according to claim 4, wherein the predetermined height is secured by the chip formed on the phase control layer. 28. The phased array antenna according to claim 4, wherein the predetermined height is secured by a cavity provided on the phase control layer, from which a dielectric layer has been removed. 29. The second multilayer structure transmits a high-frequency signal using a pseudo coaxial line in which a plurality of grounded via holes are arranged around a strip line connecting the plurality of wiring layers. The phased array antenna according to claim 5, wherein 30. The phased device according to claim 5, wherein the second multilayer structure transmits a high-frequency signal using a pseudo slot in which a coupling slot is provided between the first coupling layer and the wiring layer. Array antenna. 31. A method according to claim 30, wherein a plurality of grounded via holes are provided around the coupling slot.
The described phased array antenna. 32. The method according to claim 29, wherein a region surrounded by the via hole is excluded from the conductor pattern.
32. The phased array antenna according to 32. 33. The method according to claim 1, wherein the driving means is provided at both ends of the phase control layer.
3. The phased array antenna according to 3, 9, 10. 34. A method for manufacturing a phased array antenna which is used for transmitting and receiving high-frequency signals such as microwaves and millimeter waves and adjusts the beam direction by controlling the phase of high-frequency signals transmitted and received by each radiating element. At least, a radiating element layer in which a large number of radiating elements are arranged, and a phase control layer in which a plurality of phase control means for controlling the phase of a signal transmitted and received from each radiating element are mounted in a chip form by photolithography technology or A method for manufacturing a phased array antenna, comprising forming a pattern by an etching technique, laminating the patterned layers in a predetermined order, and bonding the laminated layers. 35. A plurality of driving means for outputting a control signal so as to give a predetermined phase shift amount to each of the radiating elements, and controlling a phase of each of the radiating elements in response to the control signal. 35. The method for manufacturing a phased array antenna according to claim 34, comprising a plurality of phase shifting means. 36. The phase control layer is characterized in that a chip on which a circuit portion of the circuit of each of the phase shift means is mounted in advance is mounted on a first substrate constituting the phase control layer. The method for manufacturing a phased array antenna according to claim 35, wherein 37. The method according to claim 34, wherein the phase control layer is formed by forming a plurality of wiring layers in which wirings are formed in advance as a multilayer structure. 38. The chip, wherein a large number of repetitively configured circuit portions of the phase shift means are collectively formed, cut out in units of the large number of collectively formed circuit portions, and mounted on the second substrate. The method for manufacturing a phased array antenna according to claim 34, wherein: