JP2000195949A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent breaking of a barrier layer by laminating a wiring layer, consisting of a wiring having a specified thickness and a barrier layer with a thickness set to correspond to the thickness of the wiring into a multilayer. SOLUTION: A first wiring 24, a second wiring 27, a third wiring 30, a fourth wiring 33 and a fifth wiring 36 are laminated sequentially on a substrate 21 as a wiring having a specified thickness. A wiring layer consisting of a first barrier layer 23, a second barrier layer 26, a third barrier layer 29, a fourth barrier layer 32, a fifth barrier layer 35 and the like, each of which has a thickness set to correspond to each of the wiring 24, 27, 30, 33 and 36, respectively, are laminated into a multilayer. Thereby, even if electrical current flows concentratedly through each of the barrier layers 23, 26, 29, 32 and 35, breakdown the barrier layers 23, 26, 29, 32 and 35 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the miniaturization of wiring required for high speed and high integration of integrated circuit devices.
The present invention relates to an integrated circuit device on which wirings realizing thinning, low resistance, high current density, and high reliability are formed.

[0002]

2. Description of the Related Art At present, an LSI (large scale) is used.
In the integrated circuit, individual elements are increasingly miniaturized with the progress of processing technology. Therefore, it is necessary to increase the density, increase the number of layers, and reduce the thickness of the wiring. The current density is ever increasing.

In such a state, electromigration becomes a problem. This phenomenon is a breaking phenomenon of wiring caused by flowing a high-density current through the wiring, and the driving force is high. It is thought to be the movement and diffusion of metal atoms due to the collision of electron flow.

For example, considering a typical logic LSI,
In the 0.35 [μm] design rule, the density of the current flowing through the power supply line is 1 × 10 ⁵ [A / cm ² ], whereas in the 0.25 [μm] design rule, ,
According to the design rule of 3 × 10 ⁵ [A / cm ² ] and 0.18 [μm], it is considered to reach 1 × 10 ⁶ [A / cm ² ].

As described above, with the miniaturization of elements, the development of a highly reliable wiring material and wiring structure capable of flowing a higher density current is required.

Hitherto, Al has been widely used as an LSI wiring material because it is inexpensive and the process is easy. In recent years, Cu, Si, Ti, Pd or the like has been added to Al, or Al wiring has been used. High reliability has been realized by forming a layered structure in which the upper and lower layers are sandwiched by a high melting point metal called a barrier metal, for example, TiN, Ti, TiW, etc., and it has responded to miniaturization of wiring.

However, for the reasons described below, the use of Al as a wiring material in future integrated circuit devices has reached its limits.

(1) Reduction of operation delay due to wiring In order to maintain high-speed operation due to scaling of LSI, it is necessary to suppress an increase in delay due to wiring due to miniaturization. Materials, processes, circuits, layouts, etc. need to be improved.

From the viewpoint of materials, it is necessary to employ a low-resistance wiring material and a low dielectric constant interlayer insulating film material.
Has a specific resistance (1.7 [μΩ · cm]) of 3
Since it is as low as 7%, it is effective in reducing delay.

(2) Physical Limit of Al to Current Density Until now, the use limit of Al to increase the current density has been extended by the addition of other elements or the laminated structure of wiring. The current flowing through the wiring is 1 × 10 ⁶ [A / cm
² ], it is no longer possible to deal with such measures.

In general, Cu has a higher melting point than Al,
Since the self-diffusion energy is large, it is considered that the current density can be increased by one digit or more than that of Al by using Cu for the wiring.

Although an integrated circuit device using Cu for wiring has already been realized, it is necessary to make efforts to promote its practical use in the future.

By the way, since it is difficult to finely process Cu by applying a dry etching method, it is not possible to apply a process that has been frequently used for Al wiring. A damascene method or a dual damascene method in which a groove or a groove and a via hole is formed in an insulating film and Cu is buried in the groove or the groove and the via hole to form a wiring. Is applied.

In order to carry out the damascene method, it is necessary to bury Cu in a groove or a via hole having a high aspect ratio. Therefore, means described below have been developed.

In this method, a sputtering method is used to apply Cu
After the film is formed, the groove is filled by annealing at 350 ° C. or more.

Since the sputtering method has good coverage and it is difficult to embed a groove having a high aspect ratio, the embedding ability is limited to an aspect ratio (A / R: about 2).

A plating method is a method of embedding Cu by electroplating or electroless plating. In the electroplating method, Cu ions in a plating solution can be drawn to the bottom of a groove by an electric field, so that a high aspect ratio is obtained. Grooves having a ratio (A / R: 4 or more) can be buried, and the film formation speed is high, which is suitable for mass production.

However, in order to fill the grooves without gaps by plating, a seed layer having a uniform thickness in the grooves is indispensable, and the technique of forming the seed layers has a great effect.

[0019] CVD (chemical vapor)
(r deposition) method When the CVD method is used, trenches having a high aspect ratio can be buried with good coverage and without gaps.

However, since the film forming speed is generally low, there is a problem that the through put is poor and the production cost is high.

Up to now, as a technique for forming a Cu wiring, Al has been used.
Sputtering methods, which have a reputation for film quality in wiring, etc., have been studied in advance, but in the future, with the miniaturization of wiring, plating and CVD methods that can respond to filling high aspect ratio grooves will be developed. In order to reduce the increasing manufacturing cost of wiring, a dual damascene method capable of simultaneously forming wiring and a conductive plug at the time of embedding is necessary.

FIGS. 4 to 6 are cutaway side views of a main part showing an integrated circuit device at a key point in a process for explaining a standard process of the dual damascene method. I do.

4A. 4- (1) An interlayer insulating film 3 made of an oxide film is formed on the interlayer insulating film 1 on which the lower wiring 2 is formed.

4- (2) CMP (Chemical mechanical p)
By applying the above (olishing), the interlayer insulating film 3 is polished and flattened.

4 (B) 4- (3) A via hole 3V for forming a conductive plug is formed in the interlayer insulating film 3 on the lower wiring 2.

Referring to FIG. 5A, 5- (1) A wiring groove 3L for an upper wiring connected to the via hole 3V is formed in the interlayer insulating film 3.

Referring to FIG. 5B, 5- (2) Cu is easily diffused into the oxide film. Therefore, the barrier film 4 is formed on the entire surface including the via holes 3V and the wiring grooves 3L.

6 (A) 6- (1) C so that the inside of the via hole 3V and the inside of the wiring groove 3L are filled.
A u film 5 is formed.

6 (B) 6- (2) By applying the CMP method, the Cu film 5 and the barrier film 4 are polished to remove unnecessary portions, and the conductive plug 5P
Then, an upper layer wiring 5L is formed.

As described above, the wiring and the conductive plug by the dual damascene method are completed, but the role of the barrier layer 4 is not only to prevent Cu from diffusing into the interlayer insulating film 3. .

FIG. 7 is a cutaway side view of a main portion showing wiring for explaining a case where a void is generated. FIG. 8 is a diagram showing a relationship between generation of a void and a resistance value. The horizontal axis represents time, and the vertical axis represents resistance.

In FIG. 7, reference numeral 11 denotes a wiring, 11A denotes a void, and 12 denotes a barrier layer.

Here, when the material of the wiring 11 is, for example, Al, as shown in FIG. 7A, when no void is generated in the wiring 11, as shown in FIG. As described above, the wiring resistance is substantially constant and has a low value.

As shown in FIG. 7B, when a void 11A is generated in the wiring 11 due to electromigration, the wiring resistance increases as indicated by (b) in FIG. 8A. As shown in FIG. 7 (c), as the void 11A grows, the wiring resistance further increases as indicated by (c) in FIG. 8 (A).

However, since the current flowing through the wiring 11 flows through the upper and lower barrier layers 12 near the void 11A, the current does not cut off due to the open resistance.

Therefore, Al wiring failure due to electromigration does not lead to disconnection, but the increase in resistance from the initial resistance or the rate of increase in resistance becomes a criterion for failure determination. From time to failure is determined, that is, the ratio of the resistance rise time to the life of the entire wiring reaches 10% to 60%, which is not negligible.

However, in the case of the Cu wiring, particularly the dual damascene wiring, the resistance rise time is not seen as in the case of the Al wiring, and as shown in FIG. Failure often occurs.

The reason for this is that the current flowing before the generation of voids concentrates on the barrier layer after the generation of voids because the aspect ratio of the wiring is large, and the density of the current flowing through the barrier layer becomes extremely high. This is because the wire is broken by electromigration or melted by Joule heat.

The rate at which the current is concentrated on the barrier layer is determined by the ratio of the cross-sectional area of the barrier layer to the cross-sectional area (cross-sectional area in the transverse direction) of the entire wiring. Since the barrier layer having a constant thickness is formed without depending on the thickness, the characteristics of Cu having high electromigration resistance cannot be fully utilized originally.

[0040]

According to the present invention, even when a void is generated in a wiring having a barrier layer and a current flows intensively in the barrier layer, the barrier layer may be broken. To improve the reliability of wiring.

[0041]

According to the present invention, the basis is to adjust the cross-sectional area of the barrier layer corresponding to the cross-sectional area of the wiring including the barrier layer. This is effective when applied to, for example, an upper layer wiring in a multi-layer wiring, in which the aspect ratio is large, the wiring layer is thick and the line width is large.

As described above, in the integrated circuit device according to the present invention, (1) a wiring having a required thickness (for example, the first wiring 24, the second wiring 27, the third wiring 27, The third-layer wiring 30, the fourth-layer wiring 33, the fifth-layer wiring 36, and the like, and a barrier layer (for example, the first-layer barrier layer 23, the second layer, etc.) whose thickness is set according to the thickness of the wiring. A multilayer wiring formed by laminating a plurality of wiring layers including an eye barrier layer 26, a third barrier layer 29, a fourth barrier layer 32, a fifth barrier layer 35, etc. (for example, see FIG. 1). Or characterized by comprising
Or

(2) It is necessary to provide a multilayer wiring formed by laminating wiring layers each having a required width and a wiring layer including a barrier layer having a thickness corresponding to the width of the wiring. An integrated circuit device characterized by the following.

(3) Wiring (for example, first layer wiring 24, second layer wiring 27, third layer wiring 30, fourth layer wiring 3
Third, fifth-layer wiring 36, etc.) and barrier layers corresponding to the wiring (for example, first-layer barrier layer 23, second-layer barrier layer 26, third-layer barrier layer 29, fourth-layer barrier layer). 32,
In a multilayer wiring (for example, see FIG. 1) formed by laminating wiring layers composed of a fifth barrier layer 35, etc., the cross-sectional area of the barrier layer (for example, the first barrier layer 23) is equal to that of the wiring. The cross-sectional area of the first-layer wiring 24 and the cross-sectional area of the barrier layer (the first-layer barrier layer 23) are determined in accordance with the total cross-sectional area.

By taking the above measures, the high electromigration resistance in the barrier layer can be effectively used to break even if a situation occurs in which a void is generated in the wiring and current concentrates in the barrier layer. Is suppressed, so that the reliability of the entire wiring can be improved.

[0046]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cutaway side view showing a principal part of an integrated circuit device for explaining an embodiment of the present invention.

In the figure, reference numeral 21 denotes a substrate on which a necessary area in an integrated circuit device is formed, 22 denotes a first-layer interlayer insulating film, 23 denotes a first-layer barrier layer, and 24 denotes a first-layer wiring. , 2
5 is a second interlayer insulating film, 26 is a second barrier layer, 2
7 is a second-layer wiring, 28 is a third-layer interlayer insulating film, 29 is a third-layer barrier layer, 30 is a third-layer wiring, 31 is a fourth-layer interlayer insulating film, and 32 is a fourth-layer insulating film. An eye barrier layer, 33 indicates a fourth-layer wiring, 34 indicates a fifth-layer interlayer insulating film, 35 indicates a fifth-layer barrier layer, 36 indicates a fifth-layer wiring, and 37 indicates an insulating film.

As is clear from the drawing, it is necessary to supply a large current as a power supply line as the wiring becomes higher in the upper layer. Further, in order to keep the current density constant, the wiring becomes gradually thicker. The minimum line width is larger than that of the wiring in the lower layer, and the thickness of the upper barrier layer is correspondingly increased.

FIGS. 2A and 2B are cutaway side views of a main part showing a wiring structure at an important part of a process for explaining a case where a sputtering method is applied. FIG.
Indicates the case of the upper layer wiring, and the same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

FIG. 2A shows the first layer wiring 2 shown in FIG.
4 is described, and the minimum line width W ₁
Is 0.3 [μm], and the depth of the via hole + the depth of the wiring groove in the dual damascene structure = D ₁ is 1.2 [μm].
m] and the aspect ratio is 4.

Here, the flat portion (the periphery of the wiring groove and its vicinity) is obtained by applying the ionized sputtering method.
Barrier layer 2 made of Ta and having a thickness of 50 [nm]
3 is formed on the entire surface including the inside of the wiring groove and the inside of the via hole. Note that Ta can be replaced with TaN.

When the ionization sputtering method is applied, the average coverage on the side wall of the wiring groove is 60%, so that the thickness of the barrier layer 23 on the side wall of the wiring groove is 3%.
0 [nm].

FIG. 2B shows the fifth-layer wiring 3 shown in FIG.
6 is described, and the minimum line width W ₅
Is 0.7 [μm], the depth of the via hole in the dual damascene structure + the depth of the wiring groove + the thickness of the barrier layer = D
₅ is 2.5 [μm] and the aspect ratio is 3.57.

Similarly, by applying the ionization sputtering method, a barrier layer 35 made of Ta or TaN having a thickness of 100 [nm] at the flat portion is formed on the entire surface including the inside of the wiring groove and the inside of the via hole. Form a film.

As described above, when the ionization sputtering method is applied, the average coverage on the wiring groove side wall is 60 [%], and the thickness of the barrier layer 35 on the wiring groove side wall is 60 [nm]. .

Incidentally, in order to form a barrier layer, PVD (physical sputtering) such as ionization sputtering is used.
In addition to the l vapor deposition method,
A CVD method can also be applied.

Usually, the film formed by the PVD method has a thickness of 60% to 70% of the thickness of the flat portion on the side wall such as the wiring groove.
Although the thickness is [%], it is excellent in terms of mass productivity, stability, low cost, and film quality (low resistance value).
When the barrier layer is formed by the PVD method, the thickness can be easily calculated from the deposition rate of the barrier layer on the flat portion.

On the other hand, the film formed by the CVD method has a great feature in that it can be grown on the side wall such as the wiring groove to a uniform thickness which is not different from the thickness of the flat portion. The method and the CVD method may be appropriately used depending on the thickness required for the film formed on the side wall of the wiring groove as one guide. When a barrier layer is formed by either the PVD method or the CVD method, the thickness can be easily calculated from the deposition rate of the barrier layer on the flat portion.

FIGS. 3A and 3B are cutaway side views showing a main part of a wiring structure at an important part of a process for explaining a case where the CVD method is applied. FIG. 3A shows a lower wiring, and FIG. 3B shows an upper wiring. And the symbols used in FIG. 1 and the same symbols represent the same parts or have the same meanings.

FIG. 3A shows the first layer wiring 2 shown in FIG.
4 is described, and the minimum line width W ₁
Is 0.3 [μm], the depth of the via hole and the depth of the wiring groove in the dual damascene structure are 1.2 [μm], and the aspect ratio is 4.

Here, MOCVD (metalorga)
nic chemical vapor depos
The barrier layer 23 made of TiN having a thickness of 30 [nm] in the flat portion is obtained by applying the
Is formed on the entire surface including the inside of the wiring groove and the inside of the via hole.

When the MOCVD method is applied, as described above, the average coverage on the side wall of the wiring groove is about 100.
%, So that the barrier layer 23 covering the side wall of the wiring groove
Is 30 [nm].

FIG. 3B shows the fifth-layer wiring 3 shown in FIG.
6 is described, and the minimum line width W ₅
Is 0.7 μm, the depth of the via hole and the depth of the wiring groove in the dual damascene structure are 2.5 μm, and the aspect ratio is 3.57.

Similarly, by applying the MOCVD method, a barrier layer 35 made of TiN having a thickness of 60 nm at the flat portion is formed on the entire surface including the inside of the wiring groove and the inside of the via hole. .

When the MOCVD method is applied, as described above, the average coverage on the side wall of the wiring groove is about 100.
%, So that the barrier layer 35 covering the side wall of the wiring groove
Has a thickness of 60 [nm].

In the present invention, many modifications can be realized without being limited to the above-described embodiment. For example, as a film forming technique of the barrier layer, in the PVD method, not only the ionization sputtering method but also the collimation method is used. -Sputtering method, long-distance sputtering method in which the distance between the target and the substrate is at least 150 [mm] or more to make the thickness of the deposited layer uniform, low pressure in which the gas pressure during deposition is 1 × 10 ^-3 [Torr] or less A sputtering method or the like can be appropriately selected and applied.

Further, as described above with reference to FIGS. 7 and 8, in a wiring having a large cross-sectional area, current concentration on the barrier layer due to generation of voids in the wiring is caused by not only Cu wiring but also Cu wiring. Since this also occurs in the case of Al wiring, it is effective to implement the present invention in that case as well. The wiring material is not limited to Cu itself or Al itself, but may be a Cu alloy or an Al alloy.

Further, the wiring structure embodying the present invention is as follows:
The present invention is effective not only for the embedded wiring based on the damascene method but also for wiring obtained by processing a wiring material film by, for example, a dry etching method.

[0069]

In the integrated circuit device according to the present invention,
The barrier layer may be formed thicker in accordance with the thickness or width of each wiring constituting the multilayer wiring, or the cross-sectional area of the barrier layer may be increased as the cross-sectional area of the wiring including the barrier layer is increased.

By adopting the above configuration, the high electromigration resistance of the barrier layer is effectively used, and even if a situation occurs in which a void is generated in the wiring and current concentrates on the barrier layer, breakage occurs. Is suppressed, so that the reliability of the entire wiring can be improved.

[Brief description of the drawings]

FIG. 1 is a cutaway side view showing a main part of an integrated circuit device for explaining an embodiment of the present invention.

FIG. 2 is a cutaway side view of a main part showing a wiring structure in a main part of a process for explaining a case where a sputtering method is applied.

FIG. 3 is a cutaway side view of a main part showing a wiring structure in a main part of a process for explaining a case where a CVD method is applied.

FIG. 4 is a fragmentary side view showing an integrated circuit device at a key step for explaining a standard process of the dual damascene method.

FIG. 5 is a fragmentary sectional side view showing an integrated circuit device at a key step for explaining a standard process of the dual damascene method.

FIG. 6 is a fragmentary side view showing an integrated circuit device at a key step for explaining a standard process of the dual damascene method.

FIG. 7 is a cutaway side view of a main part showing wiring for describing a case where a void has occurred.

FIG. 8 is a diagram illustrating a relationship between generation of a void and a resistance value.

[Explanation of symbols]

 Reference Signs List 21 Substrate on which required area in integrated circuit device is formed 22 First-layer interlayer insulating film 23 First-layer barrier layer 24 First-layer wiring 25 Second-layer interlayer insulating film 26 Second-layer barrier layer 27 Second-layer wiring 28 Third-layer interlayer insulating film 29 Third-layer barrier layer 30 Third-layer wiring 31 Fourth-layer interlayer insulating film 32 Fourth-layer barrier layer 33 Fourth-layer wiring 34 Fifth interlayer insulating film 35 Fifth barrier layer 36 Fifth wiring 37 Insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB02 BB03 BB04 BB17 BB30 BB32 DD08 DD15 DD39 DD44 DD65 EE08 EE12 FF06 FF22 GG13 HH01 HH05 HH14 5F033 HH08 HH09 HH11 HH12 HH21 HH32 JJ33 JJ08 JJ08 JJ08 JJ08 KK11 KK12 KK21 KK32 KK33 MM02 MM12 MM13 MM28 MM29 PP06 PP11 PP15 QQ11 QQ48 RR00 TT01 WW01 WW02 XX04 XX05 XX28 XX30

Claims (3)

[Claims] 1. A multilayer wiring comprising a wiring having a required thickness and a wiring layer comprising a barrier layer whose thickness is set in accordance with the thickness of the wiring in a multilayer structure. An integrated circuit device characterized by the above-mentioned. 2. A multilayer wiring comprising a wiring having a required width and a wiring layer comprising a barrier layer whose thickness is set corresponding to the width of the wiring in a multilayer structure. Integrated circuit device. 3. A multilayer wiring in which a wiring and a wiring layer composed of a barrier layer corresponding to the wiring are stacked and formed, wherein a cross-sectional area of the barrier layer is a cross-sectional area of the wiring and a cross-sectional area of the barrier layer. An integrated circuit device, which is determined according to the size of the total cross-sectional area added.