JP2000183728A - Pld system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide PLD(programmable logic device) system where a PLD is surely initialized at application of power. SOLUTION: The PLD 1 is an aggregate of logic circuits where optional circuit functions can be realized. A power supply applies a voltage V1 to the PLD 1. A delay pulse circuit 3 gives an initializing signal V2 to a CONFIC terminal of the PLD 1 when a prescribed time elapses after the voltage V1 from the power supply 4 rises and the voltage V1 is settled. Every time a memory 2 receives a clock C from the PLD 1, the memory 2 gives serial data D to set a circuit function and the PLD 1 uses the data D and completes initializing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLD (Programmable Logic Device) which can smoothly set (initialize) a PLD (programmable logic device).

[0002]

2. Description of the Related Art Conventionally, there is a programmable logic device or a programmable logic circuit, a device called PLD for short. The PLD is a device that can arbitrarily write and set a function required by a user of the PLD and use the function, and is a set of logic circuits such as an AND circuit, an OR circuit, and a flip-flop circuit.
The PLD is often configured by an IC circuit such as a VLSI. As a technique using such a PLD, for example, Japanese Patent Publication No. 2779889 (title of the invention: programmable logic device), Japanese Patent Laid-Open No. 5-1201
Japanese Patent Application Laid-Open No. 58 (Title of Invention: Backup Memory Circuit) and Japanese Patent Application Laid-Open No. 5-120158 (Title of Invention: Control Device) are disclosed.

Hereinafter, a PLD device using this type of PLD will be described with reference to a configuration diagram of FIG. 3 and a signal timing diagram of FIG.

Referring to FIG. 3, this PLD device has a P
Memory 2 for writing function setting data to LD1 and PLD1
And a power supply 4 for supplying power to the PLD 1.

The PLD 1 includes, for example, E1, E2 data (for an audio channel) and D1 to OH (overhead) of an SDH (synchronous data hierarchy) device.
OW (order wire) that transmits and receives voice and data channels using D12 data (for data channels)
/ DCC (data channel transmission / reception) function. Commercial products having OW / DCC functions include FLEX8000 series P manufactured by Altera.
LD and the like. The PLD 1 receives power of the power supply voltage V1 from the power supply 4 as an interface terminal with the outside.
S terminal, GND terminal which is set to the ground potential, and CONFIG (initialization setting) for receiving an initialization setting signal of voltage V3
A terminal, a CK terminal for supplying a write clock C to the IN terminal of the memory 2, and a DATA terminal for receiving serial data D for setting the function of the PLD 1 from the OUT terminal of the memory 2 at the clock supply timing. . Note that the PLD 1 is used for signal input / output (I
/ O) terminal. In the PLD device of FIG. 3, the voltage V3, which is the initialization setting signal for the PLD1, is the same as the power supply voltage V1.

The memory 2 stores (stores) data for setting circuit functions required by the PLD 1.
EPROM (Electrically Erasable ROM) in Memory 2
Can be used.

Referring to FIG. 4, in this PLD device,
At time t0, PLD1 receives power supply voltage V1 (H) from power supply 4.
Is received by the PS terminal, the CONFIG terminal also receives the same voltage V3 (H) initialization setting signal at the same time t0. Thus, the CONFIG terminal has a voltage of 0 V
When the voltage changes from (L) to the voltage V3 (H), the PLD 1 supplies the clock C to the memory 2. Memory 2 uses clock C
At each input timing, serial data for function setting is sent to the DATA terminal of PLD1, written in PLD1, and a predetermined function is set in PLD1, and PLD1 completes initialization setting.

[0008]

In the above-described PLD device according to the prior art, if the rising waveform of the power supply voltage is poor when the power is turned on, the PLD fails to initialize (initialize operation) with the serial data and operates normally. There was a disadvantage that it could not be initialized. That is, there is noise in the rising waveform of the power supply voltage or the PLD
In the case where the power supply voltage has a stepwise rise near the threshold level of the normal operation, the PLD cannot be initialized by sharing the PLD initialization setting signal with the power supply voltage. Such a phenomenon is likely to occur when a switching control DC / DC converter or the like is used as the power supply.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a highly reliable PLD device which can solve the above-mentioned drawbacks of the conventional technology and can reliably perform initialization setting of a PLD. .

[0010]

A PLD device according to the present invention supplies a PLD capable of setting an arbitrary function and serial data for setting a circuit function to the PLD every time a clock is supplied from the PLD to the PLD. A power supply for supplying a power supply voltage to the PLD; and a PLD after a predetermined time elapses from the rise of the power supply voltage.
And an initialization setting signal delay circuit for supplying an initialization setting signal to the initialization setting terminal of the first embodiment.

[0011] One of the PLD devices may have a configuration in which the predetermined time is equal to or longer than a time for stabilizing the output power supply voltage.

[0012] Another one of the PLD devices may have a configuration in which the initialization setting signal delay circuit is inserted between the power supply and an initialization setting terminal of the PLD.

One of the PLD devices can have a configuration in which the initialization setting signal delay circuit is a logic signal delay circuit using a monomultivibrator. And
This PLD device can have a configuration in which the PLD has an OW / DCC function of transmitting and receiving voice and data channels using the overhead of the SDH device.

Another one of the PLD devices may have a configuration in which the initialization setting signal delay circuit is a passive delay circuit having a configuration in which the power supply voltage is not irregularly changed.

The most significant feature of the PLD device according to the present invention is that, when the PLD is initialized, the PLD is initialized by an initialization setting signal for a predetermined time until the power supply voltage is stabilized after the rise of the power supply voltage. Is forcibly delayed so that the initialization setting of the PLD can be surely executed.

[0016]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a PLD device according to the present invention. FIG. 2 is a timing chart of various signals in the PLD device of FIG.

Referring to FIG. 1, this PLD apparatus includes a PLD 1, a memory 2 and a power supply 4 described with reference to FIGS. 3 and 4, and a power supply voltage V1 output from an output terminal of the power supply 4 for a predetermined time. And a delay pulse circuit 3 for supplying the voltage V2 to the CONFIG terminal of the PLD1. The voltage V2 is a voltage required to initialize the PLD1. The PLD 1, the memory 2, and the power supply 4 are shown in FIG.
4 has the same configuration and function as those described with reference to FIG. 4, and a description of the same points will be omitted.

When the PLD 1 is initialized, the PLD 1 first receives a voltage V1 from the power supply 4 for causing the PLD 1 to perform a predetermined operation. Subsequently, after the elapse of the predetermined time, the CONFIG terminal of the PLD 1 is supplied with the voltage V2 from the delay pulse circuit 3, and the PLD 1 supplies the clock C, which is a serial pulse, from the CK terminal to the IN terminal of the memory 2. The memory 2 that has received the clock C from the PLD 1 writes the serial data D to be written for initialization of the PLD 1 from the OUT terminal to the DAT of the PLD 1
Output to A terminal.

Next, the initialization setting operation of the PLD device of FIG. 1 will be described in more detail with reference to FIG.

First, when the power supply 4 is turned on at time t0, the power supply voltage V1 rises. For example, when the power supply 4 is a switching-controlled DC / DC converter, a time of several milliseconds or more is required for the time from the rise of the voltage V1 to the stabilization of the predetermined operation voltage. Therefore,
When a switching control DC / DC converter is used as the power supply 4, the voltage V
A delay time of 1 requires several ms or more. The predetermined delay time of the delay pulse circuit 3 varies depending on the type of the power supply 4 and, of course, varies depending on the time until the operating voltage of the voltage V1 output from the power supply 4 is stabilized.

The delay pulse circuit 3 monitors the start of the rise of the voltage V1. The time until the voltage V1 stabilizes (the predetermined time = t1−t0) is set in advance as a delay value of the voltage V1. Therefore, the delay pulse circuit 3 calculates the rising start time t of the voltage V1.
After a lapse of a time t1 from 0 to the time when the voltage of the voltage V1 is stabilized, the voltage V2, which is the initialization setting signal of the PLD1, is changed to the LO level.
The signal is changed from W to HIGH and supplied to the CONFIG terminal of the PLD1. Note that the voltage V2 only needs to have a sufficient value as the initialization setting signal of the PLD1, and it is needless to say that the value may be the power supply voltage V1. Since the delay pulse circuit 3 uses a well-known logic signal delay circuit using a monomultivibrator, the voltage V1
The start of rising can be monitored.

If the time from the rising of the voltage V1 output from the power supply 4 to use to the stabilization (the above-mentioned predetermined time) is known in advance, the delay pulse circuit 3 uses a filter or the like to generate noise or stairs of the voltage V1. It can also be configured using a passive delay circuit having a delay of the above-mentioned predetermined time, such as a wiring path configured to eliminate irregular changes in the change.

When the voltage V2, which is an initialization setting signal, is supplied to the CONFIG terminal of the PLD1, the PLD1 receives the CK signal.
The clock C is supplied from the terminal to the IN terminal of the memory 2.
The memory 2 is turned on every time the clock C is input.
The serial data for function setting is sent from the UT terminal to the DATA terminal of the PLD1 and written to the circuit PLD1.
A predetermined function is set in LD1, and PLD1 completes the initialization setting.

As described above, in the PLD device of FIG. 1, after the power supply voltage V1 is sufficiently stabilized, the voltage V2, which is an initialization setting signal, is supplied to the CO, which is an external terminal of the PLD1 initialization signal.
Since the initialization setting is performed by supplying the signal to the NFIG terminal, there is an effect that error-free and more reliable initialization setting can be performed.

[0025]

As described above, the PLD according to the present invention
The apparatus comprises: a PLD capable of setting arbitrary functions;
A memory for supplying serial data for setting a circuit function to the PLD to the PLD every time a clock is supplied from the power supply, a power supply for supplying a power supply voltage to the PLD, and PL
Since an initialization setting signal delay circuit that supplies an initialization setting signal to the initialization setting terminal of D is provided, the PLD initialization setting can be performed after the predetermined time period during which the power supply is sufficiently stabilized, There is an effect that initialization can be reliably performed without error in the PLD.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a PLD device according to the present invention.

FIG. 2 is a timing chart of various signals in the PLD device of FIG. 1;

FIG. 3 is a configuration diagram of a conventional PLD device.

FIG. 4 is a timing chart of various signals in the PLD device of FIG. 3;

[Explanation of symbols]

 1 PLD (Programmable Logic Device) 2 Memory 3 Delay Pulse Circuit 4 Power Supply

Claims (6)

[Claims] 1. A PLD capable of setting an arbitrary function, a memory for supplying serial data for setting a circuit function to the PLD to the PLD each time a clock is supplied from the PLD, and a power supply voltage for supplying power to the PLD Power supply
A PLD device comprising: an initialization setting signal delay circuit that supplies an initialization setting signal to an initialization setting terminal of the PLD after a predetermined time has elapsed from the rise of the power supply voltage. 2. The PLD device according to claim 1, wherein the predetermined time is equal to or longer than a time for stabilizing the output power supply voltage. 3. The PLD device according to claim 1, wherein the initialization setting signal delay circuit is inserted between the power supply and an initialization setting terminal of the PLD. 4. The PLD device according to claim 3, wherein said initialization setting signal delay circuit is a logic signal delay circuit using a monomultivibrator. 5. The PLD device according to claim 4, wherein the PLD has an OW / DCC function for transmitting and receiving voice and data channels using the overhead of an SDH device. 6. The PLD device according to claim 3, wherein the initialization setting signal delay circuit is a passive delay circuit configured to eliminate irregular changes in the power supply voltage.