JP2000183299A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for eliminating capacity loss in an information accumulation capacitor for use with a silicon nitride film for a capacity insulation material. SOLUTION: A capacitor C for accumulating information is composed of an accumulation electrode 27 consisting of a doped polycrystalline silicon film, a capacity insulation film that is made of a silicon nitride film 28, and a plate electrode that is made of a titanium nitride film 29. By composing a plate electrode with the titanium nitride film 29, the depletion of the plate electrode is suppressed and the capacity loss of the capacitor C for accumulating information can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
The present invention relates to a semiconductor integrated circuit device having a random access memory (c) and a technology effective when applied to a manufacturing technology thereof.

[0002]

2. Description of the Related Art In one of semiconductor integrated circuit devices, a memory cell is a memory cell selecting MISFET (Metal Insulator).
There is a DRAM comprising a semiconductor field effect transistor) and an information storage capacitor element including a storage electrode and a plate electrode provided with a capacitor insulating film interposed therebetween. However, the DRAM has a problem that the memory cell is miniaturized with the increase in the capacity, the amount of charge stored in the information storage capacitor element is reduced, and the information holding characteristic is deteriorated.

Therefore, in a DRAM of 64 Mbit or more, a capacitor over bit line (Capacitor Over B) in which an information storage capacitor is arranged above a bit line.
It has an it line (COB) structure, and the storage electrode has a three-dimensional shape such as a cylindrical shape or a fin shape, thereby increasing the surface area to increase the amount of stored charge.

A memory cell composed of an information storage capacitor having a cylindrical storage electrode is described in, for example, "Super LSI Memory" published by Baifukan on November 5, 1994, written by Kiyo Ito, p. There is.

As the memory cell, for example, a gate electrode of a MISFET for selecting a memory cell is formed by a first conductive film deposited on a main surface of a semiconductor substrate, and a second conductive film deposited on the first conductive film is formed on the first conductive film. MISF for memory cell selection with film
A first plug reaching a pair of impurity semiconductor regions constituting a source and a drain of the ET is formed, and a MISFE for memory cell selection is formed by a third conductive film deposited on the second conductive film.
A bit line is formed above one impurity semiconductor region of T, and a first plug is formed above the other impurity semiconductor region of the memory cell selecting MISFET by a fourth conductive film deposited on the third conductive film. A second plug is formed through the first conductive film, and a storage electrode, which is a lower electrode of the information storage capacitor, is formed of the fifth conductive film deposited on the fourth conductive film, and deposited on the fifth conductive film. A structure in which a plate electrode which is an upper electrode of the information storage capacitor element is formed by the sixth conductive film is conceivable.

In the case where a silicon nitride film is used as the capacitive insulating film of the information storage capacitor, the fifth conductive film forming the storage electrode and the sixth conductive film forming the plate electrode of the information storage capacitor are formed of a covering material. Chemical Vapor Deposition (Chemical
It is composed of a polycrystalline silicon film to which an impurity, for example, phosphorus (P) is added by a vapor deposition (CVD) method.

[0007]

In the peripheral circuit, the first conductive film forming the gate electrode of the memory cell selecting MISFET forms the gate electrode of the MISFET, and the third conductive film forms the bit line. MISFE
A first layer wiring is formed inside a connection hole provided to reach a pair of impurity semiconductor regions constituting the source and drain of T. Further, a low-resistance silicide layer is provided between the impurity semiconductor region forming the source and the drain of the MISFET and the first layer wiring in order to reduce the connection resistance therebetween.

The above-mentioned silicide layer has relatively poor heat resistance. For example, in the case of a titanium silicide layer, if a heat treatment is performed at a temperature of 800 ° C. or more, connection resistance increases and problems such as poor conduction occur. Therefore, high-temperature heat treatment cannot be performed in the step after the formation of the silicide layer.

On the other hand, the fifth conductive film forming the storage electrode of the information storage capacitor and the sixth conductive film forming the plate electrode are formed of a polycrystalline silicon film to which impurities are added. In order to activate 100%, it is necessary to perform a heat treatment at a temperature of 700 ° C. or more.

However, in the peripheral circuit, in order to avoid a problem such as conduction failure due to an increase in the connection resistance due to deterioration of the heat resistance of the silicide layer, the impurity semiconductor region forming the source and drain of the MISFET and the first After the silicide layer is formed between the layer wiring and the layer wiring, a high-temperature heat treatment required to activate 100% of impurities in the polycrystalline silicon film cannot be performed. Therefore, the activation of impurities in the polycrystalline silicon film becomes insufficient, and the width of the depletion layer increases in the polycrystalline silicon film during operation, resulting in a loss of capacitance. This loss of capacity causes the refresh characteristics to deteriorate and the reliability of the memory cell to decrease.

An object of the present invention is to provide an information storage capacitor having a three-dimensional structure using a silicon nitride film as a capacitor insulating material.
An object of the present invention is to provide a technique capable of eliminating a capacity loss.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention includes an information storage capacitance element including a three-dimensional storage electrode and a plate electrode provided with a silicon nitride film having a thickness of 10 nm or less interposed therebetween. A memory cell, wherein the plate electrode is made of a metal film or a metal compound,
Further, the storage electrode is made of a polycrystalline silicon film, a metal film or a metal compound doped with impurities.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein a three-dimensional storage electrode and a film having a thickness of 10 nm are provided.
When forming a memory cell including a capacitor element for information storage constituted by a metal film or a plate electrode made of a metal compound provided with the following silicon nitride film interposed therebetween,
The metal film or metal compound constituting the plate electrode is formed by a chemical vapor deposition method at a temperature of 700 ° C. or less.

According to the above-mentioned means, in the information storage capacitance element using the silicon nitride film as the capacitance insulating material, the plate electrode is constituted by a metal film or a metal compound formed by a chemical vapor deposition method having good coverage. By doing
Since the depletion of the plate electrode does not occur, the capacitance loss of the information storage capacitance element can be reduced. Further, by forming the storage electrode from a metal film or a metal compound, depletion of both the plate electrode and the storage electrode does not occur, so that the capacity loss of the information storage capacitor can be eliminated.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a DR according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing AM. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In FIG. 1, an area A shows a part of a memory array, and an area B shows a part of a peripheral circuit.

On the main surface of a semiconductor substrate 1 made of p-type single crystal silicon, a p-type well 2 of a memory array, a p-type well 3 of a peripheral circuit and an n-type well 4 are formed.
Further, an n-type deep well 5 is formed so as to surround the p-type well 2. Note that a threshold voltage adjustment layer may be formed in each well.

An isolation region 6 is formed on the main surface of each well. The isolation region 6 is made of a silicon oxide film, and is formed in a shallow groove 7 formed on the main surface of the semiconductor substrate 1 via a thermally oxidized silicon oxide film 8.

On the main surface of the p-type well 2, MISFETs Qs for selecting a memory cell of a DRAM are formed. Also,
The main surfaces of the p-type well 3 and the n-type well 4 are respectively provided with an n-channel MISFET Qn and a p-channel MISFET Q
p is formed.

The memory cell selection MISFET Qs is p
A gate electrode 10 is formed on a main surface of the p-type well 2 via a gate insulating film 9, and an impurity semiconductor region 11 is formed on a main surface of the p-type well 2 on both sides of the gate electrode 10. The gate insulating film 9 is made of, for example, a silicon oxide film having a thickness of 7 to 8 nm and formed by thermal oxidation. The gate electrode 10 is made of, for example, a polycrystalline silicon film 10a having a thickness of 70 nm and titanium nitride (Ti
An N) film 10b and a 100 nm-thick tungsten (W) film 10c can be used as a laminated film. The impurity semiconductor region 11 has an n-type impurity such as arsenic (A
s) or phosphorus has been introduced.

A cap insulating film 12 made of a silicon nitride film is formed on the gate electrode 10 of the memory cell selecting MISFET Qs, and the cap insulating film 12 is further covered with a silicon nitride film 13. The silicon nitride film 13 is also formed on the side wall of the gate electrode 10 and is used for a self-alignment process when forming a connection hole described later. The gate electrode 10 of the memory cell selecting MISFET Qs functions as a DRAM word line, and a word line WL is formed on the upper surface of the isolation region 6.

On the other hand, the n-channel MISFET Qn
A gate electrode 10 formed on the main surface of the p-type well 3 via the gate insulating film 9 and an impurity semiconductor region 1 formed on the main surface of the p-type well 3 on both sides of the gate electrode 10
And 4. The gate insulating film 9 and the gate electrode 10 are the same as described above. The impurity semiconductor region 14 includes a low-concentration n ^{− -type} semiconductor region 14a and a high-concentration n ^{+ -type} semiconductor region 14b.
Drain) structure.

Similarly, the p-channel MISFET Qp
A gate electrode 10 formed on the main surface of the n-type well 4 and formed via the gate insulating film 9 and an impurity semiconductor region 15 formed on the main surface of the n-type well 4 on both sides of the gate electrode 10 Be composed. The gate insulating film 9 and the gate electrode 10 are the same as described above. The impurity semiconductor region 15 is composed of a low-concentration p ^{− -type} semiconductor region 15a and a high-concentration p ^{+ -type} semiconductor region 15b.
d Drain) structure.

A cap insulating film 12 made of a silicon nitride film is formed on the gate electrode 10 of the n-channel MISFET Qn and the p-channel MISFET Qp, and a sidewall spacer 16 made of, for example, a silicon nitride film is formed on the side surface. .

Memory cell selecting MISFET Qs, n-channel MISFET Qn and p-channel MISFET
Qp is covered with an interlayer insulating film 17. Interlayer insulating film 1
7 is, for example, an SOG (Spin On Glass) film 17a, TE
A silicon oxide film (hereinafter referred to as TEO) formed by plasma CVD using OS (tetraethoxysilane) as a source gas.
Chemical oxide polishing (Chemical Mechani)
TEO planarized by cal polishing (CMP)
It can be a laminated film of the S oxide film 17b, the TEOS oxide film 17c, and the silicon oxide film 17d.

On the interlayer insulating film 17, a bit line BL and a first layer wiring 18 (M1) are formed. Bit line B
L and the first layer wiring 18 (M1) are, for example, titanium (T
i) It can be a laminated film of the film 18a, the titanium nitride film 18b, and the tungsten film 18c. As a result, the resistance of the bit line BL and the first layer wiring 18 (M1) can be reduced, and the performance of the DRAM can be improved. Further, the bit line BL and the first layer wiring 18 (M1) are formed simultaneously as described later. Thereby, the process can be simplified.

The bit line BL is connected via a plug 19 to the impurity semiconductor region 11 shared by the pair of memory cell selecting MISFETs Qs. The plug 19 is, for example, n
It is possible to form a polycrystalline silicon film into which a shape impurity is introduced. Further, a titanium silicide (TiSi ₂ ) film 20 is formed at a connection portion between the plug 19 and the bit line BL. Thereby, the connection resistance between the bit line BL and the plug 19 can be reduced, and the connection reliability can be improved.

The first layer wiring 18 (M1) is connected to the impurity semiconductor region 14 of the n-channel MISFET Qn and the impurity semiconductor region 15 of the p-channel MISFET Qp via the connection hole 21. Also, the first layer wiring 18 (M1)
A titanium silicide film 20 is formed at the connection between the semiconductor region and the impurity semiconductor regions 14 and 15. Thereby, the connection resistance between the first layer wiring 18 (M1) and the impurity semiconductor regions 14 and 15 can be reduced, and the connection reliability can be improved.

The bit line BL and the first layer wiring 18 (M
1) is covered with a cap insulating film 22a made of a silicon nitride film and a sidewall spacer 22b, and further covered with an interlayer insulating film 23. The interlayer insulating film 23 is, for example, an SOG film 23a, TEO planarized by a CMP method.
It can be a laminated film of the S oxide film 23b and the TEOS oxide film 23c.

An information storage capacitor C is formed in the memory array above the interlayer insulating film 23. Further, an insulating film 24 is formed on the interlayer insulating film 23 of the peripheral circuit. The insulating film 24 can be, for example, a silicon oxide film. When the insulating film 24 is formed in the same layer as the information storage capacitor C, the step between the memory array and the peripheral circuit due to the elevation of the information storage capacitor C is reduced. Generation can be prevented. As a result, a sufficient depth of focus can be provided for photolithography, and the process can be stabilized to cope with fine processing.

In the impurity semiconductor region 11 opposite to the impurity semiconductor region 11 connected to the bit line BL via the plug 19 of the memory cell selecting MISFET Qs, the plug 1
A plug 25 made of the same layer as that of the plug 9 is connected. Further, an information storage capacitor C is formed above the plug 25 via the plug 26, and the information storage capacitor C is connected to the storage electrode 27 connected to the plug 26.
And a capacitance insulating film made of a silicon nitride film 28 and a plate electrode made of a titanium nitride film 29.

The storage electrode 27 is formed of a polycrystalline silicon film doped with impurities. In addition to a titanium nitride film, a metal film such as a tungsten film or a metal compound such as a tungsten nitride (WN) film can be used for the plate electrode.

On the upper layer of the information storage capacitor C, a second layer wiring 31 (M2) is formed via an insulating film 30 made of, for example, a TEOS oxide film. Second layer wiring 31 (M
2) is, for example, a titanium film 31a, aluminum (Al)
It can be a laminated film of the film 31b and the titanium nitride film 31c.

The second layer wiring 31 (M2) is connected to the first layer wiring 18 (M1) via a plug 32. Plug 3
2 may be a laminated film of, for example, an adhesive layer 32a composed of a laminated film of a titanium film and a titanium nitride film and a tungsten film 32b formed by a CVD method.

The second layer wiring 31 (M 2) is
3 and the second-layer wiring 31
A third layer wiring 34 (M3) similar to (M2) is formed. The interlayer insulating film 33 is, for example, a TEOS oxide film 33.
a, a laminated film of the SOG film 33b and the T4OS oxide film 33c. Further, the third layer wiring 34 (M3)
And the second layer wiring 31 (M2) are connected by a plug 35 similar to the plug 32.

Next, an example of a method of manufacturing a DRAM according to the present embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, a semiconductor substrate 1 made of a p-type silicon single crystal having a specific resistance of about 10 Ωcm.
And a shallow groove 7 is formed in the main surface of the semiconductor substrate 1. Thereafter, thermal oxidation is performed on the semiconductor substrate 1 to form a silicon oxide film 8. Further, a silicon oxide film is deposited and polished by the CMP method to leave the silicon oxide film only in the shallow groove 7, thereby forming the isolation region 6.

Next, an n-type impurity, for example, phosphorus is ion-implanted into the semiconductor substrate 1 in a region where a memory cell is to be formed (region A: memory array) to form a deep well 5, thereby forming a memory array and peripheral circuits (region B). ) (A region where the n-channel MISFET Qn is formed)
For example, boron (B) is ion-implanted to form p-type wells 2 and 3, and another part of the peripheral circuit (p-channel MI) is formed.
The n-type well 4 is formed by ion-implanting an n-type impurity, for example, phosphorus into a region where the SFET Qp is formed. Subsequent to the ion implantation, impurities for adjusting the threshold voltage of the MISFET, for example, boron fluoride (BF ₂ ) are ion-implanted into the p-type wells 2 and 3 and the n-type well 4. The deep well 5 is formed to prevent noise from entering the p-type well 2 of the memory array through the semiconductor substrate 1 from an input / output circuit or the like.

Next, as shown in FIG.
After cleaning the surfaces of the n-type well 3 and the n-type well 4 using a HF (hydrofluoric acid) -based solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C.
A clean gate insulating film 9 having a thickness of about 7 nm is formed on each surface of the substrate.

Next, gate electrodes 10A, 10B and 10C are formed on the gate insulating film 9. Gate electrode 10A
Constitutes a part of the memory cell selection MISFET Qs, and functions as a word line WL in a region other than the active region. The width of the gate electrode 10A (word line WL), that is, the gate length is configured to have a minimum dimension within an allowable range where the short channel effect of the memory cell selecting MISFET can be suppressed and the threshold voltage can be secured to a certain value or more. Is done. The interval between two adjacent gate electrodes 10A (word lines WL) has a minimum size determined by the resolution limit of photolithography. Gate electrode 10B and gate electrode 10C
Constitute part of each of the n-channel MISFET Qn and the p-channel MISFET Qp of the peripheral circuit.

For the gate electrode 10A (word line WL) and the gate electrodes 10B and 10C, a polycrystalline silicon film 10a having a thickness of about 70 nm doped with an n-type impurity such as phosphorus is deposited on the semiconductor substrate 1 by the CVD method. Then, a titanium nitride film 1 having a thickness of about 50 nm
0b and a tungsten film 10c having a thickness of about 100 nm are deposited by a sputtering method. Further, a film thickness of 1
After depositing a cap insulating film 12 of, for example, about 50 nm, for example, a silicon nitride film by a CVD method, the cap insulating film 12 is formed by patterning these films using a photoresist film as a mask. The titanium nitride film 10b functions as a barrier layer that prevents the tungsten film 10c and the polycrystalline silicon film 10a from reacting during high-temperature heat treatment to form a high-resistance silicide layer at the interface between the two. In the barrier layer,
In addition to the titanium nitride film, a tungsten nitride film or the like can also be used.

When a part of the gate electrode 10A (word line WL) is made of a low-resistance metal (tungsten),
Since the sheet resistance can be reduced to about 2 to 2.5Ω / □, the word line delay can be reduced. Also, since the word line delay can be reduced without backing the gate electrode 10A (word line WL) with aluminum wiring or the like,
The number of wiring layers formed above the memory cells can be reduced by one.

Next, after removing the photoresist film, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. When this wet etching is performed, the gate insulating film 9 in a region other than the lower portion of the gate electrode 10A (word line WL) and the gate electrodes 10B and 10C is shaved, and the gate insulating film 9 below the gate sidewall is also isotropically. Since the etching causes an undercut, the breakdown voltage of the gate insulating film 9 is reduced as it is. Therefore, the quality of the shaved gate insulating film 9 is improved by oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, a p-type impurity, for example, boron is ion-implanted into the n-type well 4 to form a p ^- type semiconductor region 15a in the n-type well 4 on both sides of the gate electrode 10C. Further, an n-type impurity, for example, phosphorus is ion-implanted into the p-type wells 2 and 3 to form p-type wells 3 on both sides of the gate electrode 10B.
An n ^- type semiconductor region 14a is formed on the gate electrode 10A.
Impurity semiconductor regions 11 are formed in the p-type wells 2 on both sides of the substrate. Thereby, the memory cell selection MI is stored in the memory array.
The SFET Qs is formed.

Next, as shown in FIG. 4, a silicon nitride film 13 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by a CVD method, and then the silicon nitride film 13 of the memory array is covered with a photoresist film. By anisotropically etching the silicon nitride film 13 of the circuit, the gate electrode 10B,
A side wall spacer 16 is formed on the side wall of 10C. This etching uses an etching gas that increases the etching rate of the silicon nitride film 13 with respect to the silicon oxide film in order to minimize the amount of the silicon oxide film buried in the gate insulating film 9 and the isolation region 6. Do it. Further, in order to minimize the shaving amount of the cap insulating film 12 composed of the silicon nitride film on the gate electrodes 10B and 10C, the over-etching amount is kept to a necessary minimum.

Next, after removing the photoresist film, a p-type impurity, for example, boron is ion-implanted into the n-type well 4 of the peripheral circuit to remove the p ⁺ -type semiconductor region 15b (source, drain) of the p-channel MISFET Qp. The n-channel MISFET Qn is formed by ion-implanting an n-type impurity, for example, arsenic into the p-type well 3 of the peripheral circuit.
^{A +} type semiconductor region 14b (source, drain) is formed. As a result, the p-channel MISFET Q
P and n channel MISFETs Qn are formed.

Next, as shown in FIG. 5, an SOG film 17a having a thickness of about 300 nm is spin-coated on the semiconductor substrate 1, and then the semiconductor substrate 1 is heat-treated at 800.degree.
The OG film 17a is sintered (burned).

Next, a film thickness of 600 is formed on the SOG film 17a.
After depositing a TEOS oxide film 17b of about nm,
The EOS oxide film 17b is polished by the CMP method to planarize the surface. The TEOS oxide film 17b is made of, for example, ozone (O
₃ ) and tetraethoxysilane are deposited by a plasma CVD method using a source gas.

Next, a TEOS oxide film 17c having a thickness of about 100 nm is deposited on the TEOS oxide film 17b. The TEOS oxide film 17c is deposited in order to repair fine scratches on the surface of the TEOS oxide film 17b generated when the surface is polished by the CMP method. The TEOS oxide film 17c is deposited by, for example, a plasma CVD method using ozone and tetraethoxysilane as a source gas. TEOS oxide film 17
b, PSG instead of TEOS oxide film 17c
(Phospho Silicate Glass) film may be deposited.

Next, a photoresist film 36 is formed on the TEOS oxide film 17c.
For memory cell selection by dry etching using
TEOS oxide films 17c, 17b and S over impurity semiconductor region 11 (source, drain) of ISFET Qs
The OG film 17a is removed.

Note that the above etching is performed on the TEOS oxide films 17c and 17b and the SO
The etching is performed under such a condition that the etching rate of the G film 17a is increased so that the silicon nitride film 13 covering the impurity semiconductor region 11 and the upper portion of the isolation region 6 is not completely removed.

Subsequently, the memory cell selection MISF is performed by dry etching using the photoresist film 36 as a mask.
ETQs impurity semiconductor region 11 (source, drain)
By removing the silicon nitride film 13 and the gate insulating film 9 in the upper part of the semiconductor device, a connection hole 37 is formed in one upper part of the impurity semiconductor region 11 (source and drain), and a connection hole 38 is formed in the other upper part. . This etching is performed under such a condition that the etching rate of the silicon nitride film 13 with respect to the silicon oxide film (the gate insulating film 9 and the silicon oxide film in the isolation region 6) is increased.
1 and the separation region 6 are not cut deeply. This etching is performed under such a condition that the silicon nitride film 13 is anisotropically etched so that the silicon nitride film 13 remains on the side wall of the gate electrode 10A (word line WL). As a result, the connection holes 37 and 38 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 10A.
(Word line WL) in a self-aligned manner. In order to form the connection holes 37 and 38 in a self-alignment manner with respect to the gate electrode 10A (word line WL), the silicon nitride film 13 is anisotropically etched in advance to form a side wall on the side wall of the gate electrode 10A (word line WL). A spacer may be formed.

Next, after removing the photoresist film 36, plugs 19 and 25 are formed inside the connection holes 37 and 38, respectively, as shown in FIG. Plug 19, 25
A polycrystalline silicon film doped with an n-type impurity (for example, phosphorus) is deposited on the TEOS oxide film 17c by a CVD method, and then the polycrystalline silicon film is polished by a CMP method to form the inside of the connection holes 37 and 38. To form.

Next, as shown in FIG. 7, a silicon oxide film 1 having a thickness of about 200 nm is formed on the TEOS oxide film 17c.
After depositing 7d, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 17d is formed, for example, by a plasma CV using ozone and tetraethoxysilane as a source gas.
It is a TEOS oxide film deposited by the D method. By this heat treatment, the n-type impurities in the polycrystalline silicon films forming plugs 19 and 25 are removed from the bottoms of connection holes 37 and 38 from impurity semiconductor region 1 of MISFET Qs for memory cell selection.
1 (source, drain) and diffused into the impurity semiconductor region 1
1 is reduced in resistance.

Next, the silicon oxide film 17d above the connection hole 37 is removed by dry etching using a photoresist film as a mask to expose the surface of the plug 19. Next, after removing the photoresist film, the silicon oxide films 17d, 17c, 17b, the SOG film 17a and the gate insulating film 9 of the peripheral circuit are removed by dry etching using the photoresist film as a mask, thereby forming an n-channel. The n ⁺ type semiconductor region 14b of the MISFET Qn (source,
Drain) and p-channel MISFET p
^A connection hole 21 is formed above the ⁺ type semiconductor region 15b (source, drain).

Next, after removing the photoresist film, as shown in FIG. 8, a bit line BL and a first layer wiring 18 (M1) of a peripheral circuit are formed on the silicon oxide film 17d. Bit line BL and first layer wiring 18 (M1)
Is, for example, a 50 nm-thick film on the silicon oxide film 17d.
A titanium film 18a having a thickness of about 50 nm and a titanium nitride film 18b having a thickness of about 50 nm are deposited by a sputtering method, and a tungsten film 18 having a thickness of about 150 nm is further formed thereon.
c and a silicon nitride film 22a having a thickness of about 200 nm
After deposition by the VD method, these films are formed by patterning these films using a photoresist film as a mask.

After depositing a titanium film on the silicon oxide film 17d, the semiconductor substrate 1 is subjected to a heat treatment at about 800 ° C., thereby forming the surface of the n ^{+ type} semiconductor region 14b (source, drain) of the n channel MISFET, the p channel MI
Plug 19 embedded in the surface of p ^{+ type} semiconductor region 15b (source, drain) of SFET and connection hole 37
, A low-resistance titanium silicide layer 20 is formed. Thereby, the connection resistance of the wiring (bit line BL, first layer wiring 18 (M1)) connected to n ^{+ type} semiconductor region 14b, p ^{+ type} semiconductor region 15b and plug 19 can be reduced. Further, since the bit line BL is made of a tungsten film / titanium nitride film / titanium film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the bit line BL and the first layer wiring 18 (M
1) can be simultaneously formed in the same step.

Next, after removing the photoresist film, sidewall spacers 22b are formed on the side walls of the bit line BL and the first layer wiring 18 (M1). The side wall spacer 22b is formed by depositing a silicon nitride film on the bit line BL and the first layer wiring 18 (M1) by the CVD method and then anisotropically etching the silicon nitride film.

Next, as shown in FIG. 9, an SOG film 23a having a thickness of about 300 nm is spin-coated on the bit line BL and the first layer wiring 18 (M1).
Is heat-treated at 800 ° C. for about 1 minute to sinter (bake) the SOG film 23a.

Next, a film thickness of 600 is formed on the SOG film 23a.
After depositing a TEOS oxide film 23b of about nm,
The EOS oxide film 23b is polished by the CMP method to planarize the surface. The TEOS oxide film 23b is formed, for example, by a plasma C using ozone and tetraethoxysilane as a source gas.
Deposit by VD method.

Next, a TEOS oxide film 23c having a thickness of about 100 nm is deposited on the TEOS oxide film 23b. This TEOS oxide film 23c is deposited in order to repair fine scratches on the surface of the TEOS oxide film 23b generated when the surface is polished by the CMP method. The TEOS oxide film 23c is deposited by, for example, a plasma CVD method using ozone and tetraethoxysilane as a source gas.

Next, the plug 25 embedded in the connection hole 38 by dry etching using a photoresist film as a mask
TEOS oxide films 23c and 23b and SOG film 23
a and the silicon oxide film 17d are removed to form a through hole 39 reaching the surface of the plug 25. This etching is performed under conditions such that the etching rate of the silicon nitride film with respect to the TEOS oxide films 23c and 23b, the silicon oxide film 17d, and the SOG film 23a is increased, and even when the misalignment between the through hole 39 and the bit line BL occurs. In addition, the silicon nitride film 22a and the sidewall spacer 22b on the bit line BL are prevented from being deeply cut. Thereby, through hole 39 is formed in self alignment with bit line BL.

Next, after removing the photoresist film, a plug 26 is formed inside the through hole 39.
The plug 26 is formed by forming a polycrystalline silicon film doped with an n-type impurity (for example, phosphorus) on the TEOS oxide film 23c by CV.
After the deposition by the method D, the polycrystalline silicon film is formed by etching back and leaving it inside the through hole 39.

Next, as shown in FIG. 10, a silicon nitride film 40 having a thickness of about 100 nm is deposited on the TEOS oxide film 23c by the CVD method, and the peripheral circuit is dry-etched using a photoresist film as a mask. The silicon nitride film 40 is removed. The silicon nitride film 40 remaining in the memory array is used as the storage electrode 27 of the information storage capacitor C described later.
Is used as an etching stopper when the silicon oxide film between the adjacent storage electrodes 27 is etched in the step of forming.

Next, after removing the photoresist film, an insulating film 24 having a thickness of about 1.3 μm is deposited on the silicon nitride film 40, and the insulating film 24 and the insulating film 24 are dry-etched using the photoresist film as a mask. Silicon nitride film 40
By removing the groove 4 above the through hole 39.
Form one. At the same time, a frame-shaped groove 41a surrounding the memory array is formed around the memory array. The insulating film 24 is made of, for example, TE deposited by plasma CVD using ozone and tetraethoxysilane as a source gas.
This is an OS oxide film.

Next, after removing the photoresist film, a polycrystalline silicon film 42 having a thickness of about 60 nm doped with an n-type impurity (for example, phosphorus) is
Deposition is performed at a temperature of about 600 ° C. using the VD method. This polycrystalline silicon film 42 is used as a storage electrode material of the information storage capacitor C.

Next, as shown in FIG. 11, an SOG film 43 having a thickness (for example, about 2 μm) thicker than the depth of the grooves 41 and 41 a is spin-coated on the polycrystalline silicon film 42, and then the SOG film 43 is formed. Is etched back, and the insulating film 24
By etching back the polycrystalline silicon film 42 above the polycrystalline silicon film 42, the polycrystalline silicon film 42 is left inside the grooves 41 and 41a (the inner wall and the bottom).

Next, the SOG film 43 inside the groove 41 and the insulating film 24 in the gap between the grooves 41 are wet-etched using a photoresist film covering the silicon oxide film 24 of the peripheral circuit as a mask, to thereby form the information storage capacitor C. Is formed. At this time, since the silicon nitride film 40 remains in the gap between the grooves 41, the TEOS oxide film 23c thereunder is not etched. Also, the insulating film 2 of the peripheral circuit
One end of the photoresist film covering the memory cell 4 is arranged at the boundary between the storage electrode 27 formed on the outermost side of the memory array and the peripheral circuit, that is, above the groove 41a. In this way, even if misalignment occurs at the end of the photoresist film, the SOG film 43 remains inside the groove 41 of the storage electrode 27 formed on the outermost side of the memory array,
The insulating film 24 of the peripheral circuit is not etched.

Next, as shown in FIG. 12, after removing the photoresist film, a film thickness of 10
A silicon nitride film 28 of about nm or less is deposited at a temperature of about 750 ° C. using a CVD method. This silicon nitride film 28
Is used as a material of a capacitive insulating film of the information storage capacitive element C. During the deposition of the silicon nitride film 28, the n-type impurity doped in the polycrystalline silicon film 42 is activated.

Next, a film thickness of 1
After depositing a titanium nitride film 29 of about 50 nm at a temperature of about 500 ° C. using a CVD method, the titanium nitride film 29 and the silicon nitride film 28 are patterned by dry etching using a photoresist film as a mask. A plate electrode made of a titanium nitride film 29, a capacitance insulating film made of a silicon nitride film 28,
An information storage capacitance element C composed of the storage electrode 27 made of the polycrystalline silicon film 42 is formed. Thus, a DRAM memory cell composed of the memory cell selection MISFET and the information storage capacitor C connected in series to the MISFET is formed.

Next, as shown in FIG. 13, a TEOS oxide film is deposited on the entire surface of the semiconductor substrate 1 to form an insulating film 30, and a connection hole connected to the first layer wiring 18 (M1) is opened in the peripheral circuit. Then, the plug 32 is formed. The plug 32 is formed by depositing an adhesive layer 32a made of a titanium film and a titanium nitride film on the entire surface of the semiconductor substrate 1, and further forming a blanket CV.
The tungsten film 32b can be formed by depositing the tungsten film 32b by the method D and then etching back the tungsten film 32b and the adhesive layer 32a. Note that the titanium film and the titanium nitride film can be formed by a sputtering method, but can also be formed by a CVD method. Further, a titanium film 31 is formed on the entire surface of the semiconductor substrate 1.
a, an aluminum film 31b and a titanium nitride film 31c are deposited by a sputtering method, and are patterned to form a second layer wiring 31 (M2).

Finally, a TEOS oxide film 33a, an SOG film 33b and a TEOS oxide film 33c are deposited to form an interlayer insulating film 33, and a plug 35 is formed in the same manner as the second layer wiring 31 (M2). By forming the three-layer wiring 34 (M3), the DRAM shown in FIG. 1 is almost completed. After that, a passivation film is deposited on the multilayer wiring and the uppermost wiring, but illustration thereof is omitted.

Next, a principal part sectional view of a semiconductor substrate showing the structure of another information storage capacitive element to which the present embodiment is applied will be described with reference to FIGS.

FIG. 14 shows the storage electrode 2 shown in FIG.
7 shows an information storage capacitive element C in which a projection 44 made of silicon grains is formed on the inner wall surface and the outer wall surface of the polycrystalline silicon film 42 constituting No. 7. The silicon nitride film 28 covering the protrusions 44 made of silicon grains formed on the inner and outer wall surfaces of the polycrystalline silicon film 42 forming the storage electrode 27 functions as a capacitance insulating material.

FIG. 15 shows the information storage capacitor C in which the insulating film 24 is partially buried above the silicon nitride film 40 in the gap between the adjacent storage electrodes 27 shown in FIG.
The silicon nitride film 28 covering a part of the inner wall surface and the outer wall surface of the polycrystalline silicon film 42 forming the storage electrode 27 functions as a capacitance insulating material.

FIG. 16 shows the storage electrode 2 shown in FIG.
7 shows an information storage capacitive element C in which a projection 44 made of silicon grains is formed on a part of the inner wall surface and the outer wall surface of the polycrystalline silicon film 42 constituting 7. The silicon nitride film 28 covering the protrusions 44 made of silicon grains formed on a part of the inner wall surface and the outer wall surface of the polycrystalline silicon film 42 constituting the storage electrode 27 functions as a capacitance insulating material.

FIG. 17 shows an information storage capacitor C in which the insulating film 24 is buried above the silicon nitride film 40 in the gap between the adjacent storage electrodes 27 shown in FIG. The silicon nitride film 28 covering the inner wall surface of the polycrystalline silicon film 42 constituting the storage electrode 27 functions as a capacitance insulating material.

FIG. 18 shows the storage electrode 2 shown in FIG.
7 shows an information storage capacitive element C in which a projection 44 made of silicon grains is formed on the inner wall surface of a polycrystalline silicon film 42 constituting No. 7. Projection 4 made of silicon grains formed on the inner wall surface of polycrystalline silicon film 42 constituting storage electrode 27
4 functions as a capacitance insulating material.

In this embodiment, the storage electrode 27
Is made of a polycrystalline silicon film doped with impurities, but may be made of a metal film (for example, a tungsten film) or a metal compound (for example, a titanium nitride film or a tungsten nitride film).

FIG. 19 shows a capacitor (i) in which the storage electrode and the plate electrode are formed of a metal film, and a capacitor (ii) in which the storage electrode is formed of a polycrystalline silicon film and the plate electrode is formed of a metal film. And the relationship between the capacitance ratio to the maximum capacitance and the voltage of the plate electrode in the capacitor (iii) in which the storage electrode and the plate electrode are formed of a polycrystalline silicon film.

In the capacitive element (iii), when the plate electrode is applied positively, the plate electrode is depleted, and when applied negatively, the storage electrode is depleted, and a capacitance loss occurs under any application conditions. In the capacitive element (ii), since the plate electrode is not depleted, when the plate electrode is applied negatively, a capacitance loss occurs due to depletion. In the capacitive element (i), since the plate electrode and the storage electrode do not deplete, no capacitance loss occurs under any application conditions.

As described above, according to the present embodiment, since the plate electrode is constituted by the titanium nitride film 29 formed by the CVD method having good covering properties, the depletion of the plate electrode does not occur, so that the information storage Capacitance loss of the capacitor C can be reduced. Further, the storage electrode 27
Is composed of a metal film (for example, a tungsten film) or a metal compound (for example, a titanium nitride film or a tungsten nitride film), so that the depletion of both the plate electrode and the storage electrode 27 does not occur. C capacity loss can be eliminated.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in this embodiment, the case where the present invention is applied to a DRAM has been described.
The present invention can be applied to a logic-embedded DRAM in which M and M are mounted, or any semiconductor integrated circuit device in which an information storage capacitor is mounted.

[0086]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, in the information storage capacitor having a three-dimensional structure using a silicon nitride film as the capacitor insulating material, the plate electrode is made of a metal film or a metal compound formed by a CVD method having good coverage. Accordingly, the depletion of the plate electrode does not occur, so that the capacitance loss of the information storage capacitor can be reduced. further,
By forming the storage electrode with a metal film or a metal compound, both the plate electrode and the storage electrode are not depleted, so that the capacity loss of the information storage capacitor can be eliminated.

Further, since it is possible to obtain an information storage capacitor element having no capacity loss, it is possible to enlarge the margin of the refresh characteristic in the DRAM, and it is possible to reduce the voltage and the power.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a DRAM having an information storage capacitor element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor according to an embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 8 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor element according to an embodiment of the present invention;

12 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a DRAM having an information storage capacitor according to an embodiment of the present invention; FIG.

13 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM having an information storage capacitor according to an embodiment of the present invention; FIG.

FIG. 14 is a cross-sectional view of a main part of a semiconductor substrate showing an information storage capacitor element according to an embodiment of the present invention;

FIG. 15 is a cross-sectional view of a main part of a semiconductor substrate showing an information storage capacitor according to an embodiment of the present invention;

FIG. 16 is a cross-sectional view of a principal part of a semiconductor substrate showing an information storage capacitor according to an embodiment of the present invention;

FIG. 17 is a cross-sectional view of a main part of a semiconductor substrate showing an information storage capacitor element according to an embodiment of the present invention;

FIG. 18 is a cross-sectional view of a main part of a semiconductor substrate showing an information storage capacitor according to an embodiment of the present invention;

FIG. 19 is a graph showing a relationship between a capacitance ratio to a maximum capacitance of a capacitor and a voltage of a plate electrode.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 p-type well 3 p-type well 4 n-type well 5 deep well 6 isolation region 7 shallow groove 8 silicon oxide film 9 gate insulating film 10 gate electrode 10A gate electrode 10B gate electrode 10C gate electrode 10a polycrystalline silicon film 10b titanium nitride film 10c tungsten film 11 impurity semiconductor regions 12 the cap insulating film 13 a silicon nitride film 14 doped semiconductor regions 14a n ^- type semiconductor region 14b n ⁺ type semiconductor region 15 the impurity semiconductor regions 15a p ^- type semiconductor region 15b p ⁺ -type semiconductor Region 16 Sidewall spacer 17 Interlayer insulating film 17a SOG film 17b TEOS oxide film 17c TEOS oxide film 17d Silicon oxide film 18 (M1) First layer wiring 18a Titanium film 18b Titanium nitride film 18c Tungsten film 1 Plug 20 Titanium silicide layer 21 Connection hole 22a Silicon nitride film 22b Sidewall spacer 23 Interlayer insulation film 23a SOG film 23b TEOS oxide film 23c TEOS oxide film 24 Insulation film 25 Plug 26 Plug 27 Storage electrode 28 Silicon nitride film 29 Titanium nitride film Reference Signs List 30 insulating film 31 (M2) second layer wiring 31a titanium film 31b aluminum film 31c titanium nitride film 32 plug 32a adhesive layer 32b tungsten film 33 interlayer insulating film 33a TEOS oxide film 33b SOG film 33c TEOS oxide film 34 (M3) Three-layer wiring 35 Plug 36 Photoresist film 37 Connection hole 38 Connection hole 39 Through hole 40 Silicon nitride film 41 Groove 41a Groove 42 Polycrystalline silicon film 43 SOG film 44 Made of silicon grains Projection A Memory array area B Peripheral circuit area WL Word line BL Bit line C Information storage capacitance element Qs Memory cell selection MISFET Qn n-channel MISFET Qp p-channel MISFET

Claims (7)

[Claims] A storage electrode having a three-dimensional shape and a film thickness of 10 nm.
A semiconductor integrated circuit device having a memory cell including an information storage capacitor constituted by a metal film or a plate electrode made of a metal compound provided with a silicon nitride film interposed therebetween. 2. The semiconductor integrated circuit device according to claim 1, wherein said storage electrode is a polycrystalline silicon film, a metal film, or a metal compound doped with an impurity. 3. The semiconductor integrated circuit device according to claim 1, wherein said metal film is a tungsten film, and said metal compound is a titanium nitride film or a tungsten nitride film. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein said storage electrode has a cylindrical structure, and wherein said silicon nitride film and said cylinder cover inner and outer wall surfaces of said cylindrical storage electrode. Wherein the silicon nitride film coated on a part of the inner and outer wall surfaces of the mold-type storage electrode, or the silicon nitride film coated on the inner wall surface of the cylindrical-type storage electrode functions as a capacitive insulating material. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein a protrusion made of silicon grains is formed on a surface of said cylindrical storage electrode in contact with said silicon nitride film. Circuit device. 6. The semiconductor integrated circuit device according to claim 1, wherein said memory cell has a capacitor-over-bit line in which said information storage capacitance element is arranged above a bit line. A semiconductor integrated circuit device comprising a DRAM cell having a structure. 7. A storage electrode having a three-dimensional shape and a thickness of 10 nm.
In the following method of manufacturing a semiconductor integrated circuit device for forming a memory cell having an information storage capacitor constituted by a metal film or a plate electrode made of a metal compound provided with a silicon nitride film interposed therebetween, 700 ° C. of the metal film or the metal compound constituting
A method for manufacturing a semiconductor integrated circuit device formed by a chemical vapor deposition method at the following temperature.