JP2000183189A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage device whose word line is hardly disconnected even if it is made fine, and its manufacturing method. SOLUTION: First and second active regions arranged at a specified interval in a first direction are defined by an element isolation structural body 2 formed on a surface of the substrate 1. A first floating gate electrode 30F formed of a conductive material is formed to extend from a first active region to the element isolation structural body 2. A second floating gate electrode formed of a conductive material is formed to extend from a second active region to the element isolation structural body. A dielectric insulation region is provided on the element isolation structural body 2 and connects a first floating gate electrode and a second floating gate electrode physically. A control gate electrode is continuously formed on the first and second floating gate electrodes and the insulation isolation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having an FET in which a floating gate electrode and a control gate electrode are stacked, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view of a conventional semiconductor memory device using a floating gate type FET. Field oxide film 101 is formed on the surface of silicon substrate 100. The field oxide film 101 defines active regions arranged in the horizontal direction in FIG. A floating gate type FET 110 is formed in each active region. The cross-sectional view shown in FIG. 6 is a cross-sectional view of the channel region 111 of the floating gate type FET cut along a plane orthogonal to the carrier moving direction. Therefore,
The source and drain regions are not shown in FIG.

On the channel region 111, a first gate insulating film 112, a floating gate electrode 113, a second
The gate insulating film 114 and the word line 115 are stacked. The word line 115 has a two-layer structure of a polysilicon film 115a and a tungsten silicide (WSi) film 115b. The floating gate electrodes 113 of two FETs adjacent to each other are separated from each other in a region on the field oxide film 101 therebetween. Word line 11
Numeral 5 is directly disposed on the field oxide film 101 in a region where the floating gate electrode 113 is divided.

[0004]

With the miniaturization of the semiconductor memory device, the area where the floating gate electrode 113 is divided becomes narrower. For this reason, in the divided region, the step coverage rate of the word line 115 may be reduced, or a crack may occur in the word line 115.
The reduction in the step coverage rate and the occurrence of cracks cause disconnection of the word line 115.

An object of the present invention is to provide a semiconductor memory device having a structure in which a word line is hardly disconnected even if it is miniaturized, and a method of manufacturing the same.

[0006]

In accordance with one aspect of the present invention, first and second active layers formed on a substrate surface, having an insulating property, and spaced apart in a first direction. An element isolation structure defining a region; a first floating gate electrode formed of a conductive material and extending from the first active region to above the element isolation structure; and the second active region And a second floating gate electrode formed of a conductive material, and formed of an insulating material, provided on the element isolation structure, and provided on the element isolation structure. An insulating isolation region for physically connecting an electrode and a second floating gate electrode; and a conductive material continuously formed on the first and second floating gate electrodes and the insulating isolation region. Semiconductor memory device having a control gate electrode made of is provided.

An insulating isolation region is arranged between the first and second floating gate electrodes adjacent to each other.
The step on the base surface of the control gate electrode is lower than when the first floating gate electrode and the second floating gate electrode are physically separated. Therefore, the occurrence of disconnection of the control gate electrode can be suppressed.

According to another aspect of the present invention, there is provided a semiconductor substrate having a main surface, and a plurality of floating gate type FETs formed on the main surface of the semiconductor substrate.
ETs are arranged in a matrix on the main surface, and the FET in which the source region, the channel region, and the drain region of each FET are arranged in the row direction, and the plurality of FETs are electrically separated in the column direction. And two Fs arranged on the element isolation structure and arranged in the column direction.
Each of the FETs having an insulating isolation region that contacts the mutually facing end surfaces of the floating gate electrodes of the ET, ensures electrical insulation between the two floating gate electrodes, and physically connects the two. A semiconductor memory device in which the control gate electrode is connected to the control gate electrode of another FET adjacent in the column direction via the insulating isolation region.

An insulating isolation region is arranged between floating gate electrodes adjacent to each other. As compared with the case where the floating gate electrode is physically separated, the step on the underlying surface of the word line is reduced. Therefore, occurrence of disconnection of the word line can be suppressed.

According to another aspect of the present invention, a step of forming an element isolation structure on a main surface of a semiconductor substrate such that active regions are arranged at a certain interval in a first direction; Forming a first gate insulating film on the surface of the first conductive film, forming a first conductive film so as to cover the first gate insulating film and the element isolation structure, Selectively insulating a portion of the film, wherein the insulating film partially insulates a portion of the element isolation structure between the active regions arranged in the first direction; A step of forming a second gate insulating film on at least a non-insulating region of the surface of the first conductive film that has been materialized, and forming a second gate insulating film on the substrate so as to cover the second gate insulating film. Forming a second conductive film over the entire surface; Forming a gate line composed of these layers by patterning a layered structure up to the first conductive film, wherein the gate line extends in the first direction and is formed on the active region. Forming a gate line so as to pass through, and a step of adding a dopant to a region of the active region on both sides of the gate line to form a source region and a drain region. Is provided.

On the base surface of the second conductive film, the first conductive film and a region formed by insulating the first conductive film are formed. As compared with the case where the first conductive film is patterned, the step on the base surface is reduced. Therefore, a decrease in the step coverage ratio of the second conductive film can be suppressed. Disconnection of an upper layer portion of a gate line formed by patterning the second conductive film can be prevented.

[0012]

FIG. 1 is a plan view of a semiconductor memory device according to a first embodiment of the present invention. The active region 10 is formed by the element isolation structure formed on the surface of the silicon substrate.
Is defined. The active region 10 includes a plurality of row direction regions 10a extending in the row direction (horizontal direction) of FIG. 1 and a plurality of column direction regions 10b extending in the column direction (vertical direction). The row direction area 10a is arranged at a certain interval in the column direction. The column direction area 10b crosses each of the row direction areas 10a.

Gate lines 20 are arranged on both sides of each column direction region 10b. The gate line 20 has a structure in which a floating gate line and a word line are stacked. Each gate line 20 crosses the row direction region 10a,
A floating gate type field effect transistor (FET) 30 is formed at the intersection. Part of the word line and part of the floating gate line forming the gate line 20 also serve as the control gate electrode 30G and the floating gate electrode 30F of the floating gate type FET 30, respectively. A drain region 30D and a source region 30S are arranged in regions on both sides of the gate line 20 in the row direction region 10a.

The column direction region 10b intersects the row direction region 10a in the source region 30S. The drain region 30D and the column direction region 10b are connected to an upper wiring via contact holes 40 and 41, respectively.

FIG. 2A is a dashed line A2-A2 in FIG.
FIG. An element isolation structure 2 is formed on the surface of a silicon substrate 1, and a row direction region 10a of an active region
Is defined. The element isolation structure 2 has a thickness of 40 formed by, for example, a silicon local oxidation (LOCOS) method.
It is a field oxide film of 0 to 800 nm.

On the surface of the row direction region 10a, a thickness of 10 n
m first gate insulating films 10I are formed. First
The gate insulating film 10I is formed by, for example, thermal oxidation. On the first gate insulating film 30I and the element isolation structure 2, a floating gate line 21 extending in the lateral direction of FIG. 2A is formed. The floating gate line 21 constitutes a floating gate electrode 30F made of polysilicon above the first gate insulating film 30I, and above the element isolation structure 21, an insulating isolation region 31
Is configured.

The floating gate electrode 30F extends over the element isolation structures 2 on both sides thereof. The insulating isolation region 31 is provided on both sides of the floating gate electrode 30F.
Contact the mutually opposing end faces and physically connect the two. The insulating isolation region 31 is formed of, for example, SiO ₂ ,
The floating gate electrodes 30F on both sides are electrically insulated from each other.

A step is formed at the junction between the insulating isolation region 31 and the floating gate electrode 30F so that the upper surface of the insulating isolation region 31 is slightly higher than the upper surface of the floating gate electrode 30F.

The upper surface of the floating gate electrode 30F is covered with a second gate insulating film 30J having a thickness of 20 nm. The second gate insulating film 30J is formed, for example, by thermally oxidizing the upper surface of the floating gate electrode 30F.

The word line 22 is formed on the second gate insulating film 30J and the insulating isolation region 31. The word line 22 has a two-layer structure including a polysilicon film 22A having a thickness of 150 nm and a WSi film 22B having a thickness of 170 nm.
The portion of the word line 22 above the row direction region 10a also serves as the control electrode 30G. As shown in FIG. 2B, an interlayer insulating film and an upper layer wiring are formed above the word line 22.

FIG. 2B is a dashed line B2-B2 of FIG.
FIG. In the active region 10 defined on the surface of the silicon substrate 1, the drain region 30D and the source region 3 are arranged in the lateral direction (the row direction in FIG. 2) of FIG.
OS and the drain region 30D are arranged in this order at a certain interval. A channel region 30C is defined between the drain region 30D and the source region 30S.

The drain region 30D is formed, for example, by ion-implanting As under the conditions of an acceleration energy of several tens keV and a dose of 1 × 10 ¹⁵ cm ⁻² . The source region 30S is, for example, P is accelerated energy of several tens keV,
It is formed by implanting ions under the condition of a dose of 1 × 10 ¹⁴ cm ⁻² , and further implanting As under the same conditions as the drain region 30D. By ion implantation of P, an n ⁻ region is formed between the n-type region and the substrate. This n ⁻ region increases the breakdown voltage between the source region 30S and the substrate.

On the channel region 30C, a first gate insulating film 30I, a floating gate electrode 30F,
Gate insulating film 30J and control gate electrode 3
0G are stacked in this order. A side wall insulating film 30W is formed on a side surface of the laminated structure.
The sidewall insulating film 30W is formed by chemical vapor deposition (CV).
After depositing a 200 nm thick SiO ₂ film by D),
This SiO ₂ film is formed by anisotropic etching.

An interlayer insulating film 50 is formed so as to cover the surface of silicon substrate 1, control gate electrode 30G, and sidewall insulating film 30W. A contact hole 40 is formed in the interlayer insulating film 50 at a position corresponding to the drain region 30D. Bit line 52 is formed on interlayer insulating film 50. Bit line 52 is arranged along row direction region 10a shown in FIG. 1, and is connected to corresponding drain region 30D via contact hole 40.

Another interlayer insulating film 51 is formed on interlayer insulating film 50 so as to cover bit line 52. Contact holes 42 are formed in the interlayer insulating films 50 and 51 at positions corresponding to the control gate electrodes 30G.

On the interlayer insulating film 51, a word auxiliary wiring 4
6 are formed. The word auxiliary wiring 46 is arranged along the gate line 20 shown in FIG.
2, and is connected to a corresponding control gate electrode 30G. Note that an intermediate electrode for connecting the control gate electrode 30G and the word auxiliary wiring 46 may be formed in the wiring layer of the bit line 52.

Referring to FIG. 3, a method of manufacturing the semiconductor memory device according to the first embodiment will be described. FIGS. 3A and 3B are cross-sectional views corresponding to FIG. 2A of the first embodiment.

As shown in FIG. 3A, the element isolation structure 2 is formed on the surface of a p-type silicon substrate 1 by using a known technique.
Is formed to define the active region 10a. Active area 10a
Is thermally oxidized to form a first gate insulating film 30I having a thickness of 10 nm.

A polysilicon film 21a having a thickness of 130 nm is deposited by CVD so as to cover the first gate insulating film 30I and the element isolation structure 2. The substrate is heated in a mixed atmosphere of PCl ₃ and O ₂ to introduce P into the polysilicon film 21a. A resist pattern 47 having an opening above the element isolation structure 2 between the plurality of row direction regions 10a shown in FIG. 1 is formed. Instead of the resist pattern 47, a hard mask pattern of an insulating film may be formed.

Using the resist pattern 47 as a mask, O ⁺ ions are implanted into the polysilicon film 21a. O ⁺ ions are implanted using a high beam current ion implanter of about 80 to 100 mA. The ion implantation conditions include an acceleration energy of 50 to 100 keV and a dose of 1 × 10 ¹⁷ to 2 ×.
10 ¹⁸ cm ^-2 . During the ion implantation period, the substrate temperature is set to 500 to 60 to recover the damage caused by the implantation.
0 ° C. This O ⁺ ion implantation technology is based on SIM
This is an application of a technique used for forming an OX substrate.
After the implantation of the O ⁺ ions, the resist pattern 47 is removed.

As shown in FIG. 3B, the surface of the polysilicon film 21a is thermally oxidized to form a second gate insulating film 30J having a thickness of 20 nm. At this time, in the step of FIG. The implanted oxygen atoms diffuse and react with silicon,
An insulating isolation region 31 is formed.

On both sides of the insulating isolation region 31, a polysilicon region 30Fa made of the polysilicon film 21a remains. Each polysilicon region 30Fa is insulated from another polysilicon region 30Fa by the insulating separation region 31. The polysilicon film 21a having a thickness of 130 nm is oxidized to form SiO ₂
If it is a film, its thickness will be about 200 nm. However,
Since the upper layer portion of the polysilicon film 21a is sputtered and cut by about 10 to 20 nm at the time of implanting O ⁺ ions, the thickness of the insulating isolation region 31 is about 180 to 190 nm. Therefore, a step is formed at the boundary between the insulating isolation region 31 and the polysilicon region 30Fa such that the upper surface of the insulating isolation region 31 is higher than the upper surface of the second gate insulating film 30J by about 30 to 40 nm.

On the second gate insulating film 30J and the insulating isolation region 31, a 150 nm-thick polysilicon film 22Aa is formed.
And a 170 nm thick WSi film 22Ba is deposited. P is added to the polysilicon film 22Aa as in the case of the polysilicon film 21a. The WSi film 22Ba is deposited using SiH
₄ and CVD using WF ₆ . Instead of the WSi film 22Ba, another refractory metal silicide film, for example, a titanium silicide (TiSi) film, a tantalum silicide (TaSi) film, or the like can be used.

From the polysilicon film 21a to the WSi film 22B
The laminated structure up to a is patterned into the shape of the gate line 20 in FIG. WSi film 22Ba, polysilicon film 22
Aa and the etching of the polysilicon film 21a are performed using Cl
_This is performed by reactive ion etching (RIE) using ₂ and O ₂ . At this time, since the insulating separation region 31 is not etched, the insulating separation region 31 remains in a portion other than the cross section in FIG. 3B, but there is no problem in function.

Through the above-described steps, the floating gate electrode 30F and the second gate insulating film 30 shown in FIG.
J, a word line 22 is formed. The portion from the sidewall insulating film 30W to the bit line 52 shown in FIG. 2B is formed by using a known CVD, photolithography, and etching technique.

In the first embodiment, as shown in FIG. 2A, floating gate type FETs adjacent to each other
Of the floating gate electrode 30F
1 are physically connected. This connection has 3
Although a step of 0 to 40 nm is formed, this step is smaller than the step of 130 nm without the insulating isolation region 31. For this reason, it is possible to prevent the step coverage rate of the word line 22 from lowering and prevent the occurrence of cracks in the word line 22. For this reason, the occurrence of defects due to the disconnection of the word line 22 can be reduced.

FIG. 4 is a sectional view of a semiconductor memory device according to the second embodiment. The plan view of the semiconductor memory device according to the second embodiment is similar to the plan view of the semiconductor memory device according to the first embodiment shown in FIG. FIG. 4 is a dashed line A of FIG.
It is sectional drawing in 2-A2.

In the first embodiment, as shown in FIG. 2A, the insulating isolation region 31 is composed of one SiO ₂ region. In the second embodiment, as shown in FIG. 4, the insulating isolation region 31 includes a first SiO ₂ region 31A, a silicon region 31C, and a second SiO ₂ region 31B. First and second SiO ₂ regions 31A and 31B
Are sandwiching the silicon region 31C. Other configurations are the same as those of the semiconductor memory device of the first embodiment.

In order to form the insulating isolation region 31 of the second embodiment, the opening of the resist pattern 47 of the first embodiment shown in FIG. 3A is formed by the first and second SiO ₂ regions 31A.
And 31B.

In FIG. 2A, when the interval between the floating gate electrodes 30F adjacent to each other is 1 μm or more, the thickness of the insulating isolation region 31 tends to vary. If the thickness of the insulating isolation region 31 varies, the flatness of the underlying surface of the word line 22 is impaired.

In the second embodiment, as shown in FIG.
The iO ₂ region is localized and disposed near the edge of the element isolation region 2. For example, when the interval between two floating gate electrodes 30F is 1 μm, the first and second
The length of the SiO ₂ regions 31A and 31B is 0.3 μm, and the length of the silicon region 31C is 0.4 μm. Since the upper surface of the silicon region 31C is almost flat,
_{Even if} the film thickness varies between the _two regions, the region where the film thickness varies is localized. Therefore, the word line 22
The flatness of the base surface can be secured to some extent.

In the first embodiment, by oxidizing the polysilicon film, the insulating isolation region 3 shown in FIG.
1 was formed. In the third embodiment described below, the insulation isolation region 3 is formed by oxidizing the amorphous silicon film.
Form one.

In the step shown in FIG. 3A, an amorphous silicon film having a thickness of 90 nm is formed instead of forming the polysilicon film 21a. The formation of the amorphous silicon film can be performed by CVD using SiH ₄ and PH ₃ . The thickness of the SiO ₂ film formed by oxidizing a 90 nm thick amorphous silicon film is about 150
nm. Actually, the amorphous silicon film is shaved by about 10 to 20 nm during the implantation of O ⁺ ions, so that the thickness of the insulating isolation region 31 shown in FIG.
40 nm. Therefore, the second gate insulating film 30J
Between the gate and the insulating isolation region 31 is 20 to 30 nm.

When the surface of the amorphous silicon region 30Fa is oxidized to form the second gate insulating film 30J,
Amorphous silicon is polycrystallized to form a polysilicon film. Second gate insulating film 30J and insulating isolation region 31
Amorphous silicon film 22 having a thickness of 120 nm
Aa is formed, and a 150 nm thick WSi film 22 is formed thereon.
Ba is formed. Subsequent steps are the same as in the first embodiment.

In the third embodiment, the step at the boundary between the floating gate electrode 30F and the isolation region 31 shown in FIG. 2A is lower than the step in the first embodiment.
Therefore, it is possible to increase the step coverage rate of the word line 22 and suppress occurrence of disconnection.

[0046] Incidentally, in the case of the second embodiment shown in FIG. 4, SiO ₂ region 3 is oxidized amorphous silicon film
1A and 31B may be formed.

FIG. 5 is an equivalent circuit diagram of the cell array portion of the semiconductor memory device according to the above embodiment, and word lines, bit lines,
FIG. 3 is a plan view showing an arrangement of source lines. The floating gate type FETs 30 are arranged in a matrix. FET
The gate lines 20 are arranged corresponding to the columns. The word line in the upper layer of the gate line 20 is connected to the FET 30 in the corresponding column.
Of the control gate electrode 30G. FE
Bit lines 52 are arranged corresponding to the row of T30.
Each bit line 52 is connected to the drain region 30D of the FET 30 in the corresponding row via the contact hole 40.

Two FETs 30 adjacent to each other in the row direction
Source region 30S is continuous with one column direction region 10b. The column direction region 10b has a contact hole 41
Is connected to the source line 55 via the. A drive voltage is applied to source region 30S via source line 52 and column direction region 10b.

By applying a read signal to a word line in an upper layer portion of the gate line 20, information stored in the FETs 30 in a column corresponding to the word line can be read. By applying a write signal to one word line and one bit line, information can be written to the FET 30 selected by the word line and the bit line.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0051]

As described above, according to the present invention,
No large step is formed between the floating gate electrodes of the floating gate type FETs adjacent to each other.
Therefore, disconnection of a word line formed on the floating gate electrode can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a substrate for explaining a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a plan view showing an equivalent circuit diagram of a floating gate type FET and an arrangement of word lines, bit lines, and source lines.

FIG. 6 is a cross-sectional view of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation structure 10 Active region 10a Row direction region 10b Column direction region 20 Gate line 21 Floating gate line 22 Word line 30 Floating gate type FET 30S Source region 30D Drain region 30F Floating gate electrode 30G Control electrode 30C Channel region 30W Sidewall insulating film 30I First gate insulating film 30J Second gate insulating film 31 Insulation isolation region 40, 40a, 41, 42 Contact hole 46 Auxiliary word line 47 Resist pattern 50, 51 Interlayer insulating film 52 Bit line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA25 AB08 AD62 AG02 AG10 AG12 AG21 5F083 EP02 EP13 EP23 GA09 GA30 JA33 JA35 JA39 JA53 KA01 MA01 MA16 MA20 NA02 PR12 PR21 PR36

Claims (9)

[Claims] Claims: 1. An insulating material formed on a surface of a substrate,
First and second spaced apart in a first direction
An element isolation structure defining an active region, a first floating gate electrode formed of a conductive material and extending from the first active region to above the element isolation structure, and the second A second floating gate electrode formed of an electrically conductive material and extending from the active region to above the element isolation structure, formed of an insulating material, provided on the element isolation structure, An insulating isolation region that physically connects the floating gate electrode and the second floating gate electrode; and a conductive material formed continuously on the first and second floating gate electrodes and the insulating isolation region. And a control gate electrode. 2. The semiconductor memory device according to claim 1, wherein said first and second floating gate electrodes are formed of silicon, and said isolation region is formed of silicon oxide. 3. An upper surface of the insulating isolation region is located at a boundary between the insulating isolation region and the first floating gate electrode and at a boundary between the insulating isolation region and the second floating gate electrode. 3. The semiconductor memory device according to claim 2, wherein a step is formed to be higher than an upper surface of the second floating gate electrode. 4. The semiconductor device according to claim 1, wherein the insulating isolation region includes two insulating portions separated from each other in the first direction, and a region therebetween is formed of the same material as the first and second floating gate electrodes. The semiconductor memory device according to claim 1. 5. A semiconductor substrate having a main surface, and a plurality of floating gate type FETs formed on the main surface of the semiconductor substrate, wherein the FETs are arranged in a matrix on the main surface. The source region, the channel region, and the drain region are arranged in a row direction.
ET, an element isolation structure for electrically separating the plurality of FETs in the column direction, and a floating gate electrode of the two FETs arranged on the element isolation structure and arranged in the column direction, facing each other. An insulating separation region that contacts an end surface of the floating gate and electrically secures the two floating gate electrodes, and physically connects the two floating gate electrodes. Other FETs adjacent in the column direction via the region
Semiconductor memory device connected to the control gate electrode of the semiconductor memory device. 6. The semiconductor device according to claim 1, further comprising:
The FETs are arranged corresponding to each row, and the F
6. The semiconductor memory device according to claim 5, further comprising a bit line electrically connecting the drain regions of the ET. 7. The semiconductor memory device according to claim 5, further comprising a source line disposed on a main surface of said semiconductor substrate and supplying a drive voltage to a source region of each FET. 8. A step of forming an element isolation structure on a main surface of a semiconductor substrate so that active regions are arranged at a certain interval in a first direction; Forming a first conductive film so as to cover the first gate insulating film and the element isolation structure; and selectively forming a part of the first conductive film. Forming a part of the region above the element isolation structure between the active regions arranged in the first direction into an insulator; Of the conductive film surface of
Forming a second gate insulating film on at least a region that has not been converted into an insulator; and forming a second conductive film over the entire surface of the substrate so as to cover the second gate insulating film; A step of patterning a laminated structure from the second conductive film to at least the first conductive film to form a gate line composed of these laminated layers, wherein the gate line extends in the first direction. Extending the gate line so as to pass over the active region; and adding an impurity to regions of the active region on both sides of the gate line to form a source region and a drain region. A method for manufacturing a semiconductor memory device having: 9. The method according to claim 8, wherein the first conductive film is formed of silicon, and in the step of forming an insulator, the first conductive film is formed into an insulator by selectively adding oxygen. 6. The method for manufacturing a semiconductor memory device according to claim 1.