JP2000181792A - Cache controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a cache controller improved in system performance by eliminating the reduction of a cache accessible time due to a cache invalidating process by performing control so that the cache invalidating process is performed for the 1st time at the time of switching from (n)th algorithm to 1st algorithm. SOLUTION: A mapping algorithm controller 310 when judging that a hit rate 301 is less than an expected value informs a main controller 100 of a mapping switching indication 311 and switches a mapping controller A210 to other mapping controllers B220 to D240 with a selector control signal 312. In this switching, the process is carried out without invalidating the cache and when the switching to the starting mapping controller A210 is done again, the cache is invalidated for the 1st time. Consequently, the main controller 100 can continue access to the cache memory without being aware of the switching to other mapping algorithm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache control device, and more particularly to a cache memory address mapping control system.

[0002]

2. Description of the Related Art In a cache control device having only one type of mapping algorithm, a cache hit ratio is measured by an actual machine. There was only a measure to cope with the method. In addition, the measurement of the cache hit rate by the actual machine
Since not all the cache access patterns are covered, a difference occurs in the cache hit ratio depending on the system.

Therefore, Japanese Patent Laid-Open Publication No. Hei 8-263376 discloses a method in which a plurality of mapping algorithms are prepared in advance, and when the cache hit rate falls below an expected value, the mapping algorithm currently being processed is switched to another algorithm. There has been proposed a technique of performing switching control and performing cache invalidation processing for each switching processing.

[0004]

The above-mentioned JP-A-8-26
The problem with the cache control device having a plurality of mapping algorithms disclosed in Japanese Patent No. 3376 is that the cache invalidation process is performed every time the mapping algorithm is switched. The reason for this is to prevent a cache from erroneously hitting when the address tag and the set address generated by a different mapping algorithm are the same even for different access addresses.

However, in the method of invalidating the cache every time the mapping algorithm is switched,
Due to the invalidation processing, the cache memory access is interrupted, so that the time during which the cache can be accessed for a certain period of time is reduced accordingly, resulting in a decrease in system performance.

[0006] It is an object of the present invention to provide a cache control device which can improve the system performance without reducing the cache access time caused by the invalidation processing.

[0007]

According to the present invention, a plurality of cache memory mapping algorithms are provided, and when a cache hit ratio is lower than an expected value during processing by a certain algorithm, the algorithm being processed is replaced by another. A cache control device for switching to the algorithm described in claim 1, further comprising control means for controlling to immediately switch the algorithm without performing a cache invalidation process when the algorithm is switched. Is obtained.

Further, according to the present invention, a tag memory for storing an address tag, a data memory for storing block data, and a cache memory mapping algorithm different from an access address to the memory for the tag memory and the data memory. A plurality of mapping controllers for generating a set address and an address tag; a first selector for selecting one of the set addresses output from the plurality of mapping controllers and outputting the set address to the tag memory and the data memory; A second selector for selecting one of the address tags output from the plurality of mapping controllers;
An address comparison circuit for comparing an address tag output from the selector with an address tag output from the tag memory, a hit determination circuit for performing a cache hit determination based on the comparison result, and a hit ratio based on the hit determination result. And an algorithm currently being processed is immediately switched to another algorithm without performing cache invalidation processing when the hit rate is lower than an expected value, and the first and second selectors And a control means for instructing selection of the cache control device.

Further, a mappin ID for generating identification information of each of the cache memory mapping algorithms.
Generating means, a third selector for selecting the identification information under the control of the control means, an ID memory for storing identification information of the algorithm for each set address of the tag memory, and a third selector. And an ID comparison circuit that compares the identification information of the ID memory with the identification information from the ID memory and notifies the hit determination circuit of the comparison result.

[0010] The algorithm is composed of first to n-th
(N is an integer of 2 or more), wherein the control means sequentially controls the first to n-th algorithms in this order and controls the first to n-th algorithms in this order. It is characterized in that the cache invalidation process is controlled only when the mode is switched to.

The operation of the present invention will be described. When the cache memory mapping algorithm is switched, this algorithm is switched immediately without performing the cache invalidation processing, so that unnecessary cache invalidation processing is suppressed as much as possible, so that the cache accessible time per fixed time can be reduced. Lengthening, and improving system performance.

[0012]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
It is a block diagram showing an embodiment. In this example, it is a block diagram in a case where the cache control device is a two-way set associative cache and has four (first to fourth) mapping algorithms.

In FIG. 1, 100 is a main controller, 12
0 is an address bus, 140 is a data bus, 200 is an address register, 210 is a mapping controller A that generates a set address and tag data by a first mapping algorithm, and 220 is a set address and tag data by a second mapping algorithm. Is a mapping controller C that generates a set address and tag data by a third mapping algorithm, and 240 is a mapping controller D that generates a set address and tag data by a fourth mapping algorithm. .

Reference numeral 250 denotes a selector A for selecting a set address; 260, a selector B for selecting tag data; 270, a comparator A for tag data of the first compartment; and 280, a comparator B for tag data of the second compartment. 290, a hit determination circuit; 300, a hit ratio calculating means; 310, a mapping algorithm controller; 400, a tag memory of the first compartment;
10 is a tag memory of the second compartment, 420 is a data memory of the first compartment, and 430 is a data memory of the second compartment.

Further, 201 is a block address field of access address data, 202 is an address field in a block of access address data, 211 is a set address generated by the mapping controller A, 212 is tag data generated by the mapping controller A, Reference numeral 221 denotes a set address generated by the mapping controller B; 222, tag data generated by the mapping controller B; 231, a set address generated by the mapping controller C; 232, tag data generated by the mapping controller C; The set address 242 generated by the mapping controller D is tag data generated by the mapping controller D.

251 is a set address selected by the selector A, 261 is tag data selected by the selector B, 271 is a comparison result of the tag data in the first compartment, 281 is a comparison result of the tag data in the second compartment , 291 are the cache hit determination results,
301 is a calculated hit ratio, 311 is a selector control signal, 292 is a data memory enable for instructing to enable the data memory of the compartment where the hit has occurred, and 3 is a data memory enable.
11 is a mapping switching instruction to main controller 100, 31
2 is a selector control signal, 401 is tag data stored in the tag memory 400, and 411 is tag data stored in the tag memory 410.

The operation of the cache control device shown in FIG. 1 for cache memory access will be described. Main controller 100 outputs the target access address to address bus 120 and stores the access address in address register 200. Mapping controllers 210 and 22
Each of 0, 230, and 240 generates a set address and tag data from the block address 201 stored in the address register 200, and outputs the set address and the tag data to the selector A and the selector B.

Mapping algorithm controller 31
0 is the mapping controller 210 in the initial state.
Is selected by the mapping switching instruction 312. In this case, the selector A 250 sets the set address 21
1 is selected, and the selector B selects the tag data 212.

From the tag memories 400 and 410, the tag data 401 of the set address 251 is sent to the comparison circuit A.
The tag data 412 is output to the comparison circuit B, respectively, and the comparison of the tag data is performed.
The comparison circuit B280 outputs whether or not the tag data 61 and the tag data 401 match, as a comparison result 271.
61 and the tag data are similarly output to the comparison result 281.

The hit determination circuit 290 notifies the hit ratio calculation means 300 and the main controller 100 of a cache hit determination result 291 indicating whether a cache hit or a miss has occurred.
The data memory of the compartment hit by the data memory enable 292 is enabled. Since the compartment is hit, the data memory outputs the data of the in-block address 202 of the set address 251 to the data bus 140.

Main controller 100 reads the data of the target access address from data bus 140 when a cache hit occurs. The hit ratio calculation means 300 calculates the hit ratio from the number of hit determinations and the number of hits based on the cache hit determination result 291, and notifies the mapping algorithm controller 310 of the hit ratio 301 for each predetermined number of hit determinations.

Mapping algorithm controller 31
When 0 determines that the hit rate 301 is lower than the expected value, the main controller 100 is notified of a mapping switching instruction 311 and the selector control signal 312 switches the mapping controller A to another mapping controller. In this example, the mapping controller is B220.
Main controller 100 executes the access to the cache by mapping controller B, which is a new mapping algorithm, in the same manner.

Thereafter, if the cache hit rate is lower than the expected value, the mapping controller C230 and the mapping controller D240 are switched in this order. At each of these switchings, the processing is continued without invalidating the cache and the first mapping is performed again. When the mode is switched to the controller A210, the cache invalidation process is executed for the first time. Thus, main controller 100 can continue to access the cache memory only by executing the invalidation process only when changing to mapping controller A, without being aware of switching to another mapping algorithm.

FIG. 2 is a block diagram showing another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2, 440 is an ID memory of the first compartment, 450 is an ID memory of the second compartment, 500 is a mapping ID generating means for outputting an identification code of each mapping algorithm, and 510 is a mapping selected by the mapping algorithm controller 310. A selector C 520 for selecting a mapping identification code indicating a controller is a comparison circuit C for identification code of the first compartment, and a reference numeral 530 is a comparison circuit D for identification code of the second compartment.

Reference numeral 441 denotes an identification code stored in the ID memory 440; 451, an identification code stored in the ID memory 450; 501, an identification code indicating that mapping is performed by the mapping controller A;
02 is an identification code indicating mapping by the mapping controller B, 503 is an identification code indicating mapping by the mapping controller C,
Reference numeral 504 denotes an identification code indicating that the mapping is performed by the mapping controller D, reference numeral 511 denotes a selected identification code, reference numeral 521 denotes a comparison result of the identification code of the first compartment, and reference numeral 532 denotes a comparison result of the identification code of the second compartment. The other configuration is the same as that of FIG. 1, and the description is omitted.

In this configuration, first, the main controller 1
00 outputs the target access address to the address bus 120, and compares the tag data 401 and 411 with the comparison circuit A2.
The operations up to the comparison at 50 and B260 are performed in the same manner as in the first embodiment, and the following operations are performed in parallel. In this example, the mapping controller A210 is selected first.

The selector C510 receives the selector control signal 31
2, the identification code 50 indicating the mapping controller A210 selected by the selectors A250 and B260.
1 is selected and output to the identification code 511. ID memory 4
The identification codes 441 and 451 stored in the set address 250 are compared with the comparison circuits C52 and
0, and D530, and are performed in parallel up to the comparison of the identification code.

When the comparison results 271 and 521 match, the hit determination circuit 290 sets the first compartment cache hit, and when the comparison results 281 and 531 match, sets the second compartment cache hit. This is shown in the hit determination result 291.

The hit ratio calculating means 300 calculates the hit ratio as in the example of FIG. When the hit ratio is lower than the expected value, the mapping algorithm controller 310 outputs the selectors A250, B260,
Instruct C510 to only select mapping controller B220 and its identification code 502, respectively.

Also in this case, as in the example of FIG. 1, when the cache hit ratio is lower than the expected value, the mapping controller C230 and the mapping controller D240 are sequentially switched. The cache invalidation process is executed for the first time when the process is switched to the first mapping controller A210 again. Thereby, main controller 10
In the case of 0, the invalidation process is executed only when the mapping controller A is changed, and access to the cache memory can be continued without being aware of switching to another mapping algorithm.

In each of the embodiments described above, the case where the two-way set associative cache system is used has been described. However, the cache system such as direct mapping or full associative is not limited. Further, in the above-described embodiment, a case has been described in which there are four types of mapping algorithms, but the number of mapping algorithms is not limited.

[0032]

According to the present invention, the number of interruptions of cache memory access due to cache invalidation at the time of switching the mapping algorithm can be greatly reduced as compared with the prior art, so that the effective time of cache access in a certain time becomes longer, and the There is an effect that performance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 100 Main control device 200 Address register 210, 220, 230, 240 Mapping controller 250, 260, 510 Selector 270, 280, 520, 530 Comparison circuit 290 Hit determination circuit 300 Hit ratio calculation means 310 Mapping algorithm controller 400, 410 Tag memory 420 , 430 Data memory 440, 450 ID memory 500 Mapping ID generating means

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[Procedure amendment]

[Submission Date] October 25, 1999 (1999.10.
25)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

[0007]

According to the present invention, an address
Tag memory to store tags and block data
From the data memory to be accessed and the access address to the memory
Different cache memory mapping algorithms
Setting of the tag memory and the data memory
Multiple mapping codes to generate addresses and address tags
Controllers and multiple mapping controllers
Select one of the set addresses output from the
First select for outputting to the memory and the data memory
Data output from the plurality of mapping controllers.
Selector for selecting one of the address tags
And an address tag output from the second selector.
Compare with the address tag output from the tag memory
Address comparison circuit and cache based on the comparison result.
Hit determination circuit for performing hit determination and this hit determination
Hit rate calculating means for calculating a hit rate based on the result;
If this hit rate is lower than expected, cache invalid
Other algorithms that are currently being processed
Immediately switch to the first algorithm and the first and second
Control means for selecting and instructing the cache, and the cache
Generates identification information for each of the memory mapping algorithms
Mappin ID generating means, and the identification information
A third selector selected by control of the control means;
For each set address of the tag memory, the algorithm
An ID memory for storing identification information, and the third selector
Of the identification information from the ID memory and the identification information from the ID memory.
ID ratio for notifying the hit determination circuit of the comparison result
And a comparison circuit, wherein the algorithm includes first to n-th (n is
The control means.
Sequentially switches the first to n-th algorithms in this order.
Controlling the first algorithm from the n-th algorithm.
The cache invalidation process is performed only when switching to the algorithm.
Thus , a cache control device characterized by performing control in a logical manner is obtained.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0008

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[Procedure amendment 4]

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[Procedure amendment 6]

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[Correction contents]

251 is a set address selected by the selector A, 261 is tag data selected by the selector B, 271 is a comparison result of the tag data in the first compartment, 281 is a comparison result of the tag data in the second compartment , 291 are the cache hit determination results,
301 is a calculated hit ratio, 311 is a selector control signal, 292 is a data memory enable for instructing to enable the data memory of the compartment where the hit has occurred, and 3 is a data memory enable.
11 is a mapping switching instruction to main controller 100, 31
2 is a selector control signal, 401 is tag data stored in the tag memory 400, and 411 is tag data stored in the tag memory 410. 440 is the first computer
ID memory of the compartment, 450 is the second compartment
ID memory, 500 is for each mapping algorithm
Mapping ID generating means for outputting an identification code, 510
Is selected by the mapping algorithm controller 310.
A mapping indicating the selected mapping controller
The selectors C and 520 for selecting the identification code
The comparison circuits C and 530 of the identification code of the
5 is a comparison circuit D for compartment identification codes. Ma
Reference numeral 441 denotes an identification code stored in the ID memory 440.
451 is an identification code stored in the ID memory 450.
Code 501 is a mapping by mapping controller A.
Ping identification code, 502 is a mapping
That the mapping is performed by controller
The other code, 503, is a mask by the mapping controller C.
504 is a mapping code indicating that the
The mapping is performed by the mapping controller D
The identification code, 511 is the selected identification code, and 521 is
Comparison result of identification code of first compartment, 531
Is the comparison result of the identification code of the second compartment.
You.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

From the tag memories 400 and 410, the tag data 401 of the set address 251 is sent to the comparison circuit A.
The tag data 411 is output to the comparison circuit B, respectively, and the comparison of the tag data is performed.
The comparison circuit B280 outputs whether or not the tag data 61 and the tag data 401 match, as a comparison result 271.
Similarly, the comparison result 281 is obtained for the tag data 611 and the tag data 411.
Output to

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The following operation is performed in parallel with the above operation.
U.

[Procedure amendment 11]

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[Correction method] Change

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When the cache hit ratio is lower than the expected value, the mapping controller C230 and the mapping controller D240 are sequentially switched. At each of these switchings , as described above , the processing is continued without invalidating the cache, and the first time again. Mapping controller A210
, The cache invalidation process is executed for the first time. Thus, main controller 100 can continue to access the cache memory only by executing the invalidation process only when changing to mapping controller A, without being aware of switching to another mapping algorithm.

[Procedure amendment 12]

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[Correction method] Change

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[0031] In the embodiment described above, 2 is described the case of using a cache strategy-way set associative, there is no limit on the cache method and direct mapping and fully associative. Further, in the above-described embodiment, a case has been described in which there are four types of mapping algorithms, but the number of mapping algorithms is not limited.

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[Correction target item name] Fig. 1

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FIG.

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Claims (6)

[Claims] 1. A cache control device having a plurality of cache memory mapping algorithms, wherein, when a cache hit rate is lower than an expected value during processing by one algorithm, the algorithm is switched to another algorithm during processing. A cache control device, comprising: control means for controlling the switching of the algorithm immediately without performing a cache invalidation process when the algorithm is switched. 2. A tag memory for storing an address tag,
A data memory for storing block data, a plurality of mapping controllers for generating a set address and an address tag of the tag memory and the data memory by a cache memory mapping algorithm different from an access address to the memory, and a plurality of mapping controllers; A first selector for selecting one of the set addresses output from the controller and outputting the set address to the tag memory and the data memory, and a second selector for selecting one of the address tags output from the plurality of mapping controllers An address comparison circuit that compares an address tag output from the second selector with an address tag output from the tag memory; a hit determination circuit that determines a cache hit based on the comparison result; Hit rate calculating means for calculating a hit rate based on the result; and when the hit rate is lower than an expected value, immediately switch an algorithm currently being processed to another algorithm without performing cache invalidation processing. And a control means for instructing a second selector to make a selection. 3. A mappin ID generating means for generating identification information of each of the cache memory mapping algorithms, a third selector for selecting the identification information under the control of the control means, and each set address of the tag memory. ID for storing the identification information of the algorithm for each
A memory, identification information from the third selector and the I
3. The cache control device according to claim 2, further comprising an ID comparison circuit that compares the identification information from the D memory and notifies the hit determination circuit of a comparison result. 4. The algorithm includes first to n-th (n is 2
The above-mentioned integer), wherein the control means comprises:
4. The cache control device according to claim 1, wherein the first to n-th algorithms are sequentially switched and controlled in this order. 5. The cache control device according to claim 4, wherein control is performed such that the cache invalidation processing is performed only when switching from the n-th algorithm to the first algorithm. 6. The data memory comprises a plurality of compartments, and each of the tag memory, the ID memory, the address comparison circuit and the ID comparison circuit is provided corresponding to each of these compartments. 4. The cache control device according to claim 2, wherein: