JP2000181404A - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress unnecessary electromagnetic radiation without employing an electromagnetic shielding film or a metallic shield. SOLUTION: When driving a plasma display panel having plural display electrode pairs that are made up with X and Y electrodes covered by dielectric bodies, the rising wave shape of priming pulses applied to either one of the X electrodes or the Y electrodes is constituted of the synthesized wave made up with a gradual wave shape formed by employing capacitors Ck1 and Ck2 and transistors T1 to T13 and the steep wave shape formed by employing only the transistors T1 to T13 without capacitors Ck1 and Ck2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an AC surface discharge type plasma display panel (hereinafter referred to as "AC-PD").
P ") and a plasma display apparatus.

[0002]

2. Description of the Related Art Various studies have been made on plasma display panels as thin televisions or display monitors. Information devices such as plasma display panels have regulations on electromagnetic interference. In Japan, The Voluntary Contrmol Council for Interferenc
e (hereinafter, referred to as “VCCI”). Since a plasma display panel uses discharge, a large current of several amperes flows, and a magnetic field is generated.
Therefore, unless a countermeasure is taken, the prescribed value defined in VCCI cannot be satisfied. This tends to be more pronounced with larger screens and higher definition. For this reason, for example, "the forefront of the plasma display business"
(Published by the Industrial Research Council of 1997) describes that an electromagnetic wave shielding film is provided on the front surface of a panel to shield unnecessary electromagnetic radiation (EMI) from the front surface of the panel. These general countermeasures are described in "Introduction to EMC" (published by Mimatsu Data System in 1996).

Unwanted electromagnetic radiation occurs not only from the front of the panel but also from the back and sides. Therefore, it is conceivable to provide a metal shield on the back and side surfaces to block unnecessary electromagnetic radiation from the back and side surfaces. However, in the case of a plasma display panel, the temperature inside the housing increases, and in order to prevent this, ventilation holes and the like for cooling and ventilating must be provided on the side and back surfaces of the housing. Thus, it is almost impossible to completely cover the housing with electromagnetic radiation.

An AC-PDP is one of the most general plasma display panels having a memory function. Hereinafter, the AC-PDP will be described with reference to FIG.

FIG. 8 is a perspective view showing the structure of a conventional AC-PDP. The AC-PDP having the structure shown in FIG. 8 is disclosed in, for example, JP-A-7-140922 and JP-A-7-287747.
No. 6,086,045. In FIG. 8, AC-PDP
Includes a front glass plate 102 serving as a display surface, and a rear glass substrate 103 arranged to face the front glass substrate 102 with a discharge space therebetween. Then, the front glass substrate 102
Of the first electrodes 1 forming a pair with each other
04 and the second electrode 105 are each formed to extend by n pieces.

The first electrode 104 and the second electrode 105
Are also referred to as a row electrode 104 and a row electrode 105, respectively. When a metal auxiliary electrode (bus electrode) is provided on a part of the surface of each of the row electrodes 104 and 105, the metal electrode and the metal electrode can be referred to as the row electrodes 104 and 105, respectively.

[0007] In the AC-PDP, a dielectric layer 106 is formed so as to cover the row electrodes 104 and 105. Also,
MgO film 107 as a dielectric on the surface of dielectric layer 106
In some cases, the dielectric layer 106 and the MgO film 107 are collectively referred to as a “dielectric layer 106A”.

On the other hand, m third electrodes 108 (hereinafter, referred to as “column electrodes 108”) are formed on the surface of the rear glass substrate 103 on the discharge space side so as to extend so as to be orthogonal to the row electrodes 104 and 105. The partition 110 extends between the adjacent column electrodes 108 in parallel with the column electrodes 108. The partition wall 110 serves to separate the discharge cells and also serves as a support for supporting the plasma display panel so as not to be crushed by the atmospheric pressure. Then, on the surface of each column electrode 108 and on the side wall surface of the partition 110, the phosphor layers 109 emitting red, green, and blue light, respectively.
R, 109G, and 109B are provided in this order in a stripe shape.

The front glass substrate 102 having the above structure
And the rear glass substrate 103 are sealed to each other, and a discharge gas such as a Ne—Xe mixed gas or a He—Xe mixed gas is sealed in a space between the glass substrates 102 and 103 at a pressure lower than the atmospheric pressure. . In the discharge space, a portion where the paired row electrodes 104 and 105 and the column electrode 108 cross each other forms one discharge cell, that is, a pixel.

Next, the principle of the above-described AC-PDP display operation will be described. First, a voltage pulse is applied between the row electrodes 104 and 105 to cause a discharge. Then, ultraviolet rays generated by this discharge excite the phosphor layer 109, so that the discharge cells emit light. At the time of this discharge, the electrons and ions generated in the discharge space move toward the row electrodes 104 and 105 having polarities opposite to the respective polarities.
It accumulates on the surface of the dielectric layer 106A on the row electrodes 104 and 105. The charges such as electrons and ions accumulated on the surface of the dielectric layer 106A in this manner are called "wall charges".
It should be noted that the amount of wall charges cannot be a value higher than the externally applied voltage value. When a high voltage is applied to cause a discharge, the discharge may occur again at the falling edge of the applied pulse. This is called "self-erasing discharge", and is a discharge that occurs because the wall voltage formed by the applied pulse is large, and the falling wall voltage itself exceeds the discharge starting voltage.

The electric field formed by the charges acts in the direction of weakening the applied voltage, so that the discharge rapidly disappears with the formation of the wall charges. After the discharge has been extinguished, when a voltage pulse of which polarity has been reversed is applied between the row electrodes 104 and 105,
Since the electric field in which the applied voltage and the electric field due to the wall charges are superimposed is substantially applied to the discharge space, the discharge can be caused again. Thus, once a discharge occurs,
Voltage lower than the voltage at the start of discharge (hereinafter referred to as “sustain voltage”
Discharge) can be generated by applying a sustain voltage (hereinafter, also referred to as a “sustain pulse”) whose polarity is sequentially inverted between the row electrodes 104 and 105. Can be maintained. Hereinafter, this discharge is referred to as “sustain discharge”.

This sustain discharge is maintained as long as the sustain pulse is continuously applied until the wall charges disappear. The elimination of wall charges is called "erasing".
On the other hand, forming a wall charge on the dielectric layer 106A at the beginning of the discharge start is called "writing". Therefore,
A desired cell on the screen of the AC-PDP is written first, and thereafter a sustain discharge is performed to display characters, graphics, images, and the like. In addition, moving images can be displayed by performing writing, sustaining discharge, and erasing at high speed.

FIG. 9 shows a conventional driving method disclosed in Japanese Patent Application Laid-Open No. 9-62225. One field of an image is composed of a plurality of subfields, and gradation display is performed by weighting luminance for each subfield. FIG. 9 shows one of these subfields. In FIG. 9, Wu is a drive waveform applied to sustain electrodes Su1 to Suj, and Ws1 to Wsj are scan electrodes Sc1 to Sj.
A driving waveform applied to cj and Wd is a driving waveform applied to the data electrode Wd. One subfield is A, B,
It is composed of part C. A is a reset period to which a priming pulse (preliminary discharge pulse) Pp and an erase pulse (preliminary discharge erase pulse) Ppe are applied.

The priming pulse Pp is applied to the entire surface irrespective of the display history in order to initialize the state of wall charges in the cell and increase the probability of discharge. The discharge generated when a priming pulse is applied is called a priming discharge. In the above embodiment, the priming pulse is inserted once in one subfield, but may be inserted once in a plurality of subfields.

On the other hand, the erase pulse Ppe is applied to the row electrode 10
By applying a pulse voltage whose polarity changes alternately between 4, 105, the gas is applied to one of the row electrodes 104, 105 after the end of the discharge sustaining period in which gas discharge is repeatedly generated. Thereby, the display history is reset. Further, the pulse width of the erase pulse Ppe is smaller than the pulse width (Pse in FIG. 9) applied during the sustain period.
The erasing pulse Ppe is for erasing wall charges formed by the priming pulse Pp. However, if the priming pulse Pp has a sufficiently high voltage, a self-erasing discharge occurs at the fall of the priming pulse Pp. It is not necessary to apply the erase pulse Ppe.

For example, in Japanese Patent Application Laid-Open No. 10-3281, as shown in FIG. 10, several subfields in one field are reset by a self-erasing discharge of a priming pulse Pp, and the remaining subfields are erase pulses Ep.
There is disclosed an example in which reset is performed by the following. As the erase pulse Ep, the self-erasing area (erasable area) shown in FIG.
As shown by hatching, pulses having several pulse widths and pulse voltage values can be used. In addition,
In the self-erasing area shown in FIG. 11, the pulse width is 3 μs.
The following region is a region where erasing is performed in a relatively wide voltage range by lowering the erasing pulse while space charges at the rising edge of the erasing pulse still remain.

FIG. 9B shows a writing discharge period, in which discharge cells are selected in a matrix by the scanning pulse Pw and the data pulse Pd. C is the sustain pulse during the sustain discharge period
u and Ps are alternately applied to obtain a desired luminance. And
At the end of the sustain discharge period, Pse is applied as a final sustain pulse, and one subfield ends.

The priming pulse Pp in the next subfield has a potential relationship of a polarity opposite to that of the last sustain pulse Pse. Therefore, the priming pulse Pp is applied to the cells lit in the previous subfield so as to overlap the wall charges formed by the final sustain pulse Pse. As a result, the preliminary discharge can be performed stably and reliably.

FIG. 12 shows a light emission waveform when a priming pulse is applied in a polarity opposite to the potential of the final sustain pulse. FIG. 12 shows a black screen display state, a white screen display state, and a blue screen display state from the left. Since the sequence configuration is similar to the above-mentioned Japanese Patent Application Laid-Open No. 9-62225, the emission waveform of the related art can be estimated to be equivalent to the emission waveform shown in FIG. By the way, although the applied voltage is not changed under any display conditions, a light emission waveform that is slow and delayed from the pulse rising is observed in the black screen display. In the white screen display, light emission is observed very steeply and at an early timing from the rise of the pulse. In the blue screen display, the discharge cells (blue) that were lit by the immediately preceding pulse discharge at an earlier timing from the pulse application, and the discharge cells that were not lit (red and green) discharge later than the pulse application to emit light. The waveform has a shape with two peaks. This is because even if the applied voltages are equal, the amount of wall charges accumulated in the cells is different, so that the effective voltage (the wall voltage minus the externally applied voltage) is higher in the discharge cells lit in the immediately preceding subfield. Note that a period from the rise of the pulse to the occurrence of the light emission waveform is referred to as “discharge delay”.

Now, various researches and developments have been made to further improve the luminous efficiency of the AC-PDP. Among them, there is a technique for improving the power loss at the time of driving the AC-PDP, thereby achieving higher light emission efficiency.

Since the AC-PDP is a capacitive load,
When charging and discharging the plasma display panel, reactive power (power not contributing to discharge or light emission) proportional to the square of the voltage of the driving voltage pulse and the capacitance component of the panel is generated. Accordingly, since the capacitive load of the plasma display panel increases with the increase in the size of the plasma display panel, the reactive power in the total power consumption becomes too large to be ignored.

Therefore, a technique regarding a circuit for recovering reactive power is disclosed in, for example, JP-A-8-152865 and JP-B-56-30730. FIG. 13 is a diagram showing a configuration of a plasma display device having a reactive power recovery circuit disclosed in the former publication. The plasma display device shown in FIG. 13 includes a PDP 201 having a capacitance component CP, a reactive power recovery circuit 202, and a pulse generation circuit 203.

The pulse generating circuit 203 has FETs 2031 to 2034 as switching elements. The reactive power recovery circuit 202 includes FETs 2022 and 202
022, a coil 2023, a resistor 2024, and diodes 2025 and 2026. The reactive power recovery circuit 202 is connected in parallel with the PDP 201, that is, the capacitance component CP. For this reason, the circuit 202 is also called a parallel resonance type reactive power recovery circuit. In the plasma display device, the capacitance component C after discharge of the PDP 201
The energy stored in P is once absorbed by the coil 2024, and the energy is immediately recharged in the direction of the polarity opposite to that of the previous discharge so that the energy is recharged for the subsequent discharge.
Control signals are given to control terminals IN1 to IN4 of ET2031 to 2034. In this manner, the plasma display device of FIG. 8 uses the reactive power recovery circuit 202 to recover and reuse the discharge energy of the capacitance component CP.

On the other hand, FIG.
FIG. 2 is a diagram illustrating a configuration of a plasma display device having a reactive power recovery circuit 302 disclosed in Japanese Patent Application Laid-Open No. 2798 or JP-A-63-101897. The plasma display device shown in FIG. 14 is a PDP 3 having a capacitance component CP.
01, reactive power recovery circuit 302, and pulse generation circuit 3
03.

The pulse generation circuit 303 includes a switch 303
1 to 3034. The reactive power recovery circuit 302 includes switches 3021 to 3024, a coil 3025, a resistor 30
26 and capacitors 3027 and 3028. Also, the reactive power recovery circuit 302 is a PDP 201, that is,
Both ends of the capacitance component CP are connected in series. Therefore, the circuit 302 is also called a series resonance type reactive power recovery circuit. In the plasma display device, by appropriately controlling the switches 3021 to 3024, the energy stored in the capacitance component CP after the discharge is once recovered to the capacitors 3027 and 3028 via the coils 3025 and 3026, and then the predetermined energy is recovered. At this timing, the capacitance component CP is recharged using the above energy.

A series resonance type reactive power recovery circuit 3 shown in FIG.
02 is a parallel resonance type reactive power recovery circuit 202 shown in FIG.
Compared with the above, there is a disadvantage that the number of parts is large and the parts space is large, so that the cost is high. However, since the discharge energy is once charged in the capacitors 3027 and 3028, the design of the drive voltage pulse (especially the application timing) is required. There is an advantage that the degree of freedom is large and therefore the discharge is easily controlled.

[0027]

It is possible to shield unnecessary electromagnetic radiation by a method using an electromagnetic wave shielding film or a method of covering a housing with a metal shield as in the prior art. Is often not obtained. In particular, as the PDP has a larger screen and higher definition, unnecessary electromagnetic radiation increases, and the above method alone becomes insufficient. Furthermore, when the above-mentioned electromagnetic wave shielding film or metal shield is used, there is a problem that the cost is increased and the assemblability is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a novel driving method of a plasma display panel capable of suppressing unnecessary electromagnetic radiation without using an electromagnetic wave shielding film or a metal shield. It is an object to obtain a method and a plasma display device.

[0029]

According to a first aspect of the present invention, there is provided a plasma display panel having a plurality of display electrode pairs each including a first electrode and a second electrode, at least one of which is covered with a dielectric. When driving, the first
And a driving method of a plasma display panel for applying a priming pulse to one of the second electrodes, wherein a rising waveform of the priming pulse is set to a gentle waveform formed by using an impedance element and a first switch; , And a composite wave with a steep waveform formed only by the second switch.

The problem solving means according to claim 2 of the present invention is characterized in that the falling of the priming pulse does not use the impedance element but falls sharply only by the third switch.

[0031] In the means for solving problems according to claim 3 of the present invention, the impedance element is a reactor included in a reactive power recovery circuit for recovering reactive power generated in a capacitance component between the display electrode pair. It is characterized by.

According to a fourth aspect of the present invention, there is provided:
The plasma display panel has a third electrode formed so as to be orthogonal to the first electrode and the second electrode, and before the priming pulse is raised, the third electrode is a floating electrode, The third electrode is fixed to the ground before the priming pulse falls.

The problem solving means according to claim 5 of the present invention is as follows.
When the third electrode is fixed to the ground, the third electrode is gradually lowered to the ground.

[0034] The means for solving problems according to claim 6 of the present invention is:
A plasma display panel having a plurality of display electrode pairs each including a first electrode and a second electrode at least one of which is covered with a dielectric, wherein the plasma display panel applies an erasing pulse to one of the first and second electrodes. Wherein the rising waveform of the erase pulse is
It is characterized by comprising a composite wave of a gentle waveform formed using an impedance element and a first switch and a steep waveform formed only by a second switch without using the impedance element.

According to a seventh aspect of the present invention, there is provided the semiconductor device according to the seventh aspect, wherein the erase pulse falls steeply only by the third switch without using the impedance element.

[0036] In the means for solving problems according to claim 8 of the present invention, the impedance element is a reactor included in a reactive power recovery circuit for recovering reactive power generated in a capacitance component between the display electrode pair. It is characterized by.

According to a ninth aspect of the present invention, there is provided:
The plasma display panel has a third electrode formed so as to be orthogonal to the first electrode and the second electrode, and fixes the third electrode to the ground during the application of the erase pulse. It is characterized by keeping.

According to a tenth aspect of the present invention, there is provided a method for driving a plasma display panel according to any one of the first to fifth aspects, and a method for driving a plasma display panel according to the sixth aspect. In a driving method combined with a driving method, the application timing of the priming pulse to be applied an arbitrary number of times is after the application of the erasing pulse.

The eleventh aspect of the present invention is characterized in that the erasing pulse and the priming pulse are pulses of the same polarity.

According to a twelfth aspect of the present invention, there is provided a plasma display panel driven by the plasma display panel driving method according to any one of the first to eleventh aspects.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Concept of the Invention. Electromagnetic radiation is less likely to occur as the rising portion of the pulse is gentler and less steep. The present invention takes advantage of this property.

The priming discharge is independent of the display history,
Since the priming pulse must be performed, it is necessary to apply a sufficient voltage to the priming pulse to discharge the non-lighted cell in the immediately preceding subfield. However, since this voltage is more than necessary for the cell that was lit in the immediately preceding subfield, the light emission is discharged without a discharge delay (at an earlier timing from the rising edge of the pulse) as shown in FIG. In the case of discharge in the black display state, there is a considerable discharge delay, so that the pulse shape can be designed to be advantageous for unnecessary electromagnetic radiation having a gentle rise,
The discharge timing of the cell lit in the immediately preceding subfield is earlier, and in the related art, the rising of the priming pulse is also earlier, which is disadvantageous for unnecessary electromagnetic radiation. As described above, the driving method of the plasma display panel has been studied focusing on the luminous efficiency and the like.
No prior examples have been considered to reduce unwanted electromagnetic radiation.

Embodiment 1 In the first embodiment, a structure similar to that of the plasma display panel having the structure shown in FIG. 8 is used. That is, the plasma display panel is arranged along the display line direction (first direction), and is covered by a dielectric (the dielectric layer 106 in FIG. 8) with a first electrode (corresponding to the first electrode 104 in FIG. 8). Hereafter, a plurality of display electrode pairs 1054 including an “X electrode” and a second electrode (corresponding to the second electrode 105 in FIG. 8; hereinafter, referred to as a “Y electrode”) are provided. Then, column electrodes (corresponding to the third electrode 108 in FIG. 8; hereinafter, collectively referred to as “W electrodes”) which are parallel to each other are formed along a direction orthogonal to the arrangement direction of the X electrodes and the Y electrodes. I have.

The driving method is roughly as follows.
The one shown in FIG. 9 or FIG. 10 can be used. However, Embodiment 1 of the present invention is different from the related art in that the rising waveform of the priming pulse is a composite wave of a gentle waveform and a steep waveform, as described later.

Here, as described in the background art, the priming pulse is applied to the entire surface irrespective of the display history in order to initialize the wall charge state in the cell and increase the probability of discharge. The priming pulse is 1
It is inserted once in a subfield or once in a plurality of subfields.

FIG. 1 shows a circuit diagram of the plasma display device according to the first embodiment. The plasma display device shown in FIG. 1 includes a PDP 401 having the structure shown in FIG. 8, a series resonance type reactive power recovery circuit 402, and a pulse generation circuit 403.

The PDP 401 has a capacitance Cxy between the X electrode and the Y electrode, a capacitance Cxw between the X electrode and the W electrode,
It has a capacitance Cyw between the Y electrode and the W electrode. The common connection point of the capacitances Cyw and Cxw corresponds to the W electrode, the common connection point of the capacitances Cxw and Cxy corresponds to the X electrode, and the common connection point of the capacitances Cxy and Cyw corresponds to the Y electrode. .

The reactive power recovery circuit 402 includes transistors T1 to T4, capacitors Ck1 and Ck2 (reactor impedance elements), and resonance coils Lp1 and Lp2.
And The transistors T1 to T4 are switch elements such as field effect transistors.

The pulse generation circuit 403 includes a transistor T
5 to T13. The transistors T5 to T13 are switch elements such as field effect transistors. The transistors T5 to T13 are connected to the plasma display panel 40.
This is a switch for controlling the discharge of No. 1.

In the pulse generation circuit 403, the voltage Vs
Is a voltage value when the sustain discharge is repeatedly performed.
80V. The voltage Vp is the voltage value of the priming pulse, and is set to the highest voltage value for the purpose of forcibly lighting all cells regardless of the display history, for example, about 320 V. The voltage Ve is a voltage value of an erasing pulse for erasing a cell that has undergone the sustain discharge immediately before, and may be set to be equal to or higher than the voltage Vs and equal to or lower than the voltage Vp.

Among the transistors T1 to T13, the transistors T7 to T10 correspond to the plasma display panel 40.
1 is the most important switch for displaying an image, and is sometimes called a main switch.

The voltage Vw and the voltage V
The circuit configuration for applying u is shown. Voltage Vu
Is applied so that the discharge between the X electrode and the Y electrode does not reach (does not affect) the W electrode.
It is about 0V. The voltage Vw is a lower voltage value, for example, about 60V.

The above-described configuration shown in FIG.
This shows a minimum configuration required for sustain discharge. For example, when another potential is required such as an address, a transistor is added.

FIG. 2 shows a drive waveform timing chart of the first embodiment, showing ON / OFF states of the transistors T1 to T13 and voltage waveforms Vpx, Vpy, Vpw applied to the X electrode, the Y electrode, and the W electrode. I have. In addition,
FIG. 2 shows a period from the last part of the sustain discharge period to the application of the priming pulse. Here, the reactive power is recovered at the rise and fall of the sustain pulse and at the rise of the priming pulse. Hereinafter, collecting the reactive power is referred to as a reactive power recovery operation. The reactive power recovery operation is performed by, for example, a conventional technique shown in FIG.
As described above, the reactive power associated with charging / discharging the capacitance component between the electrodes has been recovered using an LC resonance circuit, and has been used for the purpose of reducing power consumption. Reactive power is
Since the voltage increases in proportion to the number of pulses to be applied, the reactive power recovery operation is mainly applied only to sustain pulses having a large number of pulse applications.

First, immediately before time A, the transistor T
1 to T13, transistors T7, T10, T12
Is ON and the others are OFF. Further, the sustain pulse P1 is applied to the Y electrode.

Next, at time A, the transistor T7
And the transistor T2 are simultaneously turned OFF and ON, respectively.
I do. Since the transistor T7 is turned off, the voltage Vs is not supplied to the Y electrode. Since the transistor T2 is turned on, the charges charged in the capacitances Cxy and Cyw pass through the resonance coil Lp1 and the transistor T2 and are stored in the capacitor Ck1. That is, the reactive power recovery operation is started.

Next, at time B, the transistor T2
And the transistor T9 are simultaneously turned OFF and ON, respectively.
I do. Thus, the reactive power recovery operation ends.

Next, at time C, application of the sustain pulse P2 is started. That is, the transistor T10 and the transistor T3 are simultaneously turned OFF and ON, respectively. As a result, the electric charge previously stored in the capacitor Ck2 is supplied to the capacitances Cxy and Cxw through the transistor T3 and the resonance coil Lp2. Capacitance Cxy, Cx
By storing electric charge in w, the voltage Vp of the X electrode
x rises.

Next, at time D, the voltage Vpx reaches the limit value due to the supply of charges to the capacitances Cxy and Cxw. At this time, the transistors T8 and T3
Are simultaneously turned ON and OFF, respectively. by this,
The voltage Vs is supplied to the X electrode.

Next, at time E, the transistor T8
And the transistor T4 are simultaneously turned OFF and ON, respectively.
I do. Since the transistor T8 is turned off, the voltage Vs is not supplied to the X electrode. Since the transistor T4 is turned on, the charges charged in the capacitances Cxy and Cxw pass through the resonance coil Lp2 and the transistor T4 and are stored in the capacitor Ck2. That is, the reactive power recovery operation is started.

Next, at time F, the transistor T4
And the transistor T10 are simultaneously turned OFF and O
N. Thus, the reactive power recovery operation ends.

Next, at time G, the sustain discharge period ends, and the pause period starts. That is, the transistor T
12 and the transistor T13 are simultaneously turned OFF and ON, respectively. As a result, the supply of the voltage Vu is stopped, and the voltage Vpw of the W electrode becomes the ground level. During the sustain discharge period, the transistor T is used to maintain the voltage Vpw of the W electrode at a constant voltage Vu with respect to the ground.
12 is turned ON.

Next, at time H, the transistor T1
3 is turned OFF. Thereby, the transistors T11 to T11
All of T13 is turned off, and the impedance of the W electrode is sufficiently higher than those of the transistors T11 to T13. Therefore, the 403 including the transistors T11 to T13 is prevented from being destroyed when the priming pulse is applied.

Next, at time I, the suspension period ends, and the reset period starts. That is, the transistors T1 and T9 are simultaneously turned ON and O
FF. As a result, the electric charge stored in the capacitor Ck1 between the times A and B passes through the transistor T1 and the resonance coil Lp1, and is supplied to the capacitances Cxy and Cyw.
The supply of the charge to the capacitances Cxy and Cyw causes the priming pulse P3 to rise slowly. Note that time H and time I may be simultaneous. Capacitance Cx
By accumulating charges in y and Cyw, the voltage Vpy of the Y electrode increases.

Next, at time J, the voltage Vpy reaches a limit value due to the supply of charges to the capacitances Cxy and Cyw. At this time, the transistor T6 and the transistor T1
Are simultaneously turned ON and OFF, respectively. by this,
The voltage Vp is supplied to the Y electrode. The voltage value of the voltage Vp is sufficiently higher than the voltage Vs.

Next, at time K, the transistor T1
3 turns ON. As a result, the voltage Vpw of the W electrode becomes the ground level.

Next, at time L, the transistor T6
And the transistor T9 are simultaneously turned OFF and ON, respectively.
I do. As a result, the voltage Vpy of the Y electrode becomes the ground level.

At time I, transistors T11 to T11
13 are all OFF, the W electrode becomes a floating electrode and Y
As the voltage Vpy of the electrode increases, the voltage Vpw of the W electrode increases.
Also drags and rises. However, the voltage Vpw of the W electrode
Is clamped by a diode connected in parallel with the transistor T12 when the voltage Vu
Not more than u.

The priming pulse P3 may be applied to the X electrode instead of the Y electrode. In this case, the priming pulse P3 is applied by the electric charge stored in the capacitor Ck2.
3 slowly starts up, without using the capacitor Ck2,
The priming pulse sharply falls only by the transistors T1 to T13.

As described above, the rising waveform of the priming pulse P3 is obtained by using the charges stored in the capacitors Ck1 and Ck2 and the gentle waveform formed by using the transistors T1 to T13, and the charges stored in the capacitors Ck1 and Ck2. Instead, it is composed of a composite wave with a steep waveform formed only by the transistors T1 to T13. by this,
Unwanted electromagnetic radiation can be reduced.

Further, the priming pulse sharply falls only by the transistors T1 to T13 without using the capacitors Ck1 and Ck2, whereby the wall charges can be sufficiently erased by the self-erasing discharge. However, even if the priming pulse P3 falls slowly, the priming pulse P3 falls slowly using the reactive power recovery circuit 402 under conditions in which the wall charges are sufficiently erased by self-erasing discharge. You may. More specifically, at time L, the transistor T6 and the transistor T2 are simultaneously turned OFF and ON, respectively. Since the transistor T6 is turned off, the voltage Vp becomes Y
Not supplied to the electrode. Since the transistor T2 is turned on, the charges charged in the capacitances Cxy and Cyw pass through the resonance coil Lp1 and the transistor T2 and are stored in the capacitor Ck1. That is, the reactive power recovery operation is started. By this reactive power recovery operation, the priming pulse P3 falls slowly.

Further, as described above, the voltage Vpw of the W electrode falls before the time L when the priming pulse P3 falls, and when the priming pulse falls,
It is assumed that the voltage Vpw of the W electrode is fixed to the ground.
Thus, when the priming pulse P3 falls, the W electrode does not function as an antenna to increase unnecessary electromagnetic radiation. In addition, since the W electrode also serves as a ground plane, an electric field leaking from the Y electrode to the outside can be suppressed, and the level of unnecessary electromagnetic radiation can be further reduced.

Further, since the rising of the priming pulse P3 is not sharpened, the priming pulse P3 is reduced by employing the transistor T6 having a small ON resistance.
It is better to increase the peak current of No. 3 and not make the rising steep. Therefore, a transistor having a high ON resistance, that is, a transistor having a low price can be adopted as the transistor T6.

As described above, in the first embodiment, attention is paid to the fact that the rising of the pulse becomes slower when the reactive power recovery operation is performed. By performing the operation, the priming pulse is slowly started to reduce unnecessary electromagnetic radiation.

The essence of the first embodiment is to make the rising of the priming pulse P3 gentle. Therefore, for example, the transistor T6 for supplying the priming voltage Vp is not turned on immediately after the collection operation is performed at time J in FIG. The voltage may be raised to Vs, and then the voltage may be raised to Vp. Alternatively, a separate switch may be provided to form a plurality of steps of stepwise pulses.

Embodiment 2 In the second embodiment, the operation of the first embodiment is replaced with FIG. 2 to FIG.
FIG. 3 shows a period from the last part of the sustain discharge period to the application of the erase pulse. For example, from the end of the sustain discharge period of the subfield A shown in FIG. This corresponds to a period until an erase pulse is applied in the period.

In the second embodiment, even at the rise of the erase pulse, the reactive power recovery operation is performed, so that the erase pulse is slowly started to reduce unnecessary electromagnetic radiation.

The erasing pulse is as described in the prior art. That is, the erasing pulse is applied to one of the X electrode and the Y electrode after the end of the discharge sustaining period in which the gas discharge is repeatedly generated by applying a pulse voltage of which polarity is alternately applied to the X electrode and the Y electrode. You. Thereby, the display history is reset. Further, the pulse width of the erase pulse is smaller than the pulse width applied during the sustain period.

First, the sustain discharge period up to time G is the same as the sustain discharge period of the first embodiment.

In the idle period from time G to time M, unlike the first embodiment, the transistors T1 to T13 are in the same state.

Next, at time M, as in the first embodiment, the suspension period ends, and the reset period starts. That is, the transistor T1 and the transistor T9 are simultaneously turned ON and OFF, respectively. By this, time A ~
B, the electric charge stored in the capacitor Ck1 passes through the transistor T1 and the resonance coil Lp1, and passes through the capacitances Cxy, Cxy
supply to yw. The supply of the charges to the capacitances Cxy and Cyw causes the erase pulse P4 to rise slowly.

Next, at time N, the voltage Vpy reaches a limit value due to the supply of charges to the capacitances Cxy and Cyw. At this time, unlike the first embodiment, the transistor T
5 and the transistor T1 are simultaneously turned ON and OF, respectively.
F. As a result, the voltage Ve is supplied to the Y electrode,
The voltage Vpy of the Y electrode becomes the voltage Ve. The voltage Ve is equal to or higher than the voltage Vs, but is set so as not to damage the pulse generation circuit 403.

Next, at time O, the transistor T6
And the transistor T9 are simultaneously turned OFF and ON, respectively.
I do. As a result, the voltage Vpy of the Y electrode becomes ground.

The erase pulse P4 is not a Y electrode, but
X electrode, in which case the capacitor Ck2
Causes the erase pulse P4 to rise slowly.

As described above, the rising waveform of the erasing pulse P4 is obtained by using the charges stored in the capacitors Ck1 and Ck2 and the gentle waveform formed by using the transistors T1 to T13 and the charges stored in the capacitors Ck1 and Ck2. Instead, it is composed of a composite wave with a steep waveform formed only by the transistors T1 to T13. Thereby, unnecessary electromagnetic radiation can be reduced.

From time M to time O, the transistor T13 remains ON. As a result, when the erase pulse P4 falls, the W electrode does not function as an antenna to increase unnecessary electromagnetic radiation.

Furthermore, the wall charge can be sufficiently erased by not using the reactive power recovery circuit 402 at the falling edge of the erase pulse.

In particular, after the discharge is generated by raising the erase pulse, it is necessary to lower the erase pulse before the space charge generated at that time does not disappear. For this reason, the pulse width of the erasing pulse is reduced, which is a factor that increases unnecessary electromagnetic radiation. Specifically, the pulse width of the erase pulse is 3 μsec or less. An erase pulse of 3 μsec or less is called a narrow erase pulse. However, according to the second embodiment, at the rise of the erase pulse which does not relatively affect the erase operation, the reactive power recovery circuit 4
02, the erase pulse can rise slowly, while the fall portion of the erase pulse, which greatly affects the erase operation, has a steep falling waveform without using the reactive power recovery circuit 402. Unnecessary electromagnetic radiation can be suppressed while performing a reliable erasing operation.

Embodiment 3 The third embodiment is a combination of the first embodiment and the second embodiment.

FIG. 4 shows a drive waveform timing chart of the third embodiment, showing ON / OFF states of the transistors T1 to T13, and voltage waveforms Vpx, Vpy and Vpw applied to the X electrode, the Y electrode and the W electrode. I have. In addition,
FIG. 4 shows a period from the last part of the sustain discharge period to the application of the priming pulse. The operation of the transistors T1 to T13 at time E to time O in FIG.
The operation of the transistors T1 to T13 from time H to time L in FIG. 4 is the same as the operation of the transistors T1 to T13 from time E to time O in FIG. Operation is the same as In addition, about the operation | movement before time E of FIG. 4, time A of FIG.
Since it is the same as time D, it is omitted.

The operation immediately after time A to time G is the same as in the first and second embodiments. From time A to time B, the reactive power recovery operation is started, and charges are stored in the capacitor Ck1.

As in the second embodiment, the electric charge stored in the capacitor Ck1 is changed from the capacitance Cx to the capacitance Mx from time M to time N.
y, Cyw, the erase pulse P4
Slowly rises to the voltage Ve. Note that time M
-Design is made so that all the charges stored in the capacitor Ck1 are not discharged at time N.

Next, the charge remaining in the capacitor Ck1 is supplied to the capacitances Cxy and Cyw from time I to time J as in the first embodiment, so that the erase pulse P4 rises slowly.

As described above, in the third embodiment, the application timing of the priming pulse P3 is after the application of the erase pulse P4.

FIG. 4 shows a case where sufficient electric charge does not remain in the capacitor Ck1 at the time I. In this case, since the voltage Vpy does not reach the voltage Vp by time J, P3 rises sharply at time J.
However, even if sufficient charge does not remain in the capacitor Ck1 at the time I, the priming pulse P3 rises slowly, so that unnecessary electromagnetic radiation can be reduced.

As described above, if the erase pulse P4 is applied before the priming pulse P3, the priming pulse P
Before the occurrence of 3, the wall charge is erased. Therefore,
The light emission waveform of the priming pulse P3 can be a gentle waveform accompanied by a discharge delay, similar to the light emission waveform when the black screen is displayed in FIG. Therefore, even if no charge remains in the capacitor Ck1 at the time I, the priming pulse P3 gradually rises at least by the discharge delay. This makes it possible to reduce unnecessary electromagnetic radiation. actually,
From FIG. 12, for example, the priming pulse P3 having a rising speed of 300 V / 500 nsec is 300 V / 500 nsec.
It is possible to slow down to about 1 μsec.

The erase pulse P4 and the priming pulse P3 are both pulses of the same polarity, so that a part of the charge previously stored in the capacitor Ck1 is used for the erase pulse P4, and the rest is used for the priming pulse P3. And the driving sequence can be simplified.

Embodiment 4 The fourth embodiment is an improvement over the first to third embodiments, and relates to the fall of the voltage Vpw of the W electrode.

FIG. 5 shows the voltage Vpw of the W electrode according to the third embodiment.
4 shows a drive waveform timing chart before and after the fall of the drive waveform.
5 correspond to time G and time K in FIG.
4 or the time G in FIG. It should be noted that only the portion related to the fall of the voltage Vpw of the W electrode is shown, and the other portions are the same as in FIGS.

As shown in FIG. 5, when the voltage Vpw of the W electrode falls, unnecessary electromagnetic radiation is further reduced by falling in two steps.

First, immediately before time α, the transistors T11 to T13 are OFF, ON, and OFF, and the voltage Vpw of the W electrode is the voltage Vu.

Next, at time α, the transistor T1
1 and the transistor T12 are simultaneously turned ON and O
FF. As a result, the voltage Vw is supplied to the W electrode, and the voltage Vpw of the W electrode becomes the voltage Vw.

Next, at time β, the transistor T1
3 turns ON. Thereby, the ground is supplied to the W electrode, and the voltage Vpw of the W electrode becomes the ground.

Note that the period from time α to time β is several hundreds.
A value of about ns is desirable, but not limited to this value.

As described above, when the W electrode is fixed to the ground, the voltage Vw is used to gradually lower the W electrode to the ground. As a result, the amount of change in the voltage Vpw of the W electrode per unit time is reduced, and the current flowing when the voltage changes can be dispersed in two stages. Current is 2
Since the current is dispersed in stages, the peak value of the current decreases. Therefore, unnecessary electromagnetic radiation is generated due to fluctuation of the ground due to the peak current, but unnecessary electromagnetic radiation can be reduced because the peak current is reduced. In addition,
In FIG. 5 described above, the W electrode is lowered to the ground in two steps using the voltage Vw.
The W electrode may be lowered to the ground at a stage or more.

Embodiment 5 FIG. Although the first to fourth embodiments have been described using the series resonance type reactive power recovery circuit 402,
A parallel resonance type reactive power recovery circuit may be used.

FIG. 6 is a circuit diagram of a plasma display device according to the sixth embodiment. The plasma display device shown in FIG. 6 includes a PDP 401 having a structure shown in FIG. 8, a parallel resonance type reactive power recovery circuit 502, and a pulse generation circuit 4 shown in FIG.
03.

The reactive power recovery circuit 502 includes transistors T14 and T15, and resonance coils Lp3 and Lp4 (reactor impedance elements). Transistor T
14, T15 are switch elements such as field effect transistors.

FIG. 7 is a drive waveform timing chart according to the fifth embodiment, showing ON / OFF states of the transistors T5 to T15, and voltage waveforms Vpx, Vpy and Vpw applied to the X electrode, the Y electrode, and the W electrode. I have. In addition,
FIG. 7 shows a period from the last part of the sustain discharge period to the application of the priming pulse.

First, at time P, the transistor T8 is turned off.
When the transistor T15 is turned on, the electric charge stored in the capacitance Cxy is changed to the transistor T15,
When a current flows through the capacitance Cxy through the resonance coil Lp3, the polarity is inverted. The voltage Ve is applied to the Y electrode by turning on the transistors T5 and T10 at time R when the maximum current flows. At this time, the potential of the W electrode is grounded after time Q. This is the first embodiment
Similarly, the reactive power recovery circuit 502 is operated for the purpose of dulling the waveform at the rise of the erase pulse. Since the series resonance type reactive power recovery circuit 402 has an external capacitance, the electric charge can be extracted from the external capacitance at an arbitrary time and the waveform can be blunted. Due to the configuration of the recovery circuit 502, a sustain pulse must be provided immediately before the erase pulse. For the same reason, a dummy pulse is provided in the period from time T to time W before the application of the priming pulse. The discharge is not performed even if the sustain pulse is applied unless the write operation is performed since the erase pulse is applied. However, the situation where the space charge remains may cause an erroneous discharge, so that the time S ~
It is desirable that the time T is separated by 20 μsec or more. Further, the transistor T12 is operated for the purpose of suppressing discharge from the W electrode by the dummy pulse.

In the fifth embodiment, the voltage Vpw is set to the ground when the voltage Vpx is approximately at the ground, and then the transistor T13 is turned off and the W electrode is set to the high impedance. Instead, the voltage may be clamped to the voltage Vu from the dummy pulse to the priming pulse. The rising of the dummy pulse is steep because the reactive power recovery operation cannot be applied. However, by making the pulse width (time T to time U) sufficiently long, the fundamental frequency of the pulse is reduced. , Unnecessary electromagnetic radiation can be reduced.

Further, by performing the reactive power recovery operation on the trailing edge of the dummy pulse, the polarity of the charge stored in the panel capacitor can be inverted and reused as in the previous erase pulse. Of the priming pulse can be blunted. Thus, even when the parallel resonance type reactive power recovery circuit 502 is used and the erase pulse and the priming pulse are provided with the same polarity, a round waveform using the reactor of the reactive power recovery circuit 502 is formed at the rise of both pulses. be able to.

Modified example. Note that Embodiments 1 to 5 correspond to FIG.
Although the present invention is applied to a plasma display panel, the present invention may be applied to a structure having another structure. For example, the present invention may be applied to a structure in which one of an X electrode and a Y electrode is covered with a dielectric and the other is not covered. Good.

[0114]

According to the first aspect of the present invention, the priming pulse can gradually rise. Thereby, unnecessary electromagnetic radiation can be reduced.

According to the second aspect of the present invention, the wall charges can be sufficiently erased.

According to the third aspect of the present invention, a reactive power recovery circuit can be used.

According to the fourth aspect of the invention, the third electrode does not function as an antenna to increase unnecessary electromagnetic radiation.

According to the fifth aspect of the invention, unnecessary electromagnetic radiation can be further reduced.

According to the sixth aspect of the present invention, the erase pulse can be made to gradually rise. Thereby, unnecessary electromagnetic radiation can be reduced.

According to the present invention, the wall charges can be sufficiently erased.

According to the invention of claim 8, a reactive power recovery circuit can be used.

According to the ninth aspect, the third electrode does not function as an antenna to increase unnecessary electromagnetic radiation.

According to the tenth aspect, the driving sequence can be simplified.

According to the eleventh aspect of the present invention, since the priming pulse is applied in a state where there is substantially no wall charge after the application of the erasing pulse, the emission waveform of the priming pulse is different from the emission waveform at the time of displaying a black screen. You can do the same.

According to the twelfth aspect of the present invention, unnecessary electromagnetic radiation is reduced in the plasma display device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a plasma display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing driving waveforms of the plasma display device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing driving waveforms of the plasma display device according to the second embodiment of the present invention.

FIG. 4 is a timing chart showing driving waveforms of the plasma display device according to Embodiment 3 of the present invention.

FIG. 5 is a timing chart showing driving waveforms of the plasma display device according to Embodiment 4 of the present invention.

FIG. 6 is a block diagram showing an overall configuration of a plasma display device according to a fifth embodiment of the present invention.

FIG. 7 is a timing chart showing driving waveforms of the plasma display device according to Embodiment 5 of the present invention.

FIG. 8 is a perspective view showing a structure of a conventional AC surface discharge type plasma display panel.

FIG. 9 is a timing chart showing one subfield driving waveform of the conventional plasma display device.

FIG. 10 is a timing chart showing driving waveforms of a conventional plasma display device.

FIG. 11 is a diagram showing a relationship between an erase pulse width and a voltage value of an erase pulse in a conventional plasma display device.

FIG. 12 is a diagram showing a voltage waveform and a light emission waveform during priming of a conventional plasma display device.

FIG. 13 is a diagram illustrating a configuration of a parallel resonance type reactive power recovery circuit according to a conventional plasma display device.

FIG. 14 is a diagram illustrating a configuration of a series resonance type reactive power recovery circuit according to a conventional plasma display device.

[Explanation of symbols]

401 plasma display panel, 402, 502
Reactive power recovery circuit, 403 pulse generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 622 G09G 3/20 622C (72) Inventor Takayoshi Nagai 2-3-2 Marunouchi, Chiyoda-ku, Tokyo No. Mitsubishi Electric Corporation F-term (reference) 5C080 AA05 BB05 DD12 DD26 EE25 EE29 FF12 GG02 GG08 GG12 HH02 HH04 JJ03 JJ04 JJ05 JJ06 KK02 KK43

Claims (12)

[Claims] 1. A first device, at least one of which is covered with a dielectric
A method for driving a plasma display panel having a plurality of display electrode pairs each including an electrode and a second electrode, wherein the priming pulse is applied to one of the first and second electrodes. Characterized in that the rising waveform is composed of a composite wave of a gentle waveform formed by using an impedance element and a first switch and a steep waveform formed only by a second switch without using the impedance element. A method for driving a plasma display panel. 2. The method of driving a plasma display panel according to claim 1, wherein the falling of the priming pulse does not use the impedance element but falls sharply only by a third switch. 3. The reactor according to claim 1, wherein the impedance element is a reactor included in a reactive power recovery circuit for recovering reactive power generated in a capacitance component between the display electrode pair. A method for driving a plasma display panel. 4. The plasma display panel has a third electrode formed to be orthogonal to the first electrode and the second electrode, and the third electrode is formed before the priming pulse is raised.
4. The method according to claim 1, wherein the first electrode is a floating electrode, and the third electrode is fixed to the ground before the priming pulse falls. 5. The method according to claim 4, wherein when the third electrode is fixed to the ground, the third electrode is gradually lowered to the ground. 6. A first device, at least one of which is covered with a dielectric material
In a plasma display panel having a plurality of display electrode pairs including an electrode and a second electrode, a driving method of the plasma display panel in which an erase pulse is applied to one of the first and second electrodes, wherein a rising waveform of the erase pulse Characterized by a composite wave of a gentle waveform formed by using an impedance element and a first switch and a steep waveform formed only by a second switch without using the impedance element. Drive method. 7. The method of driving a plasma display panel according to claim 6, wherein the erasing pulse falls sharply only by a third switch without using the impedance element. 8. The reactor according to claim 6, wherein the impedance element is a reactor included in a reactive power recovery circuit for recovering reactive power generated in a capacitance component between the display electrode pair. A method for driving a plasma display panel. 9. The plasma display panel has a third electrode formed so as to be orthogonal to the first electrode and the second electrode, and the third electrode is applied during a period in which the erase pulse is applied. 9. The electrode according to claim 6, wherein the electrode is fixed to the ground.
The method for driving a plasma display panel according to any one of the above. 10. A driving method combining the method for driving a plasma display panel according to any one of claims 1 to 5 and the method for driving a plasma display panel according to any one of claims 6 to 9; Wherein the application timing of the priming pulse is applied after the application of the erase pulse. 11. The method according to claim 10, wherein the erase pulse and the priming pulse are pulses of the same polarity. 12. A plasma display device comprising a plasma display panel driven by the method for driving a plasma display panel according to claim 1. Description: