JP2000180768A - Image-forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the drive current of an LD so that the light quantity of the LD becomes constant, when a power source is turned on by prolonging the active section of a first sampling signal after the power source is turned on and shortening those of a second and subsequent signals. SOLUTION: When the power source is turned on, a signal outputted from a voltage detector 21 is switched from L to H. The signal outputted from the detector 21 is applied to a one-shot multivibrator 22, and a signal outputted from the vibrator 22 is applied to the input terminal of an inverter 23 and one input terminal of an AND gate 25. Then, a signal outputted from the inverter 23 is applied to one input terminal of an AND gate 24, and a timer signal T4 having comparatively short pulse width T4 is applied to the other input terminal of the gate 24. Moreover, a timer signal T3, having comparatively long pulse width T3, is applied to the other input terminal of the gate 25. Then, respective signals outputted from the gates 24 and 25 are applied to an OR gate 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus for forming a latent image on a photosensitive member by scanning an LD (laser diode) light, and more particularly to a method of sampling a monitor current of an LD light while a sampling signal is active. APC (Automatic Power Control) that controls the LD drive current so that the LD light amount becomes constant based on the hold value
r Control).

[0002]

2. Description of the Related Art This type of APC circuit is disclosed in
As described in Japanese Unexamined Patent Publication No. 226675/1996 and Japanese Unexamined Patent Publication No. Hei 8-88429, a monitor current of a diode for monitoring the amount of LD light is converted into a voltage, the monitor voltage is sampled, and the monitor voltage or the monitor voltage and a reference voltage are compared. The difference is held, and the drive current of the LD is controlled based on the hold value so that the LD light amount becomes constant.

[0003]

However, in the above conventional example, when the power is turned on, the charge of the hold element is "0".
Therefore, there is a problem that the drive current of the LD does not reach an appropriate value, so that the amount of LD light does not reach the appropriate value, or that an overcurrent flows through the LD to deteriorate the LD.

The present invention has been made in consideration of the above-described problems of the related art, and has as its object to provide an image forming apparatus capable of controlling a drive current of an LD so that an LD light amount becomes constant when power is turned on.

[0005]

According to a first aspect of the present invention, there is provided an image forming apparatus for forming a latent image on a photoreceptor by scanning an LD light to achieve the above object. APC means for sampling and holding while the signal is active, controlling the drive current of the LD so that the LD light quantity is constant based on the hold value, and extending the first active section of the sampling signal after power-on. And a sampling signal generating means for shortening the second and subsequent times.

The second means is that, in the first means, the sampling signal generating means converts the sampling signal to L
It is characterized in that it is generated at the cycle of the scan synchronization detection signal of D light.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram illustrating an LD scanning optical system according to an embodiment of the image forming apparatus according to the present invention, FIG. 2 is a block diagram illustrating a synchronization detection circuit of the image forming apparatus illustrated in FIG. 1, and FIG. 4 is a timing chart showing a synchronization detection signal of the circuit, FIG. 4 is a block diagram showing a sample / hold signal generation circuit of the image forming apparatus of FIG. 1, FIG. 5 is a waveform diagram showing a timer signal of FIG. 4, and FIG. A of the image forming apparatus
FIG. 3 is a block diagram showing a PC circuit.

In the LD scanning optical system shown in FIG. 1, LD light modulated according to image data is emitted from an LD 2 mounted on an LD control plate 1, and this LD light is collimated by a collimating lens 3 and then collimated. The polygon scanner 4 is deflected at a constant angular velocity in the main scanning direction. Next, the LD light is corrected to have a constant velocity deflection by the fθ lens 5 and is irradiated onto the photoreceptor 6, whereby a latent image is formed on the photoreceptor 6.

Further, the LD light is received by the synchronization detecting element 7 every time scanning is performed in the main scanning direction. When the synchronization detection element 7 is L
When the D light is received, a current I flows through the synchronous detection element 7, and
As shown in (1), the comparator 8 outputs a synchronization detection signal XDETP which becomes active L when R1 × I> Vref. This synchronization detection signal XDETP is, as shown in FIG.
Active L during the section T1 at the beginning of one line cycle T2
And / R of the NAND SR-FF 27 shown in FIG.
Applied to terminal. Therefore, the SR-FF 27 is reset when the synchronization detection signal XDETP becomes active low, and its / Q output signal becomes active low.

In FIG. 4, the output signal of the voltage detector 21 switches from L to H when the power is turned on. The output signal of this voltage detector 21 is applied to a one-shot multivibrator
2 is applied to the input terminal of the inverter 23 and one input terminal of the AND gate 25. Inverter 2
The output signal of No. 3 is applied to one input terminal of the AND gate 24, and the timer signal T4 having a relatively short pulse width T4 is applied to the other input terminal of the AND gate 24. The timer signal T3 having a relatively long pulse width T3 is applied to the other input terminal of the AND gate 25, and the output signals of the AND gates 24 and 25 are applied to the OR gate 26. The output signal of the OR gate 26 is / S of the SR-FF 27
The synchronization detection signal XDETP shown in FIG. 3 is applied to the / R terminal of the SR-FF 27. Then, an S / H signal as shown in FIG. 5 is generated from the / Q terminal of the SR-FF 27, and the control circuit 1 shown in FIG.
3 is applied.

In such a configuration, when the power is turned on and the output signal of the voltage detector 21 switches from L to H, the output signal of the one-shot multivibrator 22 becomes H for a certain time. Further, since the SR-FF 27 is reset when the synchronization detection signal XDETP becomes active L, the / Q signal becomes active L. While the output signal of the one-shot multivibrator 22 is H, the timer signal T3 having a relatively long pulse width T3 becomes active H, and therefore, the AND gate 25 and the OR gate 26
Becomes H (the output signal of the AND gate 24 is L). Next, when the section T3 of the timer signal T3 elapses,
The output signals of the AND gates 24 and 25 and the OR gate 26 become L, the SR-FF 27 is set and the SR-FF 27
The / Q signal of H becomes H. Thus, the / Q signal is active low for a relatively long time as shown in FIG.

Next, a one-shot multivibrator 2
The output signal of No. 2 becomes L after the above-mentioned fixed time elapses, and the timer signal T4 having a relatively short pulse width T4 becomes active H. Therefore, the output signals of the AND gate 24 and the OR gate 26 become H (the output signal of the AND gate 25 becomes L). Further, since the SR-FF 27 is reset when the synchronization detection signal XDETP becomes active L, the / Q signal becomes active L. Next, when the section T4 of the timer signal T4 elapses, the AND gate 24,
25 and the output signal of the OR gate 26 become L,
FF27 is set and the / Q signal of SR-FF27 is set to H
become. Thus, the / Q signal is active low for a relatively short and long time as shown in FIG. And this / Q
The signal is used as a sample / hold (S / H) signal of the control circuit 13 shown in FIG.

Next, an APC circuit according to the present invention will be described in detail with reference to FIG. The APC circuit is configured to be able to switch between the monitor voltage and the reference voltage when switching the pixel density. The LD 2 is provided with a monitor diode (PD) 11 for receiving the light amount. The monitor current Im is applied to one input terminal of a comparator 12 as a monitor voltage V2, and a monitor voltage switch SW1 and a pixel density switch are provided. The signal IN1 is selectively applied to the line of the variable resistor VR1 or the line of the variable resistor VR2.

The monitor voltage V2 applied to the comparator 12 becomes V2 = Im * VR1 when the line of the variable resistor VR1 is selected, and V2 when the line of the variable resistor VR2 is selected. = Im * VR2. The reference voltage Vref1 or Vref2 is selectively applied to the other input terminal of the comparator 12 as the reference voltage V1 by the reference voltage changeover switch SW2 and the pixel density changeover signal IN2. The output signal V3 of the comparator 12 goes high when V2> V1, and goes low when V2> V1.

When the output signal V3 of the comparator 12 becomes high, the control circuit 13 switches the capacity changeover switch S
Turn on W4. When the switch SW4 is turned on, the charging constant current source 14 is connected to one input terminal (input voltage V4) of the error amplifier 16 via the switch SW4 and to one end of the capacitance changeover switch SW3. Switch SW3 and its switching signal IN
3 selectively connects to the capacitor C1 or C2. Therefore, when the capacitor C1 or C2 is charged, the voltage V applied to one input terminal of the error amplifier 16 is
4 rises.

On the other hand, when the output signal V3 of the comparator 12 becomes low, the control circuit 13 turns on the switch SW5. When the switch SW5 is turned on,
The charge charged in the capacitor C1 or C2 is discharged to the discharging constant current source 15, and the voltage V4 applied to one input terminal of the error amplifier 16 decreases.

The control circuit 13 switches between sampling and holding by a sample / hold (S / H) signal. When the S / H signal is high (image section), the output signal V3 of the comparator 12 is high as described above. , One of the switches SW4 and SW5 is turned on in accordance with the row. On the other hand, when the S / H signal is low (synchronization detection section), the control circuit 13
Both W4 and SW5 are turned on, whereby the voltage V4 applied to one input terminal of the error amplifier 16 is held at a constant value. In the error amplifier 16, this input voltage V4
The reference voltage Vref3 is amplified by the error, whereby the collector current of the transistor Tr1 increases and decreases, and the drive current of the LD2 increases and decreases, and the light amount of the LD2 is controlled to the set value.

Next, a case where the pixel density is switched will be described. An example of switching between 600 dpi and 1200 dpi will be described. VR1 = 1 kΩ, VR2 = 2
When VR is set to 1 kΩ for 600 dpi and VR2 = 2 kΩ for 1200 dpi, the input of the comparator 12 is controlled so that V1 = V2.
It is の of the case of 0 dpi.

Here, if the values of the variable resistors VR1 and VR2 are increased and the monitor current Im becomes too large, the setting accuracy of the LD light quantity deteriorates. Therefore, in this case, if the reference voltages V1 (Vref1, Vref2) of the comparator 12 are reduced, the values of the variable resistors VR1, VR2 do not need to be too large. For example, when Vref1 = 1V and Vref2 = 2V, Vref1 = 1V is selected when the monitor current Im is small, and Vref2 = 2V is selected when the monitor current Im is large.

When the control circuit 13 is in the hold mode, the input voltage V4 of the error amplifier 16 is held by the capacitor C1 or C2.
1, when the capacitance value of C2 is relatively large, the input voltage V4
Is held constant for a relatively long time, while the input voltage V4 is held constant for a relatively short time when the capacitance values of the capacitors C1 and C2 are relatively small. Therefore, when the capacitance values of the capacitors C1 and C2 are relatively small, there is an advantage that the time required for the potential of the input voltage V4 to be charged to the set value is short.

When the synchronization detection signal XDETP is used to generate the S / H signal of the control circuit 13, for example, if C1 = 1 μF and C2 = 0.01 μF, the period of the synchronization detection signal XDETP is long. Is C1
= 1 μF, and when the period of the synchronization detection signal XDETP is short, C2 = 0.01 μF may be selected. C1
When = 1 μF is selected, the time required to reach the set light amount becomes longer, but the time during which the light amount is held constant becomes longer. Therefore, since the APC control is performed so that the monitor current Im becomes constant, the LD light amount can be automatically controlled with a simple configuration when the linear speed is changed according to the pixel density to switch the LD light amount.

[0022]

As described above, according to the first aspect of the present invention, the first active section of the sampling signal after the power is turned on is lengthened and the second and subsequent sampling signals are shortened. L so that the LD light amount is constant
D drive current can be controlled.

According to the second aspect of the present invention, the sampling signal is generated at the period of the scanning synchronization detection signal of the LD light.
Can be controlled.

[Brief description of the drawings]

FIG. 1 is an LD of an embodiment of an image forming apparatus according to the present invention.
FIG. 2 is a configuration diagram illustrating a scanning optical system.

FIG. 2 is a block diagram illustrating a synchronization detection circuit of the image forming apparatus of FIG. 1;

FIG. 3 is a timing chart illustrating a synchronization detection signal of the synchronization detection circuit of FIG. 2;

FIG. 4 is a block diagram illustrating a sample and hold signal generation circuit of the image forming apparatus of FIG. 1;

FIG. 5 is a waveform diagram showing a timer signal of FIG. 4;

FIG. 6 is a block diagram illustrating an APC circuit of the image forming apparatus of FIG. 1;

[Explanation of symbols]

 2 LD (laser diode) 11 PD (photodiode) 12 comparator 13 control circuit 14 constant current source for charging 15 constant current source for discharging 16 error amplifier SW1 monitor voltage switch VR1, VR2 variable resistor SW2 reference voltage switch Vref1, Vref2 Reference voltage SW3 to SW5 Capacitance change switch C1, C2 Capacitor 21 Voltage detector 27 SR-FF

Claims (2)

[Claims] 1. An image forming apparatus for forming a latent image on a photosensitive member by scanning an LD light, wherein the monitor current of the LD light is sampled and held while a sampling signal is active, and based on the hold value. APC means for controlling the drive current of the LD so that the LD light quantity becomes constant, and sampling signal generation means for lengthening the active section of the first sampling signal after power-on and shortening the second and subsequent sampling signals. An image forming apparatus comprising: 2. The image forming apparatus according to claim 1, wherein the sampling signal generation unit generates the sampling signal at a period of a scanning synchronization detection signal of LD light.