JP2000180706A - Signal processor and image pickup device - Google Patents
Signal processor and image pickup deviceInfo
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- JP2000180706A JP2000180706A JP10357620A JP35762098A JP2000180706A JP 2000180706 A JP2000180706 A JP 2000180706A JP 10357620 A JP10357620 A JP 10357620A JP 35762098 A JP35762098 A JP 35762098A JP 2000180706 A JP2000180706 A JP 2000180706A
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- 238000009825 accumulation Methods 0.000 claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 6
- 101100134625 Arabidopsis thaliana NUP88 gene Proteins 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
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- 238000003384 imaging method Methods 0.000 description 2
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- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の信号源と、
それぞれの信号源の個々の信号と、複数の信号源中の少
なくとも最大値信号又は最小値信号を出力できる信号処
理装置に関するものである。TECHNICAL FIELD The present invention relates to a plurality of signal sources,
The present invention relates to a signal processing device capable of outputting individual signals of respective signal sources and at least a maximum value signal or a minimum value signal among a plurality of signal sources.
【０００２】[0002]
【従来の技術】従来、映像信号以外に映像信号の最大値
と最小値を出力する光電変換装置として、一眼レフカメ
ラ用のオートフォーカスセンサが知られている。これら
の光電変換装置は、映像信号の最大値と最小値を基に、
蓄積時間、ゲイン制御を行うオートゲインコントロール
を行っている。図１０にＢＡＳＩＳを用いたＡＦセンサ
の既略的回路構成図を示す。簡単のため３画素構成のラ
インセンサとしているが通常は数１０〜１００ｂｉｔ程
度で構成されている。2. Description of the Related Art Conventionally, an autofocus sensor for a single-lens reflex camera has been known as a photoelectric conversion device that outputs a maximum value and a minimum value of a video signal in addition to the video signal. These photoelectric conversion devices, based on the maximum and minimum values of the video signal,
Auto gain control is performed to control the accumulation time and gain. FIG. 10 shows a schematic circuit configuration diagram of an AF sensor using BASIS. For the sake of simplicity, a line sensor having a three-pixel structure is used.
【０００３】同図において、５１はｎｐｎフォトトラン
ジスタ、５２は、フォトトランジスタの光電変換部のベ
ースをリセットするＰＭＯＳトランジスタ、５３はエミ
ッタを接地するためのｎＭＯＳトランジスタ、５４は最
大値（ＰＥＡＫ）を検出するための差動増幅器、５５は
最小値（ＢＴＭ）を検出するための差動増幅器、５６は
最大値回路用の定電流源、５７は最小値回路用の定電流
源、５８はノイズ電荷を蓄積する容量ＣTN，５９は信号
電荷を蓄積する容量ＣTS，６０，６１はスイッチＭＯＳ
トランジスタ、６２，６３は転送用ＭＯＳトランジスタ
で走査回路６４で駆動される。６５，６６はバッファ増
幅器、６７は差動増幅器であり、ノイズを除去した映像
出力を出力する。In FIG. 1, reference numeral 51 denotes an npn phototransistor; 52, a PMOS transistor for resetting a base of a photoelectric conversion unit of the phototransistor; 53, an nMOS transistor for grounding an emitter; and 54, a maximum value (PEAK). 55, a differential amplifier for detecting a minimum value (BTM), 56, a constant current source for a maximum value circuit, 57, a constant current source for a minimum value circuit, and 58, a noise charge. The storage capacitors C TN and 59 are the capacitors C TS for storing signal charges, and the switches C and 60 are switch MOSs.
The transistors 62 and 63 are transfer MOS transistors and are driven by the scanning circuit 64. 65 and 66 are buffer amplifiers, and 67 is a differential amplifier, which outputs a video output from which noise has been removed.
【０００４】ここで最大値回路ＰＡ′と最小値回路Ｂ
Ａ′は図１１に示す回路となっている最大値検出回路は
出力段がｎｐｎトランジスタ最小値検出回路は、ｐｎｐ
トランジスタとなっている。ここで簡単に最大値出力原
理と述べる。各最大値回路ＰＡ′の出力が結線され定電
流源５６に接続されていると、最大値画素のｎｐｎトラ
ンジスタがオンする事により、他のＰＡ′のｎｐｎトラ
ンジスタはベースよりもエミッタ電位が高くなり、オフ
するといった原理である。これを図１２に示した。Here, a maximum value circuit PA 'and a minimum value circuit B
A ′ is a maximum value detection circuit which is the circuit shown in FIG. 11, the output stage is an npn transistor minimum value detection circuit, and pnp
It is a transistor. Here, the principle of maximum value output will be simply described. If the output of each maximum value circuit PA 'is connected and connected to the constant current source 56, the npn transistor of the maximum value pixel is turned on, so that the npn transistor of the other PA' has a higher emitter potential than the base. , Turn off. This is shown in FIG.
【０００５】従来例において、回路ブロックは、光電変
換部，最大値検出部，最小値検出部，映像信号出力部の
４ブロックで構成されている。In the conventional example, the circuit block is composed of four blocks: a photoelectric conversion unit, a maximum value detection unit, a minimum value detection unit, and a video signal output unit.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来例では、映像信号をシリアルに出力させる回路、映像
信号の最大値を出力させる回路、映像信号の最小値を出
力させる回路の３つの回路が各画素列に設けられている
ため以下の様な問題があった。However, in the above-mentioned conventional example, three circuits, a circuit for outputting the video signal serially, a circuit for outputting the maximum value of the video signal, and a circuit for outputting the minimum value of the video signal, are provided. Since it is provided in the pixel column, there are the following problems.
【０００７】回路素子数が多いためチップ面積が大き
くなる。Since the number of circuit elements is large, the chip area becomes large.
【０００８】それぞれの回路の製造バラツキ等によ
り、出力オフセットが発生する。本出願に係る第１の発
明の目的は、回路素子数を減らしてチップ面積を縮小さ
せることであり、第２の発明の目的はノイズを減少させ
ることである。[0008] An output offset occurs due to manufacturing variations of the respective circuits. An object of the first invention according to the present application is to reduce the chip area by reducing the number of circuit elements, and an object of the second invention is to reduce noise.
【０００９】[0009]
【課題を解決するための手段】上記の課題を解決するた
めに、請求項１のように複数の信号源と、前記複数の信
号源の最大値信号又は最小値信号を出力する特定値検出
手段とを有し、前記特定値検出手段は、前記複数の信号
源のそれぞれからの個別信号を順次出力する機能を兼ね
備え、さらに、前記特定値検出手段の機能を切り替える
駆動手段を有することを特徴とする信号処理装置を提供
する。In order to solve the above-mentioned problems, a plurality of signal sources and a specific value detecting means for outputting a maximum value signal or a minimum value signal of the plurality of signal sources are provided. The specific value detecting means has a function of sequentially outputting individual signals from each of the plurality of signal sources, and further includes a driving means for switching a function of the specific value detecting means. A signal processing device is provided.
【００１０】また、請求項２にように請求項１におい
て、前記駆動手段は前記特定値検出手段から信号を出力
させる駆動タイミングを異ならせることにより前記特定
値検出手段の機能を切り替えることを特徴とする信号処
理装置を提供する。According to a second aspect of the present invention, in the first aspect, the driving means switches a function of the specific value detecting means by changing a driving timing for outputting a signal from the specific value detecting means. A signal processing device is provided.
【００１１】請求項３のように請求項１又は請求項２の
いずれか１項において、前記特定値検出手段は前記複数
の信号源のそれぞれに接続された複数の電圧フォロワ回
路を含み、前記駆動手段は、前記複数の電圧フォロワ回
路の出力部を出力線に共通接続することにより、最大値
信号又は最小値信号を前記出力線に出力し、前記複数の
電圧フォロワ回路の出力部を順次前記出力線に接続する
ことにより、前記出力線に順次個別信号を出力するよう
に切り替えることを特徴とする信号処理装置を提供す
る。According to a third aspect of the present invention, in the first or second aspect, the specific value detecting means includes a plurality of voltage follower circuits connected to the plurality of signal sources, respectively. The means outputs a maximum value signal or a minimum value signal to the output line by commonly connecting output units of the plurality of voltage follower circuits to an output line, and sequentially outputs the output units of the plurality of voltage follower circuits to the output line. A signal processing device is provided, which is connected to a line to switch so as to sequentially output an individual signal to the output line.
【００１２】請求項４のように請求項３において、前記
複数の電圧フォロワ回路の出力部を前記出力線にそれぞ
れ接続する複数のスイッチ手段を含み、前記スイッチ手
段は前記駆動手段によって制御される信号処理装置を提
供する。According to a fourth aspect of the present invention, in the third aspect, the apparatus further comprises a plurality of switch means for connecting the output portions of the plurality of voltage follower circuits to the output lines, respectively, wherein the switch means is a signal controlled by the drive means. A processing device is provided.
【００１３】請求項５のように請求項４において、前記
駆動手段は、それぞれの前記スイッチ手段に同時にパル
スを供給するパルス供給手段と、それぞれの前記スイッ
チ手段に順次パルスを供給する走査回路を含むことを特
徴とする信号処理装置を提供する信号処理装置を提供す
る。According to a fifth aspect of the present invention, in the fourth aspect, the driving means includes a pulse supply means for simultaneously supplying a pulse to each of the switch means, and a scanning circuit for sequentially supplying a pulse to each of the switch means. A signal processing device for providing a signal processing device characterized by the above-mentioned features.
【００１４】請求項６のように請求項３乃至５のいずれ
か１項において、前記電圧フォロワ回路の出力部はソー
スフォロワ回路で構成されていることを特徴とする信号
処理装置を提供する。According to a sixth aspect of the present invention, there is provided a signal processing device according to any one of the third to fifth aspects, wherein the output section of the voltage follower circuit is constituted by a source follower circuit.
【００１５】請求項７のように請求項６において、前記
最大値出力手段に含まれるソースフォロワ回路は、ｎ型
のＭＯＳトランジスタで構成され、前記最小値出力手段
に含まれるソースフォロワ回路は、ｐ型のＭＯＳトラン
ジスタで構成されていることを特徴とする信号処理装置
を提供する。According to a seventh aspect of the present invention, in the sixth aspect, the source follower circuit included in the maximum value output means is constituted by an n-type MOS transistor, and the source follower circuit included in the minimum value output means is p-type. And a signal processing device comprising a MOS transistor of a type.
【００１６】請求項８のように請求項６又は請求項７の
いずれか１項において、前記出力線には定電流源が設け
られており、前記最大値信号出力時又は前記最小値信号
出力時には、それぞれ前記ソースフォロワ回路の定電流
源をオフさせ、前記出力線に設けられた定電流源をオン
させ、前記個別信号出力時には、それぞれ前記ソースフ
ォロワ回路の定電流源をオンさせ、前記出力線に設けら
れた定電流源をオフさせることを特徴とする信号処理装
置を提供する。According to an eighth aspect of the present invention, in any one of the sixth and seventh aspects, the output line is provided with a constant current source, and outputs the maximum value signal or the minimum value signal. Turning off the constant current source of the source follower circuit, turning on the constant current source provided on the output line, and turning on the constant current source of the source follower circuit at the time of outputting the individual signal, respectively. A signal processing device for turning off a constant current source provided in the signal processing device.
【００１７】請求項９のように請求項１乃至請求項８の
いずれか１項において、前記特定値出力手段の前段に前
記信号源のノイズを除去するノイズ除去手段を有するこ
とを特徴とする信号処理装置を提供する。According to a ninth aspect of the present invention, there is provided the signal according to any one of the first to eighth aspects, further comprising a noise removing unit for removing noise of the signal source at a stage preceding the specific value output unit. A processing device is provided.
【００１８】請求項１０のように請求項９において、前
記ノイズ除去手段はクランプ回路であることを特徴とす
る信号処理装置を提供する。According to a ninth aspect of the present invention, there is provided a signal processing apparatus according to the ninth aspect, wherein the noise removing means is a clamp circuit.
【００１９】請求項１１のように請求項３乃至７のいず
れか１項において、前記電圧フォロワ回路の前段にノイ
ズ除去手段を有し、前記ノイズ除去手段は前記信号源の
ノイズ成分レベル及び前記電圧フォロワ回路のオフセッ
トレベルを除去する信号処理装置を提供する信号処理装
置を提供する。According to a twelfth aspect of the present invention, in any one of the third to seventh aspects, a noise elimination means is provided before the voltage follower circuit, and the noise elimination means includes a noise component level of the signal source and the voltage. A signal processing device for providing a signal processing device for removing an offset level of a follower circuit is provided.
【００２０】請求項１２のように請求項１乃至請求項１
１のいずれか１項において、前記信号源は光電変換画素
である信号処理装置を提供する。[0020] Claims 1 to 1 as in claim 12
1. The signal processing device according to claim 1, wherein the signal source is a photoelectric conversion pixel.
【００２１】請求項１３のように複数の信号源と、前記
複数の信号源の最大値信号を出力するための最大値検出
手段と、前記複数の信号源の最小値信号を出力するため
の最小値検出手段とを有し、前記最大値出力手段又は前
記最小値出力手段は、前記複数の信号源のそれぞれから
の個別信号を順次出力する機能を兼ね備え、さらに、個
別信号を順次出力する機能を兼ね備えている前記最大値
検出手段又は前記最小値検出手段の機能を切り替える駆
動手段を有することを特徴とする信号処理装置信号処理
装置を提供する。A plurality of signal sources, a maximum value detecting means for outputting maximum value signals of the plurality of signal sources, and a minimum value for outputting minimum value signals of the plurality of signal sources. Value detection means, the maximum value output means or the minimum value output means has a function of sequentially outputting individual signals from each of the plurality of signal sources, and further has a function of sequentially outputting individual signals. A signal processing device comprising a driving unit for switching the function of the maximum value detection unit or the minimum value detection unit, which is also provided.
【００２２】請求項１４のように請求項１３において、
前記信号源は光電変換画素である信号処理装置を提供す
る。According to a thirteenth aspect, as in the fourteenth aspect,
The signal source provides a signal processing device that is a photoelectric conversion pixel.
【００２３】請求項１５のように請求項１４記載の信号
処理装置と、前記信号処理装置から出力された前記最大
値信号と前記最小値信号の差分値が所定値以上になるこ
とを検知する比較手段と、前記比較手段の出力に基づい
て前記信号処理装置内の光電変換画素の光の蓄積時間を
制御する制御手段とを有する撮像装置信号処理装置を提
供する。According to a fifteenth aspect, a comparison is made between the signal processing apparatus according to the fourteenth aspect and the signal processing apparatus for detecting that a difference value between the maximum value signal and the minimum value signal output from the signal processing apparatus is greater than or equal to a predetermined value. An image pickup apparatus signal processing apparatus comprising: means for controlling an accumulation time of light of photoelectric conversion pixels in the signal processing apparatus based on an output of the comparison means.
【００２４】[0024]
【発明の実施の形態】（第１の実施形態）図１は本発明
の特徴を最もよく表す図面であり、同図において、１は
光電変換を行うｐｎフォトダイオード、２はフォトダイ
オードの電位をＶRES にリセットするリセット用ＭＯ
Ｓ、３は差動増幅器であり、１〜３によって１つの光電
変換画素２１を構成する。４はクランプ容量、５はクラ
ンプ電位を入力するためのクランプＭＯＳで、４と５で
クランプ回路を構成している。６〜９はスイッチ用ＭＯ
Ｓ、１０は最大値検出用差動増幅器、１１は最小値検出
用差動増幅器であり、それぞれの差動増幅器は電圧フォ
ロワ回路を構成している。１２は最大値出力用スイッチ
ＭＯＳ、１３は最小値出力用スイッチＭＯＳ、１４はＯ
Ｒ回路、１５は走査回路、１６、１７は定電流用ＭＯＳ
トランジスタである。又、図２に差動増幅器１０、１１
の具体的な回路構成図を示す。最大値検出回路用には最
終段がｎＭＯＳのソースフォロワ回路、最小値検出回路
用には最終段がｐＭＯＳのソースフォロワ回路となって
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a drawing that best illustrates the features of the present invention. In FIG. 1, reference numeral 1 denotes a pn photodiode for performing photoelectric conversion, and 2 denotes a potential of the photodiode. MO for reset to reset to V RES
S and 3 are differential amplifiers, each of which constitutes one photoelectric conversion pixel 21. Reference numeral 4 denotes a clamp capacitor, and reference numeral 5 denotes a clamp MOS for inputting a clamp potential, and 4 and 5 constitute a clamp circuit. 6 to 9 are MOs for switches
S and 10 are differential amplifiers for detecting a maximum value, and 11 is a differential amplifier for detecting a minimum value. Each differential amplifier constitutes a voltage follower circuit. 12 is a maximum value output switch MOS, 13 is a minimum value output switch MOS, 14 is O
R circuit, 15 is a scanning circuit, 16 and 17 are constant current MOSs
It is a transistor. FIG. 2 shows differential amplifiers 10 and 11.
2 shows a specific circuit configuration diagram. The last stage is an nMOS source follower circuit for the maximum value detection circuit, and the last stage is a pMOS source follower circuit for the minimum value detection circuit.
【００２５】２０は画素からの信号が出力される共通出
力線である。Reference numeral 20 denotes a common output line to which a signal from a pixel is output.
【００２６】次に図３、図４のタイミングチャートを用
いて、本実施例の動作について説明する。動作状態とし
ては、リセット期間（ノイズ除去期間）、蓄積期間（Ａ
ＧＣ期間）、映像信号出力期間の３つに分けられる。先
ず、リセット期間について説明する。時刻Ｔ0 におい
て、φＲＥＳをＨｉｇｈにすることにより、ｐｎフォト
ダイオード１の電位をリセットする。時刻Ｔ1 におい
て、フォトダイオードのリセットを終了し、ノイズ除去
動作に入る時刻Ｔ2 において、φＴＮ１、φＴＮ２をＨ
ｉｇｈにすることにより、スイッチＭＯＳ６、スイッチ
ＭＯＳ７がＯＮになり光電変換用差動増幅器３の出力
は、スイッチＭＯＳトランジスタ６、最大値検出回路、
スイッチＭＯＳ７を通って、クランプ回路用容量４へ入
力される。Next, the operation of this embodiment will be described with reference to the timing charts of FIGS. The operation state includes a reset period (noise removal period), an accumulation period (A
GC period) and a video signal output period. First, the reset period will be described. At time T 0 , the potential of the pn photodiode 1 is reset by setting φRES to High. At time T 1 , the reset of the photodiode is completed, and at time T 2 at which the noise removal operation is started, φTN 1 and φTN 2 are set to H level.
The switch MOS6 and the switch MOS7 are turned on by setting the signal to high, and the output of the photoelectric conversion differential amplifier 3 is switched to the switch MOS transistor 6, the maximum value detection circuit,
The signal is input to the clamp circuit capacitor 4 through the switch MOS7.
【００２７】次の時刻Ｔ3 、Ｔ4 において、φＴＮ１、
φＴＮ２をＬＯＷにすることによりスイッチＭＯＳ７、
スイッチＭＯＳ６をＯＦＦさせ、時刻Ｔ5 、Ｔ6 でφＴ
Ｓ２をＨｉｇｈにすることによりスイッチＭＯＳ９をＯ
Ｎ、φＧＲをＨｉｇｈにすることによりクランプ用ＭＯ
Ｓ５をＯＦＦさせる。At the next times T 3 and T 4 , φTN1,
By setting φTN2 to LOW, the switch MOS7,
The switch MOS6 is OFF, φT at the time T 5, T 6
By setting S2 to High, the switch MOS9 is set to O.
By setting N and φGR to High, MO for clamping
S5 is turned off.
【００２８】この時、クランプ容量４には画素内のノイ
ズ成分と差動増幅器１０、１１のオフセット成分が加算
された電圧が保持される。以上の過程で、光電変換部と
最大値検出部と最小値検出部のノイズ（オフセット）を
クランプ除去をするためのリセット期間が終了する。At this time, the clamp capacitor 4 holds a voltage obtained by adding the noise component in the pixel and the offset components of the differential amplifiers 10 and 11. In the above process, the reset period for clamping and removing noise (offset) of the photoelectric conversion unit, the maximum value detection unit, and the minimum value detection unit ends.
【００２９】時刻Ｔ7 から蓄積期間（ＡＧＣ期間）に入
る時刻Ｔ7 において、φＰＥＡＫ、φＢＴＭをＨｉｇｈ
にすることにより、スイッチＭＯＳ１２、１３をＯＮに
して、最大値、最小値を出力したい画素に接続されてい
る差動増幅器１０、１２の出力を共通出力線２０に接続
し、定電流回路１６、１７をアクティブにする。At time T 7 when the accumulation period (AGC period) starts from time T 7 , φPEAK and φBTM are set to High.
By turning on the switch MOSs 12 and 13, the outputs of the differential amplifiers 10 and 12 connected to the pixels whose maximum and minimum values are to be output are connected to the common output line 20, and the constant current circuit 16 and Activate 17
【００３０】このように、電圧フォロワ回路を構成して
いる差動増幅器１０、１１をφＰＥＡＫ、φＢＴＭをＯ
Ｎにすることによりそれぞれ出力線２０、２０′に共通
接続することで、複数の画素の内で最大値を出力する画
素からの出力電圧が共通出力線２０に、最小値を出力す
る画素の出力電圧が共通出力線２０′に出力される。As described above, the differential amplifiers 10 and 11 constituting the voltage follower circuit are φPEAK and φBTM are O
By setting N to the common connection to the output lines 20 and 20 ′, the output voltage from the pixel that outputs the maximum value among the plurality of pixels is output to the common output line 20 and the output voltage of the pixel that outputs the minimum value. The voltage is output to the common output line 20 '.
【００３１】ここで、クランプ容量４に保持されている
電圧は以下のように示される。 ＶCP＝Ｖdavk＋ＶFPN ＋ＶRN＋Ｖoff （１） （Ｖdavk＝画素暗時電圧、ＶFPN ＝固定パターンノイズ
電圧、ＶRN＝ランダムノイズ電圧、Ｖoff ＝電圧フォロ
ワ回路オフセット電圧）Here, the voltage held in the clamp capacitor 4 is shown as follows. V CP = V davk + V FPN + V RN + V off (1) (V davk = pixel dark voltage, V FPN = fixed pattern noise voltage, V RN = random noise voltage, V off = voltage follower circuit offset voltage)
【００３２】この時の画素からの最大値又は最小値の出
力は、 ＶPB＋Ｖdavk＋ＶFVN ＋ＶRN（２） となる。ここでＶPBは最大値又は最小値電圧である。こ
の電圧がスイッチＭＯＳ８を介してクランプ回路へ入力
される。この時、先に蓄積されている電圧（１）との差
分により、差動増幅器１０、１１からの出力は、 ＶOUT ＝（２）−（１）＋Ｖoff ＝ＶPB となる。つまり、増幅増幅器からは光電変換画素のノイ
ズのみならず、差動増幅器のノイズ（オフセット成分）
も除去された信号を得ることができる。The output of the maximum value or the minimum value of the pixel at this time, the V PB + V davk + V FVN + V RN (2). Here, VPB is the maximum or minimum voltage. This voltage is input to the clamp circuit via the switch MOS8. At this time, the difference between the voltage stored in the above (1), the output from the differential amplifier 10 and 11, V OUT = (2) - a (1) + V off = V PB. That is, not only the noise of the photoelectric conversion pixel from the amplification amplifier but also the noise (offset component) of the differential amplifier
Can also be obtained.
【００３３】この時、差像増幅器１０、１１それぞれの
出力段の定電流ＭＯＳトランジスタ１８、１９はＶＣ２
をＬＯＷ、ＶＲＥＦ２をＨｉｇｈにすることにより、Ｏ
ＦＦさせておく。蓄積期間が経ち、最大値−最小値があ
る値に達した時、ＡＧＣ動作が終了し、蓄積動作が終了
する。At this time, the constant current MOS transistors 18 and 19 at the output stages of the differential image amplifiers 10 and 11 are connected to VC2
By setting REF to LOW and VREF2 to High,
Let it be FF. When the maximum value-minimum value reaches a certain value after the accumulation period, the AGC operation ends and the accumulation operation ends.
【００３４】時刻Ｔ9 から映像信号読み出し期間に入
る、時刻Ｔ9 において、ＶREF2を設定電位（所望の電流
となる電位）にすることにより、差像増幅器１１の定電
流ＭＯＳ１８をアクティブ状態にして、動作させる。時
刻Ｔ10において、走査回路１５を走査させ、φＨ１、φ
Ｈ２、φＨ３を順次出力させ、映像信号をシリアルに出
力させる。The fall from time T 9 to the video signal read period, at time T 9, by setting the V REF2 potential (potential as a desired current), and a constant current MOS18 the difference image amplifier 11 to the active state , Work. At time T 10, to scan the scanning circuit 15, φH1, φ
H2 and φH3 are sequentially output, and the video signal is output serially.
【００３５】以上の動作タイミングにより、最小値検出
回路に映像信号出力機能を兼ねさせることが可能とな
る。With the above operation timing, it is possible to cause the minimum value detection circuit to also have the video signal output function.
【００３６】本実施例において、最終出力段がソースフ
ォロワ形式である電圧フォロワ回路を各画素毎に構成
し、最小値出力時には各電圧フォロワの出力段の定電流
源をオフにして、定電流源に接続された出力線に共通接
続することにより、映像信号の最小値を得ることができ
る。また、映像信号出力時には、各電圧フォロワの出力
段の定電流源をオンにして、各電圧フォロワ回路を順
次、出力線に接続させることにより、シリアルな映像信
号を得ることができる。In this embodiment, a voltage follower circuit in which the final output stage is a source follower type is formed for each pixel, and when the minimum value is output, the constant current source of the output stage of each voltage follower is turned off and the constant current source is turned off. , The minimum value of the video signal can be obtained. In addition, when outputting a video signal, a serial video signal can be obtained by turning on the constant current source at the output stage of each voltage follower and sequentially connecting each voltage follower circuit to an output line.
【００３７】本実施例において、回路数を激減させるこ
とにより、従来よりもチップ面積を小さくすることが可
能となった。また、オフセット除去動作や、最小値出力
回路と映像信号出力回路が同一になったため、出力オフ
セットの低減も可能となった。In this embodiment, the chip area can be made smaller than that of the conventional one by drastically reducing the number of circuits. Further, since the offset removing operation and the minimum value output circuit and the video signal output circuit are the same, the output offset can be reduced.
【００３８】本実施例において、差像増幅器１０、１１
の各電圧フォロワの最終出力段はＭＯＳトランジスタに
よるソースフォロワ回路としたが、従来と同様のバイポ
ーラトランジスタによるエミッタフォロワ回路としても
同様の効果を得ることができる。In this embodiment, the difference image amplifiers 10, 11
Although the final output stage of each voltage follower is a source follower circuit using a MOS transistor, a similar effect can be obtained by using an emitter follower circuit using a bipolar transistor as in the related art.
【００３９】（第２の実施形態）図５に本発明の第２実
施例の回路構成図を示す。(Second Embodiment) FIG. 5 is a circuit diagram of a second embodiment of the present invention.
【００４０】第１実施例では、最小値検出回路に映像信
号出力機能を兼ねさせていたが、本実施例では最大値検
出回路に映像信号出力機能を兼ねさせたことを特徴とす
る。In the first embodiment, the minimum value detection circuit also has the function of outputting a video signal. However, the present embodiment is characterized in that the maximum value detection circuit also has the function of outputting a video signal.
【００４１】本実施例においても、第１実施例と同様
な、チップ面積の低減、出力オフセットの低減といった
効果を得ることが可能となった。Also in this embodiment, it is possible to obtain the same effects as in the first embodiment, such as a reduction in chip area and a reduction in output offset.
【００４２】（第３の実施形態）図６に本発明の第３実
施例の回路構成図を示す。(Third Embodiment) FIG. 6 is a circuit diagram of a third embodiment of the present invention.
【００４３】本実施例では、最大値検出回路と最小値検
出回路の入力の前にあるノイズクランプ回路がないこと
を特徴とする。当然、ノイズとなる出力オフセットは大
きくなるが、チップ面積が大幅に減らすことが可能とな
るため、性能よりもコスト優先となる光電変換装置に有
効となる。This embodiment is characterized in that there is no noise clamp circuit before the inputs of the maximum value detection circuit and the minimum value detection circuit. Naturally, the output offset that causes noise increases, but the chip area can be significantly reduced, which is effective for a photoelectric conversion device that gives priority to cost over performance.
【００４４】（第４の実施形態）図７に本発明の第４実
施例の回路構成図を示す。(Fourth Embodiment) FIG. 7 shows a circuit diagram of a fourth embodiment of the present invention.
【００４５】本実施例では、最大値出力と映像信号出力
のみを出力させる光電変換装置である安価なシステムの
場合、最小値を用いず、信号処理を行う場合がある。そ
の場合は、本実施例の様に、最大値検出回路に映像信号
出力機能を兼ねさせる事により、更なる回路削減、チッ
プ面積低減が可能となる。又、第３実施例の様にクラン
プ回路を削除しても良い。In this embodiment, in the case of an inexpensive system that is a photoelectric conversion device that outputs only the maximum value output and the video signal output, signal processing may be performed without using the minimum value. In this case, as in the present embodiment, by making the maximum value detection circuit also function as a video signal output function, it is possible to further reduce the circuit and the chip area. Further, the clamp circuit may be omitted as in the third embodiment.
【００４６】本実施例において、更に低コストの光電変
換装置が可能となる。In this embodiment, a further low-cost photoelectric conversion device can be realized.
【００４７】（第５の実施形態）図８は、本発明の第５
実施形態をあらわす回路図である。本実施形態では光電
変換画素を２次元に配列したものであり、１列ごとに最
大値検出回路と最小値検出回路が設けられている。(Fifth Embodiment) FIG. 8 shows a fifth embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an embodiment. In this embodiment, photoelectric conversion pixels are two-dimensionally arranged, and a maximum value detection circuit and a minimum value detection circuit are provided for each column.
【００４８】２０は１光電変換画素の示すものであり、
１は、光電変換を行うｐｎフォトダイオード、３０はｐ
ｎフォトダイオードの信号電荷を転送するための転送Ｍ
ＯＳ、３２は転送された信号を増幅して出力する増幅Ｍ
ＯＳ、３１は転送された信号を所定のリセット電位にリ
セットするためのリセットＭＯＳ、３３は画素を選択す
るための選択ＭＯＳである。３７は定電流源であり、増
幅ＭＯＳとソースフォロワを構成する。３５は垂直出力
線、３６は１行ずつ順次画素を選択するための垂直走査
回路、３８は水平出力線、３９は信号を順次水平出力線
に転送する水平走査回路である。又、図１と同じ構成部
材については同じ番号を付けてある。Reference numeral 20 denotes one photoelectric conversion pixel.
1 is a pn photodiode for performing photoelectric conversion, 30 is p
transfer M for transferring the signal charge of the n photodiode
The OS 32 amplifies the transferred signal and outputs the amplified signal.
OS and 31 are reset MOSs for resetting the transferred signal to a predetermined reset potential, and 33 is a selection MOS for selecting a pixel. Reference numeral 37 denotes a constant current source, which forms an amplifying MOS and a source follower. Reference numeral 35 denotes a vertical output line, 36 denotes a vertical scanning circuit for sequentially selecting pixels line by line, 38 denotes a horizontal output line, and 39 denotes a horizontal scanning circuit for sequentially transferring signals to the horizontal output line. The same components as those in FIG. 1 are given the same numbers.
【００４９】本実施例においては、垂直走査回路３６に
よって、１行ずつ画素を選択して、実施形態１と同様の
動作を行うことにより、１行中の最大値出力、最小値出
力、映像出力が得られる。In this embodiment, the vertical scanning circuit 36 selects pixels one row at a time, and performs the same operation as in the first embodiment to output the maximum value, the minimum value, and the video output in one row. Is obtained.
【００５０】以上実施形態１〜５で説明した光電変換画
素は、実施形態１〜５で説明したものに限るものではな
い。例えば、実施形態５で説明した光電変換画素を実施
形態１に用いてもよい。この場合、実施形態１はライン
センサーなので選択ＭＯＳ３３を除くことができる。
又、ＭＯＳ型の他の回路構成でもよいし、ＭＯＳ型に限
らず、ＢＡＳＩＳ、ＳＩＴ等の画素構成であってもよ
い。さらに又、光を電気信号に変換する光電変換画素で
はなく、電圧信号等を発生する信号源であればよい。The photoelectric conversion pixels described in the first to fifth embodiments are not limited to those described in the first to fifth embodiments. For example, the photoelectric conversion pixel described in the fifth embodiment may be used in the first embodiment. In this case, since the first embodiment is a line sensor, the selection MOS 33 can be omitted.
Further, another circuit configuration of the MOS type may be used, and the pixel configuration is not limited to the MOS type, and may be a pixel configuration such as BASIS or SIT. Furthermore, a signal source that generates a voltage signal or the like may be used instead of a photoelectric conversion pixel that converts light into an electric signal.
【００５１】（第６の実施形態）図９、実施形態１〜５
で説明した光電変換装置を用いた具体的な撮像装置のブ
ロック図である。(Sixth Embodiment) FIG. 9, Embodiments 1 to 5
FIG. 3 is a block diagram of a specific imaging device using the photoelectric conversion device described in FIG.
【００５２】図３において、１０１は実施形態１〜５で
説明した光電変換装置、１０２はＰＥＡＫ出力ＶPEAKと
ＢＴＭ出力ＶBTM との差分をとるための差動増幅器、１
０３は差動増幅器１０２の出力と所定の基準レベルＶ
ref とを比較し、適正な蓄積レベルに達したことを判定
するコンパレータ、１０９と１１１はＶｉｄｅｏライン
より出力される最小値と最大値の信号をそれぞれ記憶す
る記憶回路、１１０は記録回路１０９の出力と映像出力
Ｖｉｄｅｏの出力の差をとる差動増幅器、１１２は記録
回路１１１と記録回路１０９との出力の差をとる差動増
幅器、１０４はマイクロコンピュータである。マイクロ
コンピュータは、ＣＰＵコア１０４ａ、ＲＯＭ１０４
ｂ、ＲＡＭ１０４ｃ、Ａ／Ｄ変換器１０４ｄから構成さ
れる。In FIG. 3, reference numeral 101 denotes a photoelectric conversion device described in the first to fifth embodiments; 102, a differential amplifier for obtaining a difference between a PEAK output V PEAK and a BTM output V BTM ;
03 is the output of the differential amplifier 102 and a predetermined reference level V
ref and a comparator for judging that an appropriate accumulation level has been reached. 109 and 111 are storage circuits for respectively storing the minimum value and maximum value signals output from the Video line. 110 is an output of the recording circuit 109. , A differential amplifier for obtaining the difference between the outputs of the recording circuit 111 and the recording circuit 109, and 104 a microcomputer. The microcomputer includes a CPU core 104a, a ROM 104
b, RAM 104c, and A / D converter 104d.
【００５３】図３に示した撮像装置においては、まず、
マイクロコンピュータ１０４がリセット信号φres ，φ
vrs を出力し蓄積を開始する。次にコンパレータ１０３
の反転信号φcompをうけφt が出力され蓄積を中止す
る。さらにφhrs 及びφckが出力され読み出しが行われ
る。このとき最小値の出力のタイミングで記憶回路１０
９にマイクロコンピュータ１０４からサンプリング信号
ＳＨが送られ最小値が記憶される。引き続き出力される
光電変換素子アレイの出力は差動増幅器１１０により最
小値との差をとった形でＡ／Ｄ変換される。このときＡ
／Ｄ変換の参照電位Ｖrlは接地電位、ＶrhはＶref と設
定されているのでＡ／Ｄ変換は光電変換画素の出力のほ
ぼ最大値と最小値の間で行われるが、このとき光電変換
装置の出力の基準となる最小値が正確に読み出されてい
るため、Ａ／Ｄ変換が正確に被写体のコントラスト部分
について行われる。In the imaging device shown in FIG. 3, first,
The microcomputer 104 generates reset signals φ res , φ
Outputs vrs and starts accumulation. Next, the comparator 103
Tt is output in response to the inverted signal のcomp of , and the accumulation is stopped. Further, φ hrs and φ ck are output and read is performed. At this time, the storage circuit 10 outputs the minimum value output timing.
The sampling signal SH is sent from the microcomputer 104 to 9 and the minimum value is stored. The output of the photoelectric conversion element array that is subsequently output is A / D-converted by the differential amplifier 110 in the form of a difference from the minimum value. Then A
Since the reference potential Vrl of the / D conversion is set to the ground potential and Vrh is set to Vref , the A / D conversion is performed between the maximum value and the minimum value of the output of the photoelectric conversion pixel. Since the minimum value serving as the reference of the output of the conversion device has been accurately read, A / D conversion is accurately performed on the contrast portion of the subject.
【００５４】[0054]
【発明の効果】以上説明したように、本発明によれば、
複数の信号源の少なくとも最大値信号又は最小値信号及
びそれぞれの信号源からの個別信号とを出力する装置に
以下のような効果を持たせることができる。 ・小サイズ化が可能となる ・低コスト化が可能となる ・低雑音化が可能となるAs described above, according to the present invention,
A device that outputs at least the maximum value signal or the minimum value signal of a plurality of signal sources and the individual signals from each signal source can have the following effects.・ Small size possible ・ Low cost ・ Low noise
【図１】本発明の第１の実施形態に係わる回路構成図で
ある。FIG. 1 is a circuit configuration diagram according to a first embodiment of the present invention.
【図２】本発明の第１の実施形態に係わる回路構成図で
ある。FIG. 2 is a circuit configuration diagram according to the first embodiment of the present invention.
【図３】本発明の第１の実施形態に係わるるタイミング
チャート図である。FIG. 3 is a timing chart according to the first embodiment of the present invention.
【図４】本発明の第１の実施形態に係わるタイミングチ
ャート図である。FIG. 4 is a timing chart according to the first embodiment of the present invention.
【図５】本発明の第２の実施形態に係わる回路構成図で
ある。FIG. 5 is a circuit configuration diagram according to a second embodiment of the present invention.
【図６】本発明の第３の実施形態に係わる回路構成図で
ある。FIG. 6 is a circuit configuration diagram according to a third embodiment of the present invention.
【図７】本発明の第４の実施形態に係わる回路構成図で
ある。FIG. 7 is a circuit configuration diagram according to a fourth embodiment of the present invention.
【図８】本発明の第５の実施形態に係わる回路構成図で
ある。FIG. 8 is a circuit configuration diagram according to a fifth embodiment of the present invention.
【図９】本発明の第６の実施形態に係わる回路構成図で
ある。FIG. 9 is a circuit configuration diagram according to a sixth embodiment of the present invention.
【図１０】従来例の回路構成図である。FIG. 10 is a circuit configuration diagram of a conventional example.
【図１１】従来例の回路構成図である。FIG. 11 is a circuit configuration diagram of a conventional example.
【図１２】従来例の回路構成図である。FIG. 12 is a circuit configuration diagram of a conventional example.
１ ｐｎフォトダイオード ２ リセット、ＭＯＳトランジスタ ３ 差動増幅器 ４ クランプ容量 ５ クランプＭＯＳトランジスタ ６〜９ スイッチＭＯＳトランジスタ １０ 最大値検出用差動増幅器 １１ 最小値検出用差動増幅器 １２ 最大値出力線接続トランジスタ １３ 最小値出力線接続トランジスタ １４ ＯＲ回路 １５ 走査回路 １６ 最大値検出用定電流ＭＯＳトランジスタ １７ 最小値検出用定電流ＭＯＳトランジスタ １８ ｎＭＯＳ定電流源 １９ ｐＭＯＳ定電流源 １５ ソースフォロワアンプＭＯＳトランジスタ ２６ ソースフォロワ定電流源 ５１ ｎｐｎフォトトランジスタ ５２ リセットＭＯＳトランジスタ ５３ 接地ＭＯＳトランジスタ ５４ 最大値検出用差動増幅器 ５５ 最小値検出用差動増幅器 ５６、５７ 定電流源 ５８、５９ ＭＯＳ容量 ６０〜６３ スイッチＭＯＳトランジスタ ６４ 走査回路 ６５、６６ 電圧フォロワ回路 ６７ 差動増幅器 １０１ 光電変換装置 １０２、１１０ 差動増幅器 １０３ コンパレータ １０４ マイクロコンピュータ Reference Signs List 1 pn photodiode 2 reset, MOS transistor 3 differential amplifier 4 clamp capacitance 5 clamp MOS transistor 6-9 switch MOS transistor 10 maximum value detection differential amplifier 11 minimum value detection differential amplifier 12 maximum value output line connection transistor 13 Minimum value output line connection transistor 14 OR circuit 15 Scanning circuit 16 Maximum value detection constant current MOS transistor 17 Minimum value detection constant current MOS transistor 18 nMOS constant current source 19 pMOS constant current source 15 Source follower amplifier MOS transistor 26 Source follower constant Current source 51 npn phototransistor 52 Reset MOS transistor 53 Ground MOS transistor 54 Maximum value detection differential amplifier 55 Minimum value detection differential amplifier 56, 57 Constant current source 58, 59 MO S capacitance 60 to 63 Switch MOS transistor 64 Scan circuit 65, 66 Voltage follower circuit 67 Differential amplifier 101 Photoelectric conversion device 102, 110 Differential amplifier 103 Comparator 104 Microcomputer
Claims (15)
る特定値検出手段とを有し、 前記特定値検出手段は、前記複数の信号源のそれぞれか
らの個別信号を順次出力する機能を兼ね備え、 さらに、前記特定値検出手段の機能を切り替える駆動手
段を有することを特徴とする信号処理装置。1. A plurality of signal sources, and a specific value detection unit that outputs a maximum value signal or a minimum value signal of the plurality of signal sources, wherein the specific value detection unit includes a plurality of signal sources. A signal processing device having a function of sequentially outputting individual signals from the control unit, and further comprising a driving unit for switching a function of the specific value detecting unit.
特定値検出手段から信号を出力させる駆動タイミングを
異ならせることにより前記特定値検出手段の機能を切り
替えることを特徴とする。2. The method according to claim 1, wherein the driving unit switches the function of the specific value detecting unit by changing a driving timing for outputting a signal from the specific value detecting unit.
おいて、前記特定値検出手段は前記複数の信号源のそれ
ぞれに接続された複数の電圧フォロワ回路を含み、 前記駆動手段は、前記複数の電圧フォロワ回路の出力部
を出力線に共通接続することにより、最大値信号又は最
小値信号を前記出力線に出力し、前記複数の電圧フォロ
ワ回路の出力部を順次前記出力線に接続することによ
り、前記出力線に順次個別信号を出力するように切り替
えることを特徴とする。3. The device according to claim 1, wherein the specific value detection unit includes a plurality of voltage follower circuits connected to the plurality of signal sources, respectively, and the driving unit includes By commonly connecting the output units of the plurality of voltage follower circuits to the output line, a maximum value signal or a minimum value signal is output to the output line, and the output units of the plurality of voltage follower circuits are sequentially connected to the output line. Thereby, switching is performed so that individual signals are sequentially output to the output line.
ロワ回路の出力部を前記出力線にそれぞれ接続する複数
のスイッチ手段を含み、前記スイッチ手段は前記駆動手
段によって制御される。4. The apparatus according to claim 3, further comprising a plurality of switch means for connecting output units of said plurality of voltage follower circuits to said output lines, respectively, and said switch means is controlled by said drive means.
れぞれの前記スイッチ手段に同時にパルスを供給するパ
ルス供給手段と、それぞれの前記スイッチ手段に順次パ
ルスを供給する走査回路を含むことを特徴とする。5. The driving device according to claim 4, wherein the driving unit includes a pulse supply unit that supplies a pulse to each of the switch units simultaneously, and a scanning circuit that sequentially supplies a pulse to each of the switch units. I do.
て、前記電圧フォロワ回路の出力部はソースフォロワ回
路で構成されていることを特徴とする。6. The voltage follower circuit according to claim 3, wherein an output section of the voltage follower circuit is constituted by a source follower circuit.
に含まれるソースフォロワ回路は、ｎ型のＭＯＳトラン
ジスタで構成され、前記最小値出力手段に含まれるソー
スフォロワ回路は、ｐ型のＭＯＳトランジスタで構成さ
れていることを特徴とする。7. The source follower circuit according to claim 6, wherein said source follower circuit included in said maximum value output means comprises an n-type MOS transistor, and said source follower circuit included in said minimum value output means comprises a p-type MOS transistor. It is characterized by comprising.
おいて、前記出力線には定電流源が設けられており、前
記最大値信号出力時又は前記最小値信号出力時には、そ
れぞれ前記ソースフォロワ回路の定電流源をオフさせ、
前記出力線に設けられた定電流源をオンさせ、前記個別
信号出力時には、それぞれ前記ソースフォロワ回路の定
電流源をオンさせ、前記出力線に設けられた定電流源を
オフさせることを特徴とする。8. The output line according to claim 6, wherein a constant current source is provided on the output line, and the source is supplied when the maximum value signal is output or the minimum value signal is output. Turn off the constant current source of the follower circuit,
Turning on the constant current source provided on the output line, turning on the constant current source of the source follower circuit, and turning off the constant current source provided on the output line when the individual signal is output. I do.
おいて、前記特定値出力手段の前段に前記信号源のノイ
ズを除去するノイズ除去手段を有することを特徴とす
る。9. The method according to claim 1, further comprising a noise removing unit that removes noise of the signal source at a stage preceding the specific value output unit.
段はクランプ回路であることを特徴とする。10. The apparatus according to claim 9, wherein said noise removing means is a clamp circuit.
て、前記電圧フォロワ回路の前段にノイズ除去手段を有
し、前記ノイズ除去手段は前記信号源のノイズ成分レベ
ル及び前記電圧フォロワ回路のオフセットレベルを除去
する。11. The voltage follower circuit according to claim 3, further comprising: a noise remover provided before the voltage follower circuit, wherein the noise remover includes a noise component level of the signal source and an offset of the voltage follower circuit. Remove levels.
項において、前記信号源は光電変換画素である。12. The method according to claim 1, wherein
In the paragraph, the signal source is a photoelectric conversion pixel.
検出手段と、 前記複数の信号源の最小値信号を出力するための最小値
検出手段とを有し、 前記最大値出力手段又は前記最小値出力手段は、前記複
数の信号源のそれぞれからの個別信号を順次出力する機
能を兼ね備え、 さらに、個別信号を順次出力する機能を兼ね備えている
前記最大値検出手段又は前記最小値検出手段の機能を切
り替える駆動手段を有することを特徴とする信号処理装
置。13. A plurality of signal sources, maximum value detection means for outputting maximum value signals of the plurality of signal sources, and minimum value detection means for outputting minimum value signals of the plurality of signal sources. The maximum value output means or the minimum value output means has a function of sequentially outputting individual signals from each of the plurality of signal sources, and further has a function of sequentially outputting individual signals. A signal processing device comprising a driving unit for switching a function of a maximum value detection unit or a function of the minimum value detection unit.
電変換画素である。14. The signal source according to claim 13, wherein the signal source is a photoelectric conversion pixel.
最小値信号の差分値が所定値以上になることを検知する
比較手段と、前記比較手段の出力に基づいて前記信号処
理装置内の光電変換画素の光の蓄積時間を制御する制御
手段とを有する撮像装置。15. A signal processing device according to claim 14, wherein: a comparing means for detecting that a difference value between the maximum value signal and the minimum value signal output from the signal processing device is greater than or equal to a predetermined value; A control unit for controlling a light accumulation time of the photoelectric conversion pixel in the signal processing device based on an output of the comparison unit.
Priority Applications (5)
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| JP35762098A JP4323599B2 (en) | 1998-12-16 | 1998-12-16 | Signal processing apparatus and imaging apparatus |
| US09/359,685 US6781624B1 (en) | 1998-07-30 | 1999-07-23 | Signal processing apparatus |
| DE69943194T DE69943194D1 (en) | 1998-07-30 | 1999-07-28 | Signal processing device |
| EP20100181700 EP2290951A3 (en) | 1998-07-30 | 1999-07-28 | Signal processing apparatus |
| EP99305983A EP0977427B1 (en) | 1998-07-30 | 1999-07-28 | Signal processing apparatus |
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| JP35762098A JP4323599B2 (en) | 1998-12-16 | 1998-12-16 | Signal processing apparatus and imaging apparatus |
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| JP2008150486A Division JP4509202B2 (en) | 2008-06-09 | 2008-06-09 | Signal processing apparatus and imaging apparatus |
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