JP2000175159A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of picture quality owing to the discrimination of a picture by providing a means for switching sequential scanning conversion into interpolation or inter-field interpolation in a field in a sequential scanning conversion means based on the result of a means that discriminates the movement of a picture signal within one field. SOLUTION: A discriminating part 12 detects discriminates the pattern of a picture by using a movement detection signal delayed by one field by a field memory 11 and the output signal of a movement correction circuit 8. The movement detection signal outputted by the judgment part 12 switches interpolation by an inter-line operation in the field or interpolation by an inter-field operation within two fields in accordance with the level of the movement signal by a mixing circuit 6. Video signals interpolated in time compression circuits 7 and 9 are compressed to 1/2 of horizontal time and are alternately outputted by a selector 10. Then, the deterioration of picture quality owing to picture discrimination can be prevented by detecting movement within one field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for television signals, and more particularly to a video signal processing apparatus for converting an interlace signal into a progressive scanning signal.

[0002]

2. Description of the Related Art In recent years, in a digital television or the like which is being developed, an interlace signal such as NTSC transmitted from a receiver is once converted into a sequential scan. This is because flicker is reduced on the screen and vertical resolution is improved. In addition, the progressive scan conversion technology has become indispensable from the viewpoint of sharing with a video signal from a personal computer or the like which is sent by progressive scan in advance.

For this purpose, a signal processing circuit for converting a television signal from an interlace signal to a sequential scanning signal is required. Such a video signal processing apparatus is disclosed in Japanese Patent Publication No. 8-32025. Here, a conventional example will be described with reference to FIG.

In FIG. 3, assuming that an interlace signal has been input, 21 is a field memory for delaying a video signal by 262 lines, 22 is a field memory for delaying a video signal by 263 lines, and 23 is a line memory for delaying a video signal by one line. Memories, 24 and 25 are adders, 2
Reference numeral 8 denotes a motion detection circuit that outputs a motion determination result when a still or moving image is determined by taking a difference between the pixel and a pixel before 525 lines (one frame).
6 is a mixing circuit for selecting and mixing the signals of the adders 25 and 24 based on the result of the motion detection circuit 28;
Reference numeral 9 denotes a time compression circuit for outputting the input video signal in half the time of the input horizontal synchronizing signal, and reference numeral 30 denotes a selector for alternately selecting the outputs of the time compression circuits 27 and 29 and converting the output into a sequential scanning signal. It is. The operation of such a conventional video signal processing device will be described below.

[0005] The input interlace signal is first delayed by the field memory 21 and the field memory 22. Next, the adder 25 adds the signal and the signal delayed by 525 lines by the field memory 21 and the field memory 22 and sends the result to the mixing circuit 26. The signal delayed by 262 lines in the field memory 21 is further added to the line memory. 23, the signal is delayed by one line, and is added to the output of the field memory 21 by the adder 24.
It is sent to the mixing circuit 26. The signal and the video signal delayed by 525 lines by the field memory 21 and the field memory 22 are further input to the motion detection circuit 28. The motion detection circuit 28 calculates the difference between the two video signals, and if the video is a still image, the difference becomes 0, and if the video is a moving image, a detection signal corresponding to the moving image is output. The motion detection signal is switched by the mixing circuit 26 between interpolation by inter-line operation in a field or interpolation by inter-field operation in two fields according to the level of the motion signal. Next, the video signal interpolated in the time compression circuits 27 and 29 is compressed to a half horizontal time, and
The interlaced signal input by alternately outputting 0 is converted into a sequential scanning signal.

[0008] Referring to FIG. 4, in FIG. 3, a white circle indicates an input video signal, a white triangle indicates an interpolated signal, and an interpolation signal n 2 in a certain n-th line.
Generates a motion detection signal from n1 and n3. Based on the motion detection signal, an n2 interpolation signal is generated by a combination of l2, m2, n1, and n3. That is, l2, n
In the case of 2, interpolation is performed between fields, and in the case of n1 and n3, interpolation is performed within a field. As a result, the input interlace signal has twice the number of lines, and is sequentially converted into a scanning signal.

[0007]

However, in the conventional method, since a difference between two fields is obtained in the motion detection circuit, when a motion of one field occurs in the input signal, the motion is actually a moving picture even though it is a moving picture. Omission of detection occurs, and the image is significantly deteriorated. Figure 2
This will be described in more detail with reference to FIG.

In FIG. 2 (a), a rectangular frame represents an image of one field of the input interlace signal, and the elapse of time is shown on the near side. In this case, in the conventional example, if only the image indicated by oblique lines is an image in which the strobe of the camera flashes for a moment, if the images before and after are the same, it is determined to be a still image. For this reason, in the case of a still image, the vertical resolution of sequentially scanned video signals is improved by interpolating between fields, that is, by creating an interpolation signal based on l2 and m2. Because the signal is inserted as a signal, white horizontal stripes will be visible in the video with the camera's strobe light turned on.

[0009]

In order to solve the above problems, a video signal processing apparatus according to the present invention converts a motion detection signal result into one.
By holding between fields and determining a specific pattern, motion within one field is detected, and deterioration of image quality caused by determining that a video is a still image is prevented.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides means for sequentially scanning and converting an interlace signal, means for holding one field of a motion detection signal generated from the means for sequentially scanning and converting the interlace signal, and sequential scanning of the interlace signal. A means for holding one field of a motion detection signal generated from a means for converting the motion detection signal and a motion detection signal generated from a means for sequentially scanning-converting the interlace signal, a means for judging motion within one field of the video signal; Means for switching the progressive scan conversion to intra-field interpolation or inter-field interpolation in the progressive scan conversion means based on the result of the motion within the field. Detect changes in the video within one field,
An object of the present invention is to reduce the deterioration of a video when an erroneous determination is made for a still image.

An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, 1 is a field memory for delaying a video signal by 262 lines, 2 is a field memory for delaying a video signal by 263 lines, 3
Is a line memory that delays the video signal by one line, 4 and 5 are adders, and 8 is a motion when the video is determined to be still or moving by taking the difference between the pixel and the pixel before 525 lines (one frame). A motion detection circuit 11 for outputting a judgment result is provided.
A field memory for delaying a line or 263 lines; 12 a determination unit for detecting a specific pattern from the output from the motion detection circuit 8 and the output from the field memory 11;
Is a mixing circuit for selecting and mixing the signals of the adder 5 and the adder 4 based on the result of the judging unit 12, and 7 and 9 are time compressions for outputting the input video signal in half the time of the input horizontal synchronizing signal. The circuit 10 is a selector for alternately selecting the outputs of the time compression circuits 7 and 9 to convert the outputs into sequential scanning signals. An embodiment of a video signal processing device based on such a circuit will be described below.

The input interlace signal is first delayed by the field memory 1 and the field memory 2. Next, the adder 5 adds the signal and the signal delayed by 525 lines by the field memory 1 and the field memory 2 and sends the result to the mixing circuit 6. The signal delayed by 262 lines in the field memory 1 is further added to the line memory. The signal is delayed by one line by 3, added to the output of the field memory 1 by the adder 4, and sent to the mixing circuit 6. The signal and the video signal delayed by 525 lines are further input to the motion detection circuit 8. The motion detection circuit 8 calculates the difference between the two video signals, and if the video is a still image, the difference becomes 0, and if the video is a moving image, a motion detection signal corresponding to the moving image is output. The motion detection result from the motion detection circuit 8 is delayed by one field by the field memory 11 and input to the determination unit 12. The determination unit 12 generates a switching signal according to a specific pattern.

FIG. 2 shows this pattern determination. FIG. 2 illustrates a state in which an interlaced signal is transmitted in a square frame, and it is assumed that time has passed to the near side. Among them, the square frame is a still image, and the same image is sent. Also, consider a slanted rectangular frame moving image, particularly a momentary moving image in which a camera flash or the like is fired.
a) The case where the moving image ends in one field. b) is a case where the moving image ends in two fields.

First, in the case of an input signal as shown in a), when the motion detection circuit 8 performs motion detection based on a one-frame difference, the motion detection result is "static (1)-> dynamic (2)-> static (3 )-> Dynamic (4)->
Still (5) ". Here, the still image is determined as a still image, and the motion is determined as a moving image. Paying attention to stillness (3), since the still image determination is performed from the difference between the video signals before and after the hatched square frame, the motion detection circuit 8 alone determines that the input image is a moving image even though it is actually a moving image. Will be done. Therefore, in the mixing circuit 6, an interpolation signal is created based on the video signal of one field before to improve the vertical resolution. Therefore, a normal still image is inserted into the flash video, so that every other video is inserted. A striped image is displayed, and the quality of the image is significantly reduced.

The determination unit 12 detects a "moving->still" pattern by using the motion detection signal delayed by one field by the field memory 11 and the output signal of the motion compensating circuit 8, and determines the moving image. I do. As a result, the input signal of a) is "static (1)-> dynamic (2)-> dynamic (3)-> dynamic (4)-> static.
(5) ", and a decrease in video quality can be prevented.

In the case of an input signal as shown in b), when the motion detection circuit 8 performs motion detection based on a one-frame difference, the result of the motion detection is "static (6)-> motion (7)-> motion (8 )-> Dynamic (9)->
Motion (10) -static (11) ". In this case, paying attention to the motions (8) and (9), since the moving image is determined from the difference between the video signals before and after the hatched rectangular frame, the output result of the determination unit 12 is “static”.
(6)-> motion (7)-> motion (8)-> motion (9)-> motion (10)-motion (11) "
Becomes Although the motion (11) is an erroneous determination among the determination results, the quality of the video is not degraded even if the vertical resolution is not improved because the interpolation signal is generated in the own field.

The motion detection signal output from the decision section 12 is switched by the mixing circuit 6 between interpolation by inter-line operation in a field or interpolation by inter-field operation in two fields according to the level of the motion signal. . Next, the video signals interpolated in the time compression circuits 7 and 9 are １ ／
The interlaced signal is compressed by the horizontal time and output alternately by the switch 10 to be converted into a sequential scanning signal.

[0018]

As described above, according to the present invention, in a video signal processing apparatus for converting an interlaced signal into a progressive scanning signal, even if an erroneous discrimination of a motion detection circuit occurs due to a video moving within one field, A sequentially scanned image can be displayed without deterioration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal processing device according to a second embodiment of the present invention;

FIG. 2 is a diagram illustrating a determination method of a determination unit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional video signal processing device.

FIG. 4 is a diagram showing a conventional video signal processing device interpolation pixel;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Field memory 2 Field memory 3 Line memory 4 Adder 5 Adder 6 Mixing circuit 7 Time compression unit 8 Motion detection circuit 9 Time compression unit 10 Selector 11 Field memory 12 Judgment unit 21 Field memory 22 Field memory 23 Line memory 24 Addition Unit 25 adder 26 mixing circuit 27 time compression unit 28 motion detection circuit 29 time compression unit 30 selector

Claims (1)

[Claims] 1. A means for sequentially scanning-converting an interlace signal, a means for holding one field of a motion detection signal generated from a means for sequentially scanning-converting the interlace signal, and a means for sequentially scanning-converting the interlace signal. A means for holding a motion detection signal generated from a means for sequentially scanning-converting a motion detection signal and the interlace signal, means for holding one field, and means for judging motion within one field of the video signal, and judging motion within one field of the video signal A video signal processing apparatus comprising means for switching the progressive scan conversion in the progressive scan conversion unit to either intra-field interpolation or inter-field interpolation based on the result of the means.