JP2000175120A - Video signal switch circuit/method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an unnecessary operation and an unnecessary picture state by providing a judgment means for outputting a control signal designating the video signal of the other format which can be decoded to a switch when the inputted video signal is judged to be not decoded. SOLUTION: A CPU 4 frequency-discriminates whether a signal processing circuit 2 can execute decoding or not based on the frequency of a detected HD pulse and the upper limit value and the lower limit value of the frequency of the HD pulse, which are stored in the storage means of the CPU 4 and which a signal processing circuit 2 can decode. When the signal processing circuit 2 is judged that it cannot execute decoding as the result of frequency discrimination, the CPU 4 outputs indications so that a (b) terminal side and an (e) terminal side are connected to SW 6 and a (c) terminal side and an (f) terminal side are connected to SW 7 based on information which is stored in the storage means and which is on effect that the composite signal of an NTSC system, which is obtained by down-converting a component signal, is connected to an outer input terminal 11 stored in a storage means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for switching video signals.

[0002]

2. Description of the Related Art At present, for example, in satellite broadcasting, a program is broadcast by a video signal of a multi-video format (a plurality of video formats). 12G in Japanese satellite broadcasting
The standard television (digital subcarrier N
TSC system) Broadcasting and Hi-Vision (MUSE system)
Broadcasting is taking place.

[0003] Also, video signals from external devices such as VTRs and DVDs include signals in a plurality of video formats (systems). Therefore, the conventional video receiving apparatus may not be able to normally display a screen with the received video signal. Here, a conventional technique will be described.

FIG. 5 is a diagram showing a configuration of a conventional component signal input correspondence switching circuit. In FIG. 5, reference numeral 101 denotes an output unit. The output unit 101 displays an image, and is, for example, a CRT or an LCD. 102 is a signal processing circuit. The signal processing circuit 102 converts the input component signal (for example, composed of a Y signal, an RY signal, and a BY signal) into a signal to be displayed on the output unit 101, and outputs the signal. This is output to the unit 101.

[0005] Reference numeral 105 denotes a color demodulation circuit. Color demodulation circuit 1
Numeral 05 converts an input composite (or YC) signal into a component signal and outputs it. 13
0 is an input unit. The input unit 130 receives information from the user to switch the video signal, and is, for example, a push button switch, a mouse, or the like.

Reference numeral 131 denotes a CPU. The CPU 131
The control is performed to switch the video input from the outside to the video desired by the user based on the information indicating that the video signal input to the input unit 130 by the user is to be switched. 1
32 is a synchronization separation circuit. The synchronization separation circuit 132 separates a synchronization signal from an input component signal, and outputs the synchronization signal to the output unit 101.

137 is an external input terminal. The external input terminal 137 is a terminal to which a multi-format video signal is supplied from outside. Here, it is assumed that the external input terminal 137 is supplied with a component signal from the outside. 138 and 139 are external input terminals.
The external input terminal 138 and the external input terminal 139 are terminals to which a composite (or YC) signal which is a video signal of a predetermined format is supplied from outside.

Reference numeral 106 denotes a switch (SW). SW1
Reference numeral 06 includes an a terminal, a b terminal, and a common e terminal, and the e terminal is a SW (switch) connected to either the a terminal or the b terminal. And the CPU 131
SW 106 receives the instruction (control) from
The terminal is connected to the terminal, or the terminal e is connected to the terminal b. The external input terminal 137 is connected to the terminal a. b
A component signal output from the color demodulation circuit 105 is connected to the terminal. The e terminal is connected to the signal processing circuit 102 and the synchronization separation circuit 132.

Reference numeral 107 denotes a SW (switch). SW1
07 is a SW (switch) connected to a c terminal, a d terminal, and a common f terminal, and the f terminal is connected to either the c terminal or the d terminal. And the CPU 131
SW 107 receives the instruction (control) from
The terminal is connected to the terminal, or the terminal f is connected to the terminal d. The external input terminal 138 is connected to the terminal c. d
An external input terminal 139 is connected to the terminal. And f
The terminal is connected to the color demodulation circuit 105.

Next, the operation of a circuit for switching a component signal in the conventional video receiving apparatus will be described. For example, when displaying the component signal supplied to the external input terminal 137, the user needs to
Is transmitted to the CPU 131 via the external input terminal 137 via the. CP that received the information
U131 instructs SW106 to connect the e terminal of SW106 to the a terminal. Thereby, the signal processing circuit 10
The component signal of the external input terminal 137 is supplied to the second and the sync separation circuit 132 via the SW 106, and an image is displayed on the output unit 101.

When displaying a composite signal (for example, a signal from a VTR) supplied to the external input terminal 138, the user inputs, via the input unit 130, information indicating switching to the signal of the external input terminal 138 to the CPU 131. Send to Upon receiving the information, the CPU 131 switches SW10
7, the terminal f of the SW 107 is connected to the terminal c. Thus, the composite signal supplied to the external input terminal 138 is supplied to the color demodulation circuit 1 via the SW 107.
05 is input. Then, the CPU 131 sets the SW 106
To connect the e terminal of the SW 106 to the b terminal.
Thereby, the signal processing circuit 102 and the synchronization separation circuit 1
32, the component signal of the external input terminal 138 is supplied via the SW 106, and the output unit 101 displays an image.

[0012]

However, there are cases where the video receiving apparatus receives a television signal of a broadcast system that cannot be decoded and a signal of an external device that cannot be decoded. In this case, when a component signal that cannot be decoded by the signal processing circuit 102 and the synchronization separation circuit 132 is input, the signal processing circuit 102 and the synchronization separation circuit 13
Circuit operation is not performed normally because 2 cannot be decoded.
Display on the output unit 101 is not performed normally. Therefore, conventionally, the user has confirmed the abnormality of the screen display of the output unit 101,
It is determined that the signal cannot be decoded by the video receiver. Then, as a result of the determination, the user cannot decode with the signal, and the display cannot be normally displayed on the screen. Switching to a signal that can be displayed.

For this reason, in this prior art, since the user checks the screen state by himself and switches to a signal that can be decoded by manual operation, an unnecessary state such as video muting occurs on the screen. Accordingly, it is an object of the present invention to provide a video signal switching technique that eliminates unnecessary operations and unnecessary screen states when a broadcast-type television signal that cannot be decoded or a component signal of a signal from an external device is received.

[0014]

According to the present invention, there is provided a video signal switching circuit in a device to which video signals of different formats are inputted, wherein video signals of different formats are inputted and designated by a control signal. And a switch for outputting a video signal in a specified format, and determining whether or not the input video signal can be decoded. If it is determined that the input video signal can be decoded, a control signal for specifying the input video signal is determined. Is output to the switch,
When it is determined that the input video signal cannot be decoded as a result of the determination, a determination unit that outputs a control signal designating a video signal of another format that can be decoded to the switch is provided.

[0015] The determining means may output an HD pulse (Horizon) from the input multi-format video signal.
means for separating and outputting the zontal driving pulse) and detecting the frequency of the HD pulse by counting the output HD pulse, and determining whether or not decoding can be performed based on the frequency of the HD pulse. And means for performing the operation.

Further, the video signal switching circuit further comprises means for switching the video signal within a vertical blanking period. Further, the video signal switching circuit includes:
4. The video signal switching circuit according to claim 1, further comprising means for down-converting a video signal in a format that cannot be decoded and converting the video signal into a video signal that can be decoded.

Accordingly, when a television signal of a broadcast system which cannot be decoded or a component signal of a signal of an external device is received, unnecessary operations and unnecessary screen states can be omitted. According to another aspect of the present invention, there is provided a video signal switching circuit in a device to which a video signal to which format identification information for identifying a type of a format is added is input. A switch for outputting a video signal of a format specified by the signal, and determining whether or not the video signal can be decoded based on the format identification information of the input video signal, and determining that the video signal can be decoded as a result of this determination Outputs a control signal designating the input video signal to the switch, and when it is determined that the input video signal cannot be decoded as a result of the determination,
Determining means for outputting, to the switch, a control signal designating another video signal that can be decoded.

Further, the video signal switching circuit further comprises means for switching the video signal within a vertical blanking period. Further, the video signal switching circuit includes:
It is characterized by further comprising means for down-converting a video signal of a format that cannot be decoded and converting it into a video signal that can be decoded.

Accordingly, when a television signal of a broadcast system which cannot be decoded or a component signal of a signal of an external device is received, unnecessary operations and unnecessary screen states can be omitted. The present invention that achieves the above object is a video signal switching circuit in a device to which a video signal of a multi-video format is input, a receiving unit that receives a video signal of a multi-video format, Means for down-converting a video signal of a multi-video format into a video signal of a predetermined format, separating an HD pulse (Horizontal Driving pulse horizontal drive pulse) from the input video signal of the multi-video format, and counting the HD pulses Detecting the frequency of the HD pulse, determining whether or not decoding can be performed based on the frequency of the HD pulse. If the result of the determination is that decoding is possible, an instruction to switch to a video signal of the multi-video format is issued. Output, and if it is determined that decoding is not possible, Determining means for outputting an instruction to switch to a video signal of a predetermined format; means for switching to a video signal of a multi-video format in response to the instruction to switch to a video signal of the multi-video format; and an instruction to switch to a video signal of the predetermined format And means for switching to a video signal of a predetermined format in response to the

Thus, when a television signal of a broadcast system that cannot be decoded or a component signal of a signal of an external device is received, unnecessary operations and unnecessary screen states can be omitted. The present invention to achieve the above object is a video signal switching method for outputting any decodable video signal in a device to which a video signal of a multi-video format and a video signal of a predetermined format are input,
HD pulse from video signal of multi video format,
VD pulse (Vertical Driving pulse vertical drive pulse)
And a step of counting the HD pulse immediately after the VD pulse a predetermined number of times to detect the frequency of the HD pulse, and determining whether the video signal of the multi-video format can be decoded based on the frequency of the HD pulse. And, if the result of the determination is that decoding is possible, the step of holding the video signal in the multi-video format and the result of the determination, if it is determined that decoding is not possible, Switching to a video signal.

Thus, when a television signal of a broadcast system which cannot be decoded or a component signal of a signal of an external device is received, unnecessary operations and unnecessary screen states can be omitted.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described. FIG. 1 is a diagram showing the configuration of the component signal input corresponding switching circuit of the first embodiment. In FIG. 1, reference numeral 1 denotes an output unit. The output unit 1 displays an image.
RT or LCD.

Reference numeral 2 denotes a signal processing circuit. Signal processing circuit 2
Is the input component signal (eg, Y signal,
(Composed of the RY signal and the BY signal) into a signal to be displayed on the output unit 1, and the signal is output to the output unit 1.
Is output to Reference numeral 3 denotes a multi-horizontal frequency-adaptive sync separation circuit. Multi-horizontal frequency compatible sync separation circuit 3
Is to separate a synchronization signal from component signals having different input frequencies and output the synchronization signal to the output unit 1. When a component signal is input to the multi-horizontal-frequency-corresponding sync separation circuit 3, an HD pulse (Horizontal Driving pulse) is output from the component signal.
e: horizontal drive pulse) and VD pulse (Vertical Driv
ing pulse: vertical drive pulse) is separated and output.

Reference numeral 4 denotes a CPU (central processing unit). CP
U4 has storage means and counter means for counting the pulses input to the CPU 4 and detecting the frequency of the pulses based on the counted number and the count time. Therefore, the CPU 4 includes a multi-horizontal frequency-compatible synchronization separation circuit 3.
The HD pulse and the VD pulse output from are input. Then, the CPU 4 causes the counter means to count the HD pulse immediately after the VD pulse to detect the frequency of the HD pulse. Further, the CPU 4 stores an upper limit value and a lower limit value of a frequency (frequency of the HD pulse) at which the signal processing circuit 2 can decode.

Reference numeral 5 denotes a color demodulation circuit. The color demodulation circuit 5
This is a color demodulation circuit for a composite (or YC) signal. The color demodulation circuit 5 receives the input composite (or
YC) signal is converted into a component signal and output. Reference numeral 6 denotes a SW (switch). SW6 is a
A terminal, a b terminal, and a common e terminal, and e
The terminal is a SW connected to either the a terminal or the b terminal
(Switch). The SW 6 is connected to the CPU 4, and upon receiving an instruction from the CPU 4, the SW 6 sets the e terminal to a
The terminal is connected to the terminal, or the terminal e is connected to the terminal b. The component signal output from the color demodulation circuit 5 is connected to the terminal b of the SW 6. Further, the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 are connected to the e terminal of the SW 6.

Reference numeral 7 denotes a SW (switch). SW7 is
It comprises a c terminal, a d terminal, and a common f terminal,
The f terminal is connected to either the c terminal or the d terminal.
W (switch). The SW 7 is connected to the CPU 4, and upon receiving an instruction from the CPU 4, the SW 7 connects the f terminal to the c terminal or connects the f terminal to the d terminal. The f terminal of SW7 is connected to the color demodulation circuit 5.

Reference numeral 10 denotes an external input terminal. The external input terminal 10 is a terminal to which a component signal which is a video signal of a multi video format is supplied from outside.
The external input terminal 10 is connected to the terminal a of the switch SW6. Note that, for the sake of specific description, it is assumed that a component signal has already been input to the external input terminal 10 from the outside.

Reference numeral 11 denotes an external input terminal. The external input terminal 11 is connected to an NTSC system, a PAL system, and an SE
A composite signal or a YC signal (a composite signal is a video signal of a predetermined format in the CAM system)
Y: a terminal for supplying a luminance signal and C: a signal separated into a color signal). And the external input terminal 11
Connected to terminal c of SW7. Here, for the sake of specific description, it is assumed that a downconverted NTSC composite signal having the same content as the component signal of the external input terminal 10 is input to the external input terminal 11.

Reference numeral 12 denotes an external input terminal. The external input terminal 12 is externally supplied with NTSC, PAL, and SEC
A terminal for supplying a composite signal or a YC signal in the AM system. And the external input terminal 12
Connected to d side of SW7. Next, the operation of the first embodiment will be described. As an initial setting, the external input terminal 11
The component signal is downconverted to N
Information indicating that the composite signal of the TSC system is connected is stored in the storage unit of the CPU 4.

FIG. 2 is a diagram showing a flowchart of the first embodiment. First, the CPU 4 sets the e terminal to a
Instruct SW6 to connect to the terminal. The SW 6 receiving this instruction connects the e terminal to the a terminal. As a result, the component signal of the external input terminal 10 is input to the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 via the SW 6 (step S1).

The multi-horizontal frequency synchronous separation circuit 3 to which the component signal of the external input terminal 10 is inputted.
Separates the HD pulse and the VD pulse from the component signal and outputs it to the CPU 4. Upon receiving the HD pulse and the VD pulse, the CPU 4 causes the counter means of the CPU 4 to count the HD pulse immediately after the VD pulse several times, and to detect the frequency of the HD pulse within the vertical retrace period (step S2). .

Then, the CPU 4 determines the detected frequency of the HD pulse and the upper limit value and the lower limit value of the frequency (frequency of the HD pulse) which can be decoded by the signal processing circuit 2 and stored in the storage means of the CPU 4. Based on this, it is determined whether or not the signal processing circuit 2 can decode (hereinafter, also referred to as frequency determination) (step S3). When the signal processing circuit 2 determines that decoding can be performed as a result of the frequency determination, the CPU 4 sets the terminal e, which is the current state, to a
Keep the state connected to the terminal. That is, the component signal of the external input terminal 10 is kept in a state of being input to the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 from the e terminal of SW6. Then, the component signal is converted into a signal to be displayed on the output unit 1 based on the component signal by the signal processing circuit 2 and output to the output unit 1. The component signal is converted into a synchronization signal for display on the output unit 1 based on the component signal by the multi-horizontal frequency synchronization separation circuit 3 and output to the output unit 1. Then, the video of the component signal supplied to the external input terminal 10 is displayed on the output unit 1 (step S4).

If the signal processing circuit 2 determines that decoding is not possible as a result of the frequency discrimination, the CPU 4 transmits the component signal to the external input terminal 11 stored in the storage means in an NTSC composite. The terminal b and the terminal e are connected to SW6 based on the information that the signal is connected, and c is connected to SW7.
An instruction is output to each of the terminals to connect the terminal and the f terminal. Here, the timing for outputting the instruction is determined by the CPU.
4, the next input HD pulse is the trigger timing. As a result, a downconverted NTSC composite signal having the same content as the component signal of the external input terminal 10 connected to the external input terminal 11 is connected to the color demodulation circuit 5 via the SW 7. Then, the NTSC composite signal is converted into a component signal by the color demodulation circuit 5. The converted component signal is connected to the signal processing circuit 2 and the multi-horizontal frequency synchronization separation circuit 3 via the SW 6. Then, the component signal connected to the signal processing circuit 2 is converted into a signal to be displayed on the output unit 1 by the signal processing circuit 2 and output to the output unit 1.
The component signal connected to the multi-horizontal frequency sync separation circuit 3 is separated into a HD pulse and a VD pulse by the multi-horizontal frequency sync separation circuit 3 and output to the output unit 1. The output unit 1 performs a display based on the signals output from the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 (step 5).

Thus, even when a component signal that cannot be decoded is input, a signal obtained by down-converting the component signal can be displayed. When a component signal that can be decoded by performing the above-described steps (1 to 5) at predetermined intervals is input, the component signal is displayed. When a component signal that cannot be decoded is input, the component signal is displayed. Can display the downconverted signal.

Next, a second embodiment will be described. FIG. 3 is a diagram illustrating a configuration of a component signal input correspondence switching circuit based on video format identification information according to the second embodiment. In the description of the second embodiment, a description of the same parts as in the first embodiment will be omitted, and only different parts will be described.

In FIG. 3, reference numeral 8 denotes a multi-video format receiving circuit. The multi-video format receiving circuit 8 receives video signals having different frequencies, demodulates the video signals into component signals, and outputs the component signals. Further, the multi-video format receiving circuit 8 outputs to the CPU 4 a format identification signal that is format identification information for identifying the type of the format of the received video signal.

Reference numeral 9 denotes a down-converter circuit. The down converter circuit 9 is a multi video format receiving circuit 8
Supplies a component signal, and down-converts the component signal into a composite signal of NTSC / PAL / SECAM signal or YC signal. The multi-video format receiving circuit 8 is connected to the a terminal of the SW 6 and supplies a component signal to the a terminal of the SW 6. The multi video format receiving circuit 8 is connected to the down converter circuit 9 and supplies a component signal to the down converter circuit 9.

The down-converter circuit 9 is connected to the terminal c of the switch SW7 and outputs a composite signal or a YC signal to the terminal c of the switch SW7. Next, the operation of the second embodiment will be described. Multi video format receiving circuit 8
Is supplied to the terminal a of the SW 6 and the down-converter circuit 9.

The down-converter circuit 9 down-converts the input signal into a composite signal of NTSC / PAL / SECAM signal or YC signal, and outputs the down-converted signal to the terminal c of SW7. Here, the signal output from the down converter circuit 9 is NT
It is assumed to be an SC composite signal. The CPU 4 determines whether or not the signal processing circuit 2 can decode based on the format identification signal received from the multi-video format receiving circuit 8.

When the signal processing circuit 2 determines that decoding can be performed, the CPU 4 sets SW6 to SW6.
An instruction is output to connect the e terminal 6 to the a terminal. Upon receiving the instruction, the SW 6 connects the e terminal to the a terminal. Thus, the component signal supplied from the multi-video format receiving circuit 8 is converted into a signal for display on the output unit 1 based on the component signal by the signal processing circuit 2 via the SW 6 and output to the output unit 1. .
The component signal is converted into a synchronization signal for display on the output unit 1 based on the component signal by the multi-horizontal frequency synchronization separation circuit 3 and output to the output unit 1.

If the signal processing circuit 2 determines that decoding is not possible, the CPU 4 outputs the NTSC composite signal obtained by down-converting the component signal to the terminal c of SW7 stored in the storage means. Are output to SW6 to connect the b terminal side and the e terminal side, and SW7 to the SW terminal to connect the c terminal side and the f terminal side. Thus, the downconverted NTSC composite signal having the same content as the component signal supplied from the multi-video format receiving circuit 8 is connected to the color demodulation circuit 5 via the downconverter circuit 9 and SW7. Then, the NTSC composite signal is converted into a component signal by the color demodulation circuit 5. The converted component signal is connected to the signal processing circuit 2 and the multi-horizontal frequency synchronization separation circuit 3 via the SW 6. Then, the component signal connected to the signal processing circuit 2 is converted into a signal to be displayed on the output unit 1 by the signal processing circuit 2 and output to the output unit 1. Further, the component signals connected to the multi-horizontal frequency synchronous separation circuit 3 are subjected to synchronous separation of the HD pulse and the VD pulse by the multi-horizontal frequency synchronous separation circuit 3 and output to the output unit 1. The output unit 1
The display is performed based on the signals output from the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3.

Next, a third embodiment will be described. FIG. 4 is a diagram illustrating a configuration of a component signal input corresponding switching circuit according to the third embodiment. In the description of the third embodiment, a description of parts similar to those of the first embodiment and the second embodiment will be omitted, and only different parts will be described.

The CPU 4 receives a VD pulse and an HD pulse from the multi-horizontal frequency sync separation circuit 3 and a video format identification signal from the multi-video format receiving circuit 8. When the video format identification signal is input from the multi video format receiving circuit 8, the CPU 4 determines whether or not the signal processing circuit 2 can decode based on the video format identification signal.

When the video format identification signal is not input from the multi video format receiving circuit 8, the CPU 4 determines whether or not the signal processing circuit 2 can decode the signal from the multi-horizontal frequency sync separation circuit 3. The determination is made based on the received VD pulse and HD pulse.

[0045]

As described above, according to the present invention, unnecessary operations by the user can be eliminated, and unnecessary screen states (video mute) can be eliminated. In a broadcast such as a digital broadcast in which the video format changes depending on the time zone, the user does not need to switch the signal during viewing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a component signal input correspondence switching circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a flowchart of a first embodiment according to the present invention.

FIG. 3 is a diagram showing a configuration of a component signal input correspondence switching circuit based on video format identification information according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a component signal input corresponding switching circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional component signal input correspondence switching circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Output part 2 Signal processing circuit 3 Multi-horizontal frequency synchronous separation circuit 4 CPU 5 Color demodulation circuit 6, 7 SW (switch) 8 Multi video format receiving circuit 9 Down converter circuit 10, 11, 12 External input terminal

Claims (9)

[Claims] 1. A video signal switching circuit in a device to which video signals of different formats are input, wherein a switch that receives video signals of different formats and outputs a video signal of a format specified by a control signal, Judge whether the decoded video signal can be decoded,
If it is determined that decoding can be performed as a result of this determination, a control signal specifying the input video signal is output to the switch.If it is determined that the input video signal cannot be decoded as a result of the determination, Determining means for outputting, to the switch, a control signal designating a video signal of another format that can be decoded. 2. The apparatus according to claim 1, wherein the determining unit is configured to output an HD pulse (Horizont pulse) from the input multi-video format video signal.
al Driving pulse (horizontal drive pulse), and means for separating and outputting the output. The output HD pulse is counted, the frequency of the HD pulse is detected, and it is determined whether decoding can be performed based on the frequency of the HD pulse. 2. The video signal switching circuit according to claim 1, further comprising: 3. The video signal switching circuit according to claim 1, wherein said video signal switching circuit further includes means for switching a video signal within a vertical blanking period. . 4. The video signal switching circuit according to claim 1, further comprising means for down-converting a video signal in a format that cannot be decoded and converting the video signal into a video signal that can be decoded. 2. The video signal switching circuit according to claim 1. 5. A video signal switching circuit in a device to which a video signal to which format identification information for identifying a type of a format is added is input, wherein a video signal of a different format is input and specified by a control signal. A switch for outputting a video signal of a format, and determining whether or not the video signal can be decoded based on the format identification information of the input video signal. If it is determined that the video signal can be decoded, The switch outputs a control signal specifying the video signal to the switch.If the result of the determination is that the input video signal cannot be decoded, a control signal specifying another video signal that can be decoded is transmitted to the switch. A video signal switching circuit, comprising: a determination unit that outputs the video signal. 6. The video signal switching circuit according to claim 5, wherein said video signal switching circuit further includes means for switching a video signal within a vertical blanking period. 7. The video signal switching circuit according to claim 5, further comprising means for down-converting a video signal in a format that cannot be decoded and converting the video signal into a video signal that can be decoded. 2. The video signal switching circuit according to claim 1. 8. A video signal switching circuit in a device to which a video signal of a multi-video format is input, a receiving unit receiving a video signal of the multi-video format, and a video of the multi-video format received by the receiving unit. Means for down-converting a signal into a video signal of a predetermined format; separating an HD pulse (Horizontal Driving pulse horizontal drive pulse) from the input multi-video format video signal; counting the HD pulses;
Detecting the frequency of the pulse, determining whether decoding can be performed based on the frequency of the HD pulse, and outputting a command to switch to a video signal of the multi-video format when determining that decoding can be performed as a result of the determination, A determination unit that outputs an instruction to switch to the video signal of the predetermined format when it is determined that decoding cannot be performed as a result of the determination; and a video signal of the multi video format in response to the instruction to switch to the video signal of the multi video format. A video signal switching circuit, comprising: means for switching to a video signal; and means for switching to a video signal of a predetermined format in response to an instruction to switch to a video signal of the predetermined format. 9. A video signal switching method for outputting any decodable video signal in a device to which a video signal of a multi-video format and a video signal of a predetermined format are input, comprising: HD pulse,
VD pulse (Vertical Driving pulse vertical drive pulse)
Separating the number of HD pulses immediately after the VD pulse a predetermined number of times, and detecting the frequency of the HD pulse; and determining whether the video signal of the multi-video format can be decoded based on the frequency of the HD pulse. And a step of holding the video signal of the multi-video format if it is determined that decoding is possible, and a step of holding the video signal of the multi-video format. Switching to a video signal.