JP2000175077A - Noise level detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise level detection circuit that can detect a noise from a video signal on which a copy guard signal is superimposed and a video signal that is digital-processed with high precision stably. SOLUTION: A BPF 103 extracts an AC component of an input luminance signal, a full wave rectifier circuit 104 rectifies the AC component and converts it into an absolute value, which is fed to a sample integration circuit 105, where the signal is sampled and integrated for a prescribed period of a back porch for a horizontal blanking period, a line integration circuit 106 integrates the signal in the unit of lines for a prescribed scanning period and the integration result is used for a noise level detection signal. Thus, a noise can be detected from a video signal on which a copy guard signal is superimposed with high precision stably. After the input luminance signal is digitized through an A/D converter 102, the signal is processed through the processing after the BPF 103, then a noise can be detected from a video signal that is digital-processed with high precision stably.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a noise level detecting circuit for detecting a noise component of a video signal.

[0002]

2. Description of the Related Art A conventional noise detection circuit is disclosed in
As described in Japanese Patent No. 1076, for example, noise of an input video signal is detected for the purpose of controlling a noise suppression circuit. That is, the high-frequency component of the input luminance signal is extracted by a high-frequency filtering circuit, which is subjected to full-wave rectification by a full-wave rectification circuit, and the amount of the image high-frequency component is detected. The average value of the detected signal during the vertical synchronizing signal period is detected by the sample and hold circuit, and the detected voltage is held during the effective video signal period, so that when this voltage is large, there is much noise, In this case, the noise of the video signal is automatically suppressed by turning on the noise suppression circuit and weakening the input video luminance signal according to the voltage. As described above, the noise detection position of the input video signal is a predetermined period in the vertical blanking period (hereinafter, vertical blanking period).

In recent years, there is a video device that outputs a video signal on which a copy guard signal is superimposed. For example, it is a recording / reproducing device such as a digital video disk (DVD) or home VTR software on which a copy guard signal is recorded and superimposed. This copy guard signal is for preventing normal recording on a home VTR. Among such copy guard methods, there is a copy guard signal in which a video signal having a white peak during a vertical blanking period is superimposed. If such a signal is superimposed in the vertical blanking period, the conventional noise detection circuit may erroneously detect the copy guard signal as a noise component.

In general, a character multiplex signal and the like are superimposed during a vertical blanking period of a TV video signal, but a copy guard signal is further superimposed. Also,
In a home VTR, head switching noise occurs during the vertical synchronization period. Performing noise detection during the vertical blanking period in this manner may cause erroneous detection.

[0005] In recent TV receivers, digital processing circuits such as a line comb filter and a three-dimensional Y / C separation circuit have been introduced. If the noise detection is to be performed at a portion other than the back porch during the horizontal blanking period, for example, at the horizontal synchronizing signal portion, it is necessary to quantize the noise including the noise amplitude superimposed on the tip (sync chip) of the horizontal synchronizing signal. In this case, the input range must be included in a range that is not originally a video scanning period, so that the S / N of the video signal at the time of quantization in the A / D conversion circuit is deteriorated.

[0006]

As described above, in the conventional noise detection circuit, the noise detection circuit may make an erroneous determination due to the copy guard signal superimposed during the vertical blanking period. If the noise detection is to be performed in the horizontal synchronizing signal portion, the input range of the A / D conversion circuit required for digital processing must be expanded more than necessary, which may degrade the S / N of the video signal. was there.

In view of the above problems, the present invention provides a noise level detection circuit capable of performing stable and highly accurate noise detection on a video signal on which a copy guard signal is superimposed or on a digitally processed video signal. The purpose is to provide.

[0008]

According to a first aspect of the present invention, there is provided a noise level detecting circuit for extracting an AC component of a luminance signal and rectifying the AC component, and for converting the rectified signal during a horizontal blanking period. The integrated circuit includes a sample integration circuit that performs sample integration during a predetermined period of the back porch, a line integration circuit that integrates a signal after sample integration for a predetermined scanning line period, and a circuit that holds an integration signal of the line integration circuit. .

According to a second aspect of the present invention, there is provided a noise level detecting circuit for extracting an AC component of a luminance signal and rectifying the AC component, and rectifying the rectified signal in a predetermined period of a back porch in a horizontal blanking period. A sample integration circuit for performing sample integration, a line integration circuit for integrating a signal after sample integration for a predetermined scanning line period, a field integration circuit for integrating a signal after line integration for a predetermined field period, and an integration signal of the field integration circuit And a circuit for holding

According to the first and second aspects of the present invention, an AC component of a luminance signal is extracted and rectified, sample integration is performed in a predetermined period of a back porch in a horizontal blanking period, and a predetermined scanning line period (a video period). ), The line integration is performed only. Therefore, compared to the case where the noise detection position is set to the vertical blanking period as in the conventional case, the accuracy of the video signal on which the copy guard signal is superimposed or the digitally processed video signal is more stable. High noise detection can be performed.

According to a third aspect of the present invention, in the noise level detecting circuit according to the first or second aspect, the line integration circuit performs an integration operation during a video scanning period excluding a vertical blanking period.

According to the third aspect of the present invention, line integration is performed in a video scanning period in which the influence of noise is more likely to appear on a screen than in a vertical blanking period, and a noise level detection signal is obtained. Therefore, it is possible to obtain a noise detection result corresponding to actual visual noise.

According to a fourth aspect of the present invention, in the noise level detection circuit according to any one of the first to third aspects, the circuit for extracting and rectifying the AC component is provided in a stage preceding the noise level detection circuit.
A / D for converting analog luminance signal to digital luminance signal
A conversion circuit is further provided, and a noise level detection operation is performed with a digital luminance signal.

According to the fourth aspect of the present invention, after the analog luminance signal is converted into a digital signal, the AC component is rectified, sampled and integrated in a predetermined period of a back porch in a horizontal blanking period, and further, a line is provided for a predetermined image period. Since integration is performed, compared to the case where noise detection is performed in the horizontal synchronization signal part,
There is no need to extend the input range of the A / D conversion circuit required for digital processing more than necessary, and the S /
There is little risk of deteriorating N.

According to a fifth aspect of the present invention, there is provided a noise level detecting circuit for extracting an AC component of a luminance signal and rectifying the AC component, and a noise level detecting circuit for detecting a noise level during a predetermined period of a back porch during a horizontal blanking period. Means for generating a gate pulse, a sample integration circuit for performing sample integration of the signal after the AC component rectification during the period of the gate pulse, and gate pulse control means for controlling the gate pulse to a different arbitrary position. Things.

According to a sixth aspect of the present invention, in the noise level detection circuit of the fifth aspect, the gate pulse control means controls a gate pulse position so that a noise detection value obtained by the sample integration circuit becomes minimum. Features.

According to the fifth and sixth aspects of the present invention, the noise component detection accuracy is improved by setting the noise level detection gate position in the back porch period so that the noise detection value obtained by the sample integration circuit is minimized. Can be done.

A noise level detecting circuit according to a seventh aspect of the present invention is a noise level detecting circuit for automatically determining an optimum position of a noise level detecting gate pulse with respect to an input luminance signal. After the band is limited by a band-pass filter, the filter output is subjected to absolute value conversion, a circuit for limiting the output within a certain level, and a detection for controlling a plurality of noise integration circuits based on the input horizontal and vertical synchronization signals. A control circuit and a noise level detection gate pulse finally obtained based on a control signal from the detection control circuit in a predetermined period of a back porch during a horizontal blanking period of the luminance signal, N (N is a natural number) A sample integration circuit for pixel integration and an M (M is a natural number) line product of an output of the sample integration circuit by a control signal from the detection control circuit A line integration circuit, a field integration circuit for integrating the output of the line integration circuit in an L (L is a natural number) field by a control signal from the detection control circuit, and a noise level detection gate in response to an instruction from the microcomputer. A judgment control circuit for generating various control signals for judging that the pulse is at an optimal position with respect to the luminance signal; and a noise level detection circuit for use in the sample integration circuit based on a signal output from the judgment control circuit. Selection circuit for varying the position of the gate pulse for use, and the noise level detection gate pulse are set arbitrarily n times (n: natural number) at different positions by the delay selection circuit, and the sample line in each state is set. Based on the integration result of
An optimal position determination circuit for determining an optimal noise level detection gate position, based on a determination result from the optimal position determination circuit, controlling the delay selection circuit, and holding the noise level detection gate at an optimal position. In this state, stable noise level detection is possible.

According to the seventh aspect of the present invention, when the noise level detection gate pulse is set in the back porch period of the horizontal blanking period, the noise level detection gate pulse is arbitrarily set n times (n : Natural number)
An optimum position determination circuit for determining the optimum noise level detection gate position based on the integration result of the sample line in each state is provided, so that delay selection is performed based on the determination result from the optimum position determination circuit. By controlling the circuit and holding the noise level detection gate at the optimum position, it is possible to perform stable noise level detection.

According to a eighth aspect of the present invention, in the noise level detecting circuit according to the seventh aspect, when the delay selection circuit changes the gate pulse position by n (n: natural number) times to make a determination, the noise is detected in the vicinity of the center. A circuit for providing an offset value so as to be an optimum noise level detection gate position in (m: natural number) determinations is further provided to enable stable detection of the optimum position of the noise level detection gate regardless of disturbance. It is characterized by.

According to the eighth aspect of the present invention, it is difficult to determine an erroneous detection position as optimal due to accidental noise while determining the optimum position of the noise level detection gate. An offset period (identification period) is provided at a position in a range determined to be the optimum position, so that a period in which the position is originally stable is easily determined as the optimum position (decision probability is increased).

According to a ninth aspect of the present invention, in the noise level detection circuit according to the seventh aspect, the input luminance signal is a standard signal or a non-standard signal such as a VTR special reproduction signal, based on the input horizontal and vertical synchronization signals. Determine whether the signal is a standard signal, and when the determination result changes from non-standard to standard, generate a control signal for re-determining the optimum position of the noise detection gate again, and supply the control signal to the determination control circuit. It is characterized by further comprising a judgment circuit.

According to the ninth aspect of the present invention, a standard / non-standard signal is determined based on a synchronization signal of an input signal, and when the determination changes from non-standard to standard, the noise level detection gate is optimized again. Determine the position. This makes it possible to determine the position of the noise level detection gate in a standard state of a stable signal.

According to a tenth aspect of the present invention, in the noise level detection circuit of the seventh aspect, when the value of the noise level detection result detected by the field integration circuit changes greatly, the optimum position of the noise detection gate is again determined. A circuit for generating a control signal for redetermining and supplying the control signal to the determination control circuit is further provided.

According to the tenth aspect, when the value of the noise level detection result changes significantly, the optimum position of the noise level detection gate is determined again. This makes it possible to determine the position of the noise level detection gate in a standard state of a stable signal, as in the ninth aspect.

[0026]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a noise level detection circuit according to a first embodiment of the present invention.

In FIG. 1, the noise level detection circuit comprises:
An input terminal 101 for inputting an analog luminance signal,
A / D conversion circuit 102 for converting an analog luminance signal into a digital luminance signal, and a band-pass filter (BPF) 103 for extracting an AC component of the digital luminance signal
And full-wave rectification of the AC component to convert it to an absolute value (by converting the negative component of the AC component to the positive component,
A full-wave rectifier circuit 104 for expressing the entire C component only with an absolute value), a sample integrator circuit 105 for sample-integrating the rectified signal in a predetermined period of the back porch during the horizontal blanking period, and , A holding circuit 107 for holding the line integration result, an output terminal 108 for outputting the holding signal as a noise level detection signal, and a horizontal synchronizing signal. (HD), a clock generation circuit 109 for generating a clock pulse used for sampling or the like, a sample integration circuit 105 and a line integration circuit based on a vertical synchronization signal (VD), a horizontal synchronization signal (HD), and the clock pulse. 106 Timing generation for generating a timing signal such as a gate pulse for determining each integration period A road 110, the vertical synchronizing signal of the input luminance signal (VD), and is configured with an input terminal 111, 112 for inputting the horizontal synchronizing signal (HD), respectively.

In the above configuration, the luminance signal input from the input terminal 101 is converted into a digital signal by the A / D conversion circuit 102, and the digital signal is transmitted through the BPF 103 to the full-wave rectification circuit 10.
4 is input. The BPF 103 extracts a Takagi AC component of about 2 MHz or higher that is visually noticeable in the digital luminance signal. It is assumed that the color burst signal included in the back porch of the analog luminance signal in the horizontal blanking period has been removed in the processing preceding the input terminal 101.

The output signal of the full-wave rectifier circuit 104 is integrated by a sample integrator circuit 105 for a predetermined sample period. Here, the predetermined sample period is set to a relatively stable predetermined period in the back porch of the horizontal blanking period of the luminance signal.

The sample integration circuit 105 includes an adder 120
And an AND gate 121 supplied with a gate pulse a from the timing generation circuit 110;
09 and a D flip-flop 122 which operates by being supplied with the same clock as the sampling clock used in the A / D conversion circuit 102.

In the adder 120, the output signal of the full-wave rectifier circuit 104 and the output signal of the flip-flop 122 are added. The gate pulse a is input to the AND gate 121, and the output signal of the adder 120 is guided to the flip-flop 122 only when the gate pulse a is at the “H” level. When the gate pulse a is at the “L” level, the output signal of the AND gate 121 is at the “L” level regardless of the output signal of the adder 120.
Also becomes the “L” level. That is, the sample integration circuit 105 performs an integration operation on the output signal of the full-wave rectification circuit 104, which is an absolute value circuit, only while the gate pulse a is at the “H” level. FIGS. 2A and 2B show the timing of the gate pulse a.

The output signal of the sample integration circuit 105 is input to the line integration circuit 106. Line integration circuit 106
Operates with an adder 123, an AND gate 124 supplied with a gate pulse b from the timing generation circuit 110, and a clock supplied from the clock generation circuit 109 which is the same as the sampling clock used in the A / D conversion circuit 102. And a D flip-flop 125 that performs the operation.

In the adder 123, the sample integrator 10
5 and the output signal of the flip-flop 125 are added, and the output signal of the adder 123 is
To the flip-flop 125 via That is, like the sample integration circuit 105, the line integration circuit 106 integrates the output signal of the sample integration circuit 105 only during the period when the gate pulse b input to the AND gate is at the “H” level. 3 (a) and 3 (b) show the gate pulse b
The timing of is shown.

In a home video tape recorder (VTR), skew may occur during the vertical blanking period. Therefore, it is convenient to allow time for skew to be drawn in and generate the skew at the timing shown in FIG. It is.
It is sufficient to set the timing at which the gate pulse b rises 50 to 60 lines after the end of the vertical blanking period.

The integration output of the line integration circuit 106 is held by the flip-flop 107 for a necessary period by the timing signal from the timing generation circuit 110, and is output from the output terminal 108 as a noise level detection signal.

For example, if the frequency of the sampling clock CLK is 910 times the horizontal synchronization frequency, the gate pulse a in the back porch during the horizontal blanking period is set.
Is equivalent to 24 samples and has a pulse width of about 1.7 μs. That is, using the gate pulse a having a pulse width of 1.7 μs, sample integration for 24 samples is performed in a predetermined period of the back porch.

The value obtained by integrating the 24 samples is used by the line integration circuit 106 to obtain, for example, 1
Integration of 28 lines results in 3072 samples per field, which is the number of samples corresponding to 3 lines or more in the horizontal scanning period, and enables stable noise detection.

FIG. 4A shows an input signal and an output signal of the full-wave rectifier circuit 104. The sample signal after full-wave rectification after passing through the BPF 103 has a positive portion and a negative portion around the 0 level, and the sample signal after full-wave rectification of the positive and negative signals through the full-wave rectifier circuit 104 has a negative portion. Is turned back to the positive electrode side and converted to an absolute value. In the sample signals before and after full-wave rectification, 0, 3, 4, and 5 indicate the absolute value of each sample. In fact, A
/ D conversion so that 0, 3,
4 and 5 are 3-digit binary numbers, 000,011,100,1
Although it is expressed as 01, it is described as a signal of decimal numbers 0, 3, 4, and 5 for convenience.

FIG. 4B is a diagram for explaining the operation of the sample integration circuit 105. Input S to sample integration circuit 105
The case where the sample signals (signals of absolute values 0, 3, 4, and 5) after full-wave rectification shown in FIG. In the sample integration circuit 105, S1 is the output signal of the full-wave rectification circuit 104 (adder 10).
2), and S2 is an AND signal.
An output signal of the gate 121 is shown, and S3 is an output signal of the flip-flop 122 (the other input signal of the adder 102). In the sample integrator circuit 105, when the gate pulse a to the AND gate 121 is at the "H" level, the relationship of S1 + S3 = S2 holds, and the added value S2 is input to the flip-flop 122 of the next stage and the next clock pulse It is output as a signal S3 at the rising timing of CLK. The input sample signal (0,
(3, 4, 5), the integral output S3 is finally 5 + 7 = 1.
It is 2. Gate pulse a of AND gate 121
Becomes "L" level, the signal S2 becomes 0, and the 0 is output from the flip-flop 122 as the signal S3 at the rising edge of the next clock pulse CLK.

FIG. 5 is a block diagram showing a noise level detecting circuit according to a second embodiment of the present invention. The difference from FIG. 1 is that a field integration circuit 202 is provided after the line integration circuit 106.

The integration output of the line integration circuit 106 is input to the field integration circuit 202 after being held by the flip-flop 201.

The field integration circuit 202 includes the adder 21
0 and the gate pulse c from the timing generation circuit 205
, And a D flip-flop 212 that operates by being supplied with the same clock as the sampling clock used in the A / D conversion circuit 102 from the clock generation circuit 109.
Performs an integration operation during a period when the gate pulse c is at the “H” level. That is, the field integration circuit 202 inputs the signal after the line integration, integrates the signal for a predetermined field period defined by the gate pulse c, and outputs the integrated signal. The timing generation circuit 110 generates the gate pulses a and b based on the horizontal and vertical synchronization signals (HD, VD) and the clock pulse similarly to the timing generation circuit 110 of FIG. 1, and also generates the horizontal and vertical synchronization signals (HD, VD). VD) and a gate pulse c based on the clock pulse.

The integration output of the field integration circuit 202 is
The signal is held in the flip-flop 107 only for a necessary period by a timing signal from the timing generation circuit 110, and is output from the output terminal 108 as a noise level detection result.

With such a configuration, a signal obtained by integrating the noise component in the back porch period of the horizontal blanking period, by a predetermined number of scanning line periods, and by a predetermined number of fields, is subjected to field integration. It can be obtained as a noise level detection result.

FIG. 6 is a block diagram showing a noise level detecting circuit according to a third embodiment of the present invention.

In FIG. 6, the noise level detection circuit comprises:
An input terminal 101 for inputting an analog luminance signal,
An A / D conversion circuit 102 for converting an analog luminance signal into a digital luminance signal, a BPF 103 for extracting an AC component of the digital luminance signal, and a BPF 103 for full-wave rectifying the AC component and converting it to an absolute value. Wave rectifier circuit 104 and holding circuit 107 for holding the signal after sample integration
, An output terminal 108 for outputting a holding signal as a noise level detection signal, and an input horizontal and vertical synchronization signal (H
D, VD) and a detection control circuit 512 for controlling the sample integration circuit 105, and a signal after rectification from the full-wave rectification circuit 104 is detected by the detection control circuit 512 for a predetermined period of a back porch during a horizontal blanking period. A sample integrator circuit 105 for integrating a sample of N (N is a natural number) pixels by a noise level detection gate pulse finally obtained based on a control signal from the control circuit; Control circuit 521 for generating various control signals for determining that the position is optimal for
A delay selection circuit 522 for changing a gate pulse position by changing a delay amount of a noise level detection gate pulse used in the sample integration circuit 105 based on a signal output from the determination control circuit 521; The detection gate pulse is set arbitrarily n times (n: natural number) at different positions by the delay selection circuit 522, and based on the result of the sample integration in each state, the gate pulse at which the integration result becomes the minimum level And an optimum position determination circuit 523 for determining the phase of the gate signal as the optimum noise level detection gate position. Based on the optimum position determination result from the optimum position determination circuit 523, the determination control circuit 521 delays the gate pulse. By determining the amount and controlling the delay selection circuit 522 to set the noise level detection gate to the optimum position, Thereby enabling the noise level detection.

In the above configuration, the luminance signal input from the input terminal 101 is converted into a digital signal by the A / D conversion circuit 102, and the digital signal is transmitted through the BPF 103.
4 is input. The BPF 103 extracts a Takagi AC component of about 2 MHz or higher that is visually noticeable in the digital luminance signal. Note that the color burst signal included in the back porch of the analog luminance signal in the horizontal blanking period has been removed in the processing at the preceding stage of the input terminal 101. The output signal of the full-wave rectifier circuit 104 is supplied to a sample integrator circuit 105 for detecting a noise level, where the sample signal is integrated for a predetermined period in a back porch during a horizontal blanking period. The predetermined period of the sample integration is set to a period in which the waveform is stable and the noise level is the smallest in the back porch of the horizontal blanking period of the luminance signal by the optimal position control of the noise level detection gate described later.

On the other hand, as for a control system for controlling the noise level detection gate to the optimum position, the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) of the input luminance signal are inputted from the input terminals 112 and 111, respectively. , Detection control circuit 512. The detection control circuit 512 supplies a control signal such as a reset signal to the sample integration circuit 105,
Further, a gate pulse for noise level detection is given to the delay selection circuit 522.

The decision control circuit 521 includes a delay selection circuit 52
2, a control signal for changing the delay amount of the noise level detection gate pulse output from the detection control circuit 512 is generated.

The optimum position determination circuit 523 compares the respective integration results when the phase of the noise level detection gate pulse is changed n times by the determination control circuit 521, and detects the noise level at which the integrated value becomes the minimum level. The optimum gate position is determined to be the optimum position, and the optimum position n is returned to the determination control circuit 521.

In the judgment control circuit 521, a control signal for holding the optimum position n of the noise level detecting gate pulse is supplied to the delay selection circuit 522 based on the judgment result of the optimum position judgment circuit 523.

The result of the sample integration circuit 105 is output to the holding circuit 107, and is held for an arbitrary fixed period by the noise level holding control signal given from the detection control circuit 512, and is output from the output terminal 108 as a noise level detection signal. Output. As described above, even if the back porch of the input luminance signal in the horizontal blanking period changes depending on the state of the input signal (television signal, VTR signal, DVD signal, game machine signal by radio wave) (the luminance signal waveform in FIG. 8). ), The noise level detection gate can be set at the optimum position to stably detect the noise level.

FIG. 7 is a block diagram showing a noise level detecting circuit according to a fourth embodiment of the present invention.

In FIG. 7, the noise level detection circuit
An input terminal 101 for inputting an analog luminance signal,
An A / D conversion circuit 102 for converting an analog luminance signal into a digital luminance signal, a BPF 103 for extracting an AC component of the digital luminance signal, and a BPF 103 for full-wave rectifying the AC component and converting it to an absolute value. Wave rectifier circuit 104 and limiter circuit 603 for limiting the upper limit level of the rectified signal
And a detection control circuit 512 for controlling the plurality of noise integrating circuits 106 and 202 based on the input horizontal and vertical synchronizing signals (HD, VD), and the detection by the back porch during the horizontal blanking period of the luminance signal. A sample integration circuit 105 for integrating N (N is a natural number) pixels by a noise level detection gate pulse finally obtained based on a control signal from a control circuit 512;
Is integrated by the control signal from the detection control circuit 512 for M (M is a natural number) lines.
06 and the output of the line integration circuit 106 are changed to L (L is a natural number) by a control signal from the detection control circuit 512.
Field integration circuit 202 for integrating by field, and holding circuit 107 for holding the signal after field integration
And an output terminal 108 for outputting the holding signal as a noise level detection signal, and receiving an instruction from the microcomputer 620,
A judgment control circuit 521 for generating various control signals for judging that the noise level detection gate pulse is at an optimum position with respect to the luminance signal, and the judgment control circuit 521
Sample integrator 1 based on the signal output from
05, a delay selection circuit 522 that varies the delay amount of the gate pulse for noise level detection to vary the position of the gate pulse, and the noise level detection gate is placed n times at different positions in the delay selection circuit 522 arbitrarily. (N: natural number), and based on the results of the sample line integration in each state, an optimum position determination circuit 523 that determines the phase of the gate pulse at which the integration result has the minimum level as the optimum noise level detection gate position. The determination control circuit 521 determines the delay amount of the gate pulse based on the optimum position determination result from the optimum position determination circuit 523, and controls the delay selection circuit 522 to detect the noise level. By setting the gate at the optimum position, stable noise level detection is possible.

In the above configuration, the luminance signal input from the input terminal 101 is converted into a digital signal by the A / D conversion circuit 102, and the digital signal is transmitted through the BPF 103 to the full-wave rectification circuit 10.
4 is input. The BPF 103 extracts a Takagi signal of about 2 MHz or more, which is visually noticeable, from the luminance signal, and supplies the extracted signal to the full-wave rectifier circuit 104 at the subsequent stage.

In the full-wave rectifier circuit 104, the output of the BPF 103 is converted into an absolute value, and the converted value is supplied to a limiter circuit 603 to limit the upper limit level, and is supplied to a sample integrator circuit 105 in the subsequent stage.

On the other hand, with respect to a control system for controlling the noise level detection gate to the optimum position, a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) of an input luminance signal are input from input terminals 112 and 111, respectively. , Detection control circuit 512.

The detection control circuit 512 includes a gate pulse for noise level detection, a line integration control signal, and a field integration signal for controlling the sample integration circuit 105, the line integration circuit 106, the field integration circuit 202, and the noise level holding circuit 107, respectively. It generates an integration control signal, a noise level holding control signal, and the like.

Here, the judgment control circuit 521
When the determination control circuit 521 receives an instruction for noise level determination from the detection control circuit 51,
2 generates a control signal for changing the delay amount of the noise level detection gate pulse output from the control signal 2.

In the delay selection circuit 522, the phase of the noise level detection gate pulse output by the control signal from the determination control circuit 521 is shifted by n (n) with respect to the back porch in the horizontal blanking period of the input luminance signal. : Natural number) The amount of delay can be varied. And
With the noise level detection gate pulse output from the delay selection circuit 522, the sample integration circuit 105 performs integration for an arbitrary fixed period corresponding to the gate pulse on the back porch of the horizontal blanking period of the luminance signal. It is provided to a line integration circuit 106.

The line integration circuit 106 performs integration for a predetermined line period according to the line integration control signal supplied from the detection control circuit 512, and supplies the result to the optimum position determination circuit 523 and the field integration circuit 202. The optimum position determination circuit 523 compares each integration result when the phase of the noise level detection gate pulse is changed n times by the determination control circuit 521, and optimizes the phase of the noise level detection gate pulse which is the minimum level. The position is determined, and the optimum position n is returned to the determination control circuit 521.

The determination control circuit 521 supplies a control signal for maintaining the optimum position n to the delay selection circuit 522 based on the determination result of the optimum position determination circuit 523, and the delay selection circuit 522 detects the optimum noise level. A gate pulse is generated, sample integration in the back porch is performed, line integration is performed, and the integration result is given to the field integration circuit 202.

In the field integration circuit 202, an arbitrary predetermined field period integration is performed by the field integration control signal given from the detection control circuit 512, and the result of the noise integration is given to the noise level holding circuit 107.

In the noise level holding circuit 203, the noise level holding signal is updated every predetermined fixed field period by the noise level holding control signal supplied from the detection control circuit 512, and the noise level detection signal is output from the output terminal 108. Is output as

As described above, even if the back porch of the input luminance signal within the horizontal blanking period changes depending on the state of the input signal (television signal, VTR signal, DVD signal, game machine signal by radio wave) (FIG. 8). (See the edge portion of the back porch in the luminance signal waveform), and the noise level can be stably detected by setting the noise level detection gate to the optimum position.

Next, another embodiment of the operation for determining the optimum position of the gate pulse for noise level detection when performing the noise level detection on the input luminance signal in the noise level detection circuit of FIG. 8 and 9 will be described.

FIG. 8 shows both ends (edges) of the back porch of the luminance signal depending on the type of the luminance signal (television signal, VTR signal, DVD signal, game machine signal, etc. by radio waves).
Even when there is a waveform fluctuation in the part (indicated by multiple solid lines) or when there is disturbance noise during the essentially stable period corresponding to approximately the middle of the back porch, the inherent stability equivalent to approximately the middle of the back porch In order to increase the probability that the determined period is determined as the optimum position of the noise level detection gate, an offset period for distinguishing the originally stable period from the others and an offset value for facilitating the optimum position determination (4 hex in the figure) , Hex is provided with a means for giving hexadecimal meaning). In other words, when the delay selection circuit 522 changes the position of the noise level detection gate n (n: natural number) times during the back porch period to make a determination,
Means for giving a predetermined offset value to the line integral value in the range of the gate position m times near the center (offset period) so that the optimum noise level detection gate position is obtained during (m: natural number) determinations is further provided. .

When the noise level is detected by changing the gate position n times during the back porch period, the offset value is subtracted for m times near the center from the sample line integration results of each time. As a result, when disturbance noise occurs near the center of the back porch period,
The integrated value near the center increases due to the disturbance noise, but is subtracted by the offset value, and the integrated value for optimal position determination is calculated to be small. Therefore, the noise level detection gate position is set near the almost stable center of the back porch. can do. Means for giving the offset value,
Means for subtracting the offset value may be provided in the optimum position determination circuit 523.

FIG. 9 is a timing chart for explaining the operation of determining the optimum position of the noise level detection gate shown in FIG.

The gate position control signal shown in FIG. 9A indicates control information output from the judgment control circuit 521.

The line integration result in FIG. 9B shows the integration result of the sample line at each gate position.

The offset period shown in FIG. 9C is provided during a period in which the noise level detecting gate pulse is originally stable with respect to the back porch in the horizontal blanking period of the input luminance signal and is not easily affected by ringing or the like. Have been.
That is, the offset period in the back porch is VT
If the type of the input luminance signal such as the R signal is different, the signal level is unstable at the rising edge of the waveform as shown by a plurality of solid lines in FIG. 8, so that the signal level is provided in a stable period to avoid this.

The offset value shown in FIG. 9D is an arbitrary fixed value. In order to prevent the judgment of the optimum position at the edge portion of the back porch due to a sudden factor at the time of determining the optimum position, An offset value is provided.

9 (e) is obtained by subtracting each offset value (FIG. 9 (d)) in the offset period of FIG. 9 (c) from the sample line integration result of FIG. 9 (b). Value.

The judgment result of FIG. 9 (f) is a result of judging the minimum value (MIN) among the judgment input values of FIG. 9 (e).

As described above, even when disturbance noise is generated at an intermediate position where the back porch is originally stable, the offset value is subtracted at the intermediate position so that the noise level detection gate is less affected by disturbance when determining the optimum position. In addition, the optimum position of the noise level detection gate can be stably detected.

FIG. 10 is a block diagram showing a noise level detecting circuit according to a fifth embodiment of the present invention.

In FIG. 10, a standard judgment circuit 730 is further provided in the configuration of FIG. Other configurations are the same as those in FIG. From the horizontal and vertical synchronization signals (HD, VD) input from the input terminals 112 and 111, the standard determination circuit 730 determines whether the input luminance signal is a standard signal or VTR special playback (for example, rewind playback, fast forward playback, etc.). It is determined whether the signal is a non-standard signal, and when the determination result changes from the non-standard signal to the standard signal, a control signal for re-determining the optimum position of the noise detection gate is given to the determination control circuit 521 again. It is for.

More specifically, the standard determination circuit 730 includes a means for generating a clear pulse based on the vertical synchronization signal (VD) of the input luminance signal, and an internal counter for counting the number of horizontal synchronization signals (HD) of the input luminance signal. , A holding means for holding the count value, and a comparator for comparing the held count value with a previously prepared value, so as to supply the clear pulse to a clear terminal of an internal counter.
The internal counter is cleared with a clear pulse to start counting the number of horizontal synchronization signals (HD), and the next vertical synchronization signal (V
The count value is held in the holding means at the same time as the internal counter is cleared by the clear pulse according to D). And
The held value is compared with a value prepared in advance by a comparator, and the count value is determined to be 262/263 or 312 /
When one of the sets 313 is detected alternately and continuously for a predetermined field period, it is determined to be the standard. Here, 262/263 indicates that the television system is M
In the case of the system, the count values 262 and 263 appear alternately for each field, and 312/313 indicates that the count values 312 and 313 alternate for each field when the television system is the B, G, or I system. It appears that it appears. Then, when the determination result shifts from the non-standard state to the standard state, the standard determination circuit 730 outputs a control signal for re-determining the optimum position of the noise level detection gate to the determination control circuit 521.

As an example of the transition from the non-standard state to the standard state, for example, the standard state (262/2) in which the first channel (1CH) is received by a television wave.
When switching from 63) to the VTR reproduction signal, the VTR reproduction is performed through the non-standard state (250/270) from the standard state (262/263) of 1CH until switching to the standard state (262/263) of the VTR reproduction signal. To the standard state (262/263). The special reproduction state such as the rewind reproduction and the fast forward reproduction of the VTR is a non-standard state, and the transition from the non-standard state of the special reproduction to the standard state (262/263) of the VTR reproduction is performed.

According to the configuration of FIG. 10, when the optimum position control of the noise level detection gate is performed in the same manner as in the embodiment of FIG. 7, the signal of the input terminal 101 is in a non-standard state as in the above-mentioned VTR special reproduction. However, when the state changes to the standard state and the signal becomes stable, non-standard → standard changes are detected and the optimal position of the noise level detection gate is re-determined. Without determining the optimum position.

Note that, instead of the standard decision circuit 730 in the embodiment of FIG.
When the value of the noise level detection signal detected by the holding circuit 107 greatly changes based on the integration result of the above, a control signal for re-determining the optimum position of the noise detection gate to the determination control circuit 521 is provided. A configuration in which a circuit (not shown) is provided may be employed.

According to the embodiment of the present invention described above,
Since the AC component extracted from the input luminance signal is rectified and converted into an absolute value and sample integration is performed during a predetermined period of the back porch during the horizontal blanking period, a video signal in which a copy guard signal is superimposed during the vertical blanking period or an input range. , It is possible to perform stable and highly accurate noise detection even for a digitally processed video signal in which is limited.

Further, there are the following advantages (1) to (3).

(1). The optimum position of the noise level detection gate can be automatically determined according to the state of the back porch during the horizontal blanking period of the input signal, and stable noise level detection is possible.

(2). At the time of determining the optimum position of the noise level detection gate, an offset value is given during a period in which noise can be detected stably, so that the determination is less likely to be affected by accidental disturbance.

(3). When it detects that the input signal has switched from non-standard to standard, by re-determining the optimal position of the noise level detection gate, a signal that the microcomputer in the ordinary video equipment cannot grasp the input state, For example, highly accurate noise level detection is possible for a VTR signal from an external input terminal.

In the above-described embodiment, the configuration is described in which an analog luminance signal is input, and a noise level is detected by an A / D converted and digitized signal.
The present invention is not limited to the case where noise level detection is performed on a digitized signal, and the A / D conversion circuit is eliminated, and the analog signal is not converted into an analog signal without being converted into an analog signal. , The noise level can be detected.

[0089]

As described above, according to the present invention, stable and highly accurate noise detection can be performed even for a video signal on which a copy guard signal is superimposed or a digitally processed video signal. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a noise level detection circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a gate pulse a in FIG.

FIG. 3 is a diagram illustrating a gate pulse b in FIG.

FIG. 4 is an explanatory diagram for explaining the operation of FIG. 1;

FIG. 5 is a block diagram of a noise level detection circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a noise level detection circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram of a noise level detection circuit according to a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram illustrating another embodiment of the operation of determining the optimum position of the noise level detection gate in FIG. 7;

FIG. 9 is a timing chart for explaining an optimum position determining operation of the noise level detection gate shown in FIG. 8;

FIG. 10 is a block diagram of a noise level detection circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101: input luminance signal 102: A / D conversion circuit 103: band-pass filter 104: full-wave rectifier circuit (absolute value circuit) 105: sample integration circuit 106: line integration circuit 107: holding circuit 108: noise level detection signal output terminal 111 Vertical synchronization signal 112 Horizontal synchronization signal 202 Field integration circuit 512 Detection control circuit 521 Determination control circuit 522 Delay selection circuit 523 Optimal position determination circuit 620 Microcomputer 730 Standard determination circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadashi Oguma 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E Co., Ltd. F-term (reference) 5C021 PA35 PA42 PA57 PA58 PA63 PA76 PA85 RB07 SA06 SA17 YA01

Claims (10)

[Claims] A circuit for extracting an AC component of a luminance signal and rectifying the AC component; a sample integration circuit for integrating a sample of the rectified signal in a predetermined period of a back porch during a horizontal blanking period; A noise level detection circuit, comprising: a line integration circuit that integrates the signal of the line integration circuit for a predetermined scanning line period; and a circuit that holds an integration signal of the line integration circuit. 2. A circuit for extracting an AC component of a luminance signal and rectifying the AC component; a sample integration circuit for performing sample integration of the rectified signal during a predetermined period of a back porch during a horizontal blanking period; A line integration circuit that integrates the signal of FIG. 2 for a predetermined scanning period, a field integration circuit that integrates the signal after line integration for a predetermined field period, and a circuit that holds an integration signal of the field integration circuit. Noise level detection circuit. 3. The noise level detection circuit according to claim 1, wherein said line integration circuit performs an integration operation during a video scanning period excluding a vertical blanking period. 4. An A / D conversion circuit for converting an analog luminance signal into a digital luminance signal at a stage preceding the circuit for extracting and rectifying the AC component, and performing a noise level detection operation with the digital luminance signal. Claim 1 characterized by the following:
4. The noise level detection circuit according to any one of Items 3 to 3. 5. A circuit for extracting an AC component of a luminance signal and rectifying the AC component; a means for generating a gate pulse for noise level detection during a predetermined period of a back porch during a horizontal blanking period; A noise level detection circuit comprising: a sample integration circuit that samples and integrates a signal after component rectification during a period of the gate pulse; and a gate pulse control unit that controls the gate pulse to a different arbitrary position. 6. The noise level detection circuit according to claim 5, wherein said gate pulse control means controls a gate pulse position so that a noise detection value obtained by said sample integration circuit is minimized. 7. A noise level detection circuit for automatically determining an optimum position of a noise level detection gate pulse for an input luminance signal, wherein the input luminance signal is band-limited by a band-pass filter.
A circuit for converting the absolute value of the filter output to a limit within a certain level, a detection control circuit for controlling a plurality of noise integrating circuits based on the input horizontal and vertical synchronization signals, and a horizontal block of the luminance signal. A sample integration circuit for integrating N (N is a natural number) pixels by a noise level detection gate pulse finally obtained based on a control signal from the detection control circuit during a predetermined period of a back porch during a ranking period; A line integration circuit for integrating the output of the integration circuit by M (M is a natural number) lines according to a control signal from the detection control circuit; and (Natural number) Field integration circuit that performs field integration and a gate pulse for noise level detection in response to an instruction from the microcomputer A judgment control circuit for generating various control signals for judging an appropriate position; and a position of a noise level detection gate pulse used in the sample integrator circuit, based on a signal output from the judgment control circuit. And the noise level detection gate pulse are set arbitrarily n times (n: natural number) at different positions in the delay selection circuit, and based on the integration result of the sample line in each state. An optimum position determination circuit for determining an optimum noise level detection gate position, based on the determination result from the optimum position determination circuit, controlling the delay selection circuit to hold the noise level detection gate at the optimum position. A noise level detection circuit that enables stable noise level detection in a state where the noise level is reduced. 8. When the delay selection circuit makes the determination by changing the gate pulse position n (n: natural number) times, the optimum noise level detection gate position is determined in m (m: natural number) times near the center. 8. The noise level detecting circuit according to claim 7, further comprising a circuit for giving an offset value so that the optimum position of the noise level detecting gate can be stably detected regardless of disturbance. 9. A decision is made as to whether an input luminance signal is a standard signal or a non-standard signal such as in VTR special reproduction from the input horizontal and vertical synchronizing signals, and the decision result is changed from non-standard to standard. 8. The noise detecting apparatus according to claim 7, further comprising: a standard judgment circuit for generating a control signal for judging again the optimum position of the noise detection gate when the change has occurred, and supplying the control signal to the judgment control circuit. Level detection circuit. 10. A control signal for re-determining the optimum position of the noise detection gate when the value of the noise level detection result detected by the field integration circuit greatly changes and supplied to the determination control circuit. 8. The noise level detection circuit according to claim 7, further comprising a circuit that performs the operation.