JP2000174848A - Communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily obtain a high fault detection rate without the need for manual revision of physical connection by providing a switch that short-circuits/ opens line connectors between the line connector and a line I/F circuit and short-circuits the switch in the case of test. SOLUTION: A switch circuit 29 is provided between a data transfer line 21, that interconnects a line I/F circuit 17 and a line connector 25 and a data transfer line 22 that connects a line I/F circuit 18 and a line connector 26. Similarly, a switch circuit 30 is provided between a data transfer line 23 that connects a line I/F circuit 19 and a line connector 27 and a data transfer line 24 that connects a line I/F circuit 20 and a line connector 28. At normal operation, switch circuits 29, 30 are open under the control of a microprocessor 2, and the switch circuits 29, 30 are closed at test operation. The switch circuit 29 is closed by a SW control signal 31 from the microprocessor 2 to connect the data transfer lines 21, 22 thereby conducting a loopback test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device provided with a line return switch circuit for testing a line control unit.

[0002]

2. Description of the Related Art Conventionally, when data is communicated using a communication line, the line is connected to a communication connection device as the number of lines to be used increases, and the communication control device transfers the data to the line via the communication connection device. It is a transfer system.

In this system, when it is desired to test the operation of the communication control device, a method of performing the test using the system or a method of attaching a loopback circuit to the communication control device and performing the test has been adopted. In such cases, the former must make the entire system for testing, and the time dedicated to testing,
The equipment and the place are uneconomical, and the latter has a problem that the signal reception state with the adapter in the communication connection device is different from that of the system, so that an accurate test of the communication control device cannot be performed.

For this reason, Japanese Patent Laying-Open No. 57-30449 discloses that a line adapter and a loopback circuit are added to a line control device to perform a self-loopback test of the line control device without passing through a line connection device. Has been described. In this conventional example, a line adapter and a loopback circuit are required, a test of a line close to the actual operation is required, and further capital investment for the test needs to be reduced.

[0005] Also, JP-A-2-25141 discloses that
Communication that controls transmission / reception of communication performed via the operation line and diagnoses a communication control device having a self-diagnosis function by internal loopback diagnosis using a loopback path inside the device and loopback diagnosis using a loopback path outside the device. In the control diagnosis method, the internal loopback diagnosis and the external loopback diagnosis are characterized in that the communication control device is physically separated from the operation line, and means for executing the internal loopback diagnosis and the external loopback diagnosis exclusively from each other is provided. This conventional example also requires a folded connector for external folded diagnosis, and there is a need to further improve the manpower and reliability.

Here, a block diagram showing an example of the configuration of a conventional large-scale communication control unit will be described with reference to FIG.

In FIG. 15, an EISA (Extended Industry Standard Architectur), which is an I / O bus of a server, is used.
e: 32-bit expansion bus for personal computers and PCI (Periphe
ralComponent Interconnect: I / O bus for personal computer)
A bus converter circuit 1 is provided between the host bus 3 and the MPU bus 5. The bus converter circuit 1, the local memory 4, the microprocessor 2, and the line control circuits 15 and 16 are connected to each other via the MPU bus 5. Is done. The line control circuit 15 includes line I / F circuits 17 and 18,
Line I / F circuits 19 and 20 are connected to the line control circuit 16, and they are respectively data transfer paths 21, 22 and 2.
Line connectors 25, 26, 27,
28.

The communication control unit is a unit for transmitting and receiving data to and from an upper bus 3 such as a server and a line side connector.
Communication is controlled between two communication stations of a client and a server by being connected to a plurality of communication lines. Line control system is MPU2
In accordance with the above program, data is controlled between the line control circuits 15, 16 and the MPU bus 5 by matching with the bus converter circuit 1, and the upper bus 3 and the line control circuits 15, 1 are controlled.
6 is controlled via the MPU bus 5.
The MPU 2 issues a control instruction to the line control circuits 15 and 16 according to a communication control program stored in the local memory 4 and controls data transmitted and received between the line control circuits 15 and 16 and the upper bus 3.

Referring to FIG. 16, a folding test in the conventional configuration shown in FIG. 15 will be described. In the loopback test using the communication control unit configured as shown in FIG.
Since there is no mechanism for directly connecting between the / F circuits 17 and 18 and between the line I / F circuits 19 and 20, data cannot be looped back on the line side by the line control circuits 15 and 16. When performing the loopback test, the line control circuit 15
The communication data is looped back at and 16. Therefore, even if the loopback test is normally completed, the diagnosis is performed only for the MPUs connected by the thick arrows in FIG.
The parts connected to the bus 5, namely the bus converter circuit 1, the microprocessor MPU2, the local memory 4,
Since it is limited to the line control circuits 15 and 16, it is only possible to determine whether or not the upper bus 3 to the line control circuits 15 and 16 are functioning normally.
Failures of 7, 18, 19, and 20 (shaded portions in FIG. 16) cannot be detected.

In addition, except for the upper bus shown in FIG.
As shown in Fig. 7, CCU (Communication Control Uni
t) Usually, the parallel terminals 66 of the CCU card 60 are inserted into the input / output bus connector of the upper bus of the server and are operated. Also, C
The CU card 60 is connected to the connector terminals CH0 to CH3 with the CCU.
The connectors 61 of the lines # 0 to # 3 of the cable 67 are inserted and connected, and the line between the connector 62 and the external client is connected to transmit and receive data and control data.

When a loopback circuit is configured to include the line I / F circuits 17 to 20, a communication control unit (CCU)
As shown in the configuration of above, with human intervention,
U) The connector or modem 65 is connected to the connector 64 of the CCU cable 68, and the connector 63 of the CCU cable 68 and the connectors 62 of the lines # 0 to # 3,
Connectors 61 and C of lines # 0 to # 3 by cable 67
A plurality of connections were required, such as the terminals CH0 to CH3 of the CU card 60. Also, CCU card 60
Transmits and receives data to and from the host computer by inserting the parallel terminal 66 into a bus connector arranged on an upper bus of the host computer. A loopback test can be performed under this connection. With this configuration and connection, the data transfer paths 21, 22, 23, 24
, It is possible to detect a failure of the line I / F circuits 17, 18, 19, 20.

[0012]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a communication system including a line I / F circuit without attaching an external line cable or a loopback connector when performing a loopback test inside a communication control device. An object of the present invention is to easily obtain a high fault detection rate without manually changing a physical connection by detecting a fault inside a control device.

Another object of the present invention is to enable a test to be performed with various connection patterns of line I / F circuits without manual intervention.

[0014]

According to the present invention, there is provided a communication control apparatus for controlling data communication through a communication line, wherein a plurality of line-side connectors connected to a plurality of lines and a plurality of interfaces serving as interfaces connected to the line-side connectors are provided. Line I / F
A circuit, line control means for transmitting and receiving data to and from a higher-level bus for transmission / reception to / from the line I / F circuit; A switch for short-circuit / open is provided.
The switch is short-circuited during the test.

According to the present invention, a communication control device for controlling data communication through a communication line includes a line-side connector connected to a transmission / reception line, and a transmission unit and a reception unit serving as interfaces connected to the line-side connector. A line I / F circuit, line control means for transmitting and receiving data to and from the transmission / reception to / from the line I / F circuit to an upper bus, and a short circuit / open circuit between the transmission unit and the reception unit of the line I / F circuit. And a short circuit during the test by the control means.

The present invention also provides a gate array for line control in a case where a return test is performed in the same card without using a line cable and a return connector (or a modem) in a card type communication control unit. And a switching circuit for performing a test including an interface circuit between line connectors connected to the line connector.

The present invention will be described with reference to the drawings. In FIG. 1, the microprocessor 2, the local memory 4, and the line control circuit 6 are connected to the MPU bus 5.

A microprocessor (MPU) 2 controls a line control circuit 6 according to a communication control program stored in a local memory 4. The line control circuit 6 controlled by the microprocessor 2 has a line I
By controlling the / F circuits 7 and 8, communication data is transmitted and received to and from the outside.

The line interface (I / F) circuit 7
It is connected to the line side connector 12 via the data transfer path 10. The line I / F circuit 8 is connected to the line side connector 13 via the data transfer path 11. The line side connectors 12 and 13 are connected to a line cable.

The switch (SW) circuit 9 is connected to the data transfer path 1
It is connected between 0 and 11 and turns on or off the SW circuit 9 via a switch (SW) control signal 14 output from the microprocessor 2 to the SW circuit 9 according to an instruction from the microprocessor 2. This SW circuit 9
Is in an OFF state during a normal operation, but is switched to an ON state in response to an instruction from the microprocessor 2 during a test operation, whereby the line I / F circuit 7 and the line I / F
The F circuit 8 is physically connected, whereby data is transmitted and received between the line I / F circuit 7 and the line I / F circuit 8, and the line via the line I / F circuit 7 and the line I / F circuit 8 A loopback test with a line via the terminal can be executed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

[First Embodiment] (Configuration of this Embodiment) FIG. 1 is a functional block diagram showing a first embodiment of the present invention. The line return switch circuit according to the present embodiment is stored in a card form in the communication control device and performs a return test in the card. The bus converter circuit 1, the microprocessor 2, the local memory 4, the MPU bus 5, the line It comprises a control circuit 6, line I / F circuits 7, 8, a switch circuit 9, data transfer paths 10, 11, and line side connectors 12, 13.

In the communication control apparatus including the line return switch circuit, the bus converter circuit 1, the microprocessor 2, the local memory 4, and the line control circuit 6 are connected to the MPU bus 5, respectively. 3, a bus converter circuit 1 is provided. Each component in FIG. 1 is a card type CCU.
The card is inserted into an I / O bus slot in the server while being attached to and stored in a card. Also, this C
The CU card is provided with a plurality of line-side connectors 12 and 13 shown in FIG. 1 and is connected to a line such as an external client.

The line I / F circuit 7 is connected to the line side connector 12 by the data transfer path 10 and the line I / F circuit 8
Are connected to the line side connector 13 by the data transfer path 11, respectively. Further, a switch circuit 9 is provided between the data transfer paths 10 and 11. The line I / F circuits 7 and 8 have a reception I / F circuit and a transmission I / F circuit, respectively, and receive data and transmission signals from the line side connectors 12 and 13 in a data structure to the line control circuit 6. It has functions such as conversion and line impedance matching.

The bus converter circuit 1 comprises an MPU bus 5 to which the microprocessor 2 is connected and an upper bus 3
(EISA (Extended Industry Standard Archistectu
re: One of the 32-bit expansion buses for personal computers) Bus, PC
I (Peripheral Component Interconnect) bus etc.)
Interface with the

The microprocessor 2 is connected to the bus converter circuit 1, the line control circuit 6, and the local memory 4 via the MPU bus 5, and performs various communication control procedures. Communication is performed via the line control circuit 6 according to the program data.

The line control circuit 6 is connected to the line I / F circuits 7 and 8, and controls data transmission and reception of these I / F circuits 7 and 8.

The line I / F circuit 7 is connected to the line side connector 12 via the data transfer path 10 and the line I / F circuit 8 is connected to the line side connector 13 via the data transfer path 11. In order to perform signal output and input to and from a line, signal electrical conversion and the like are performed according to recommendations of the ITU-TS (Telecommunication Standardization Center) and the like.

The switch (SW) circuit 9 is connected to the data transfer path 1
It is provided between 0 and 11, and is connected to the microprocessor 2 via the SW control signal 14. The switch circuit 9 is turned on or off by an instruction from the microprocessor 2 via the SW control signal 14. The switch circuit 9 is in an OFF state during a normal operation, but transitions to an ON state in response to an instruction from the microprocessor 2 during a loopback test operation, whereby the line I / F circuit 7 is turned on.
And the signal line between 8 is connected. This enables data communication between the line I / F circuits 7 and 8. In the OFF state, the state between the data transfer paths 10 and 11 is the same as the disconnected state. The switch (SW) circuit 9 includes a plurality of lines formed of, for example, MOSFETs and relays.

A line cable of an external transmission line is connected to the line side connectors 12 and 13. For example, a printer, a modem, a router, a hard disk, and the like are connected using a LAN Ethernet cable.

FIG. 2 shows an example of connection of signal lines in the RS-232-C system in the case of performing a loopback test between different line I / F circuits using the switch circuit 9 in the configuration shown in FIG. The switch circuit 9 shown in FIG. 2 is in an OFF state during a normal operation, but as shown in FIG. 2, shows a connection state of each signal line when the switch circuit 9 changes to an ON state in accordance with an instruction from the microprocessor 2. This figure 2
When the switch circuit 9 transits to the ON state as shown in (1), data communication can be performed between the line I / F circuits 7 and 8.

A list of signal line names, pin numbers and names of the RS-232-C system is also shown in FIG. RS-23
2-C is a normal data terminal device (DTE: Data Termina).
l Equipment) and line termination equipment (DCE: Data Circui)
A standard that defines the exchange of signals with t-terminating equipment. DTE is equivalent to a personal computer and DCE is equivalent to a modem. According to the RS-232-C standard, the transmitting DTE turns on the ER and instructs the transmitting DCE to connect a line as a serial interface using 9 pins out of 25 pins. The transmitting DCE receives this, connects to the line, and returns the DR to the transmitting DTE. Next, the transmitting DTE turns on the RS and requests the transmitting DCE to start transmission. The transmitting DCE receiving the RS puts out a carrier for sending transmission data to the line, and returns CS to the transmitting DCE. At this stage, the transmitting DTE can transfer data to the transmitting DCE using SD.
On the other hand, the receiving DCE that has detected the carrier transmitted by the transmitting DCE turns on the CD and notifies the receiving DTE.
The receiving DTE that has received the CD enters a receiving state and receives data through the RD. According to the RS-232-C standard, when connecting between a personal computer and a modem,
Use cables. When connecting personal computers, mutual communication is made possible by using a cross cable to avoid collision between output signals. Therefore, in this embodiment, the latter cross cable is used.

(Explanation of Operation of the Present Embodiment) Next, FIG.
The operation of the communication control unit will be described with reference to FIG.

The bus converter circuit 1 is provided between the upper bus 3 and the MPU bus 5 and includes a microprocessor 2
The transfer control is performed when the data from the upper bus 3 is stored in the local memory 4 or when the data in the local memory 4 is transferred to the upper bus 3 by the DMA read and DMA write.

The microprocessor 2 executes a communication control program stored in the local memory 4 connected by the MPU bus 5, and controls the line control circuit 6 according to a communication procedure. The switch (SW) control signal 14 is used to control the ON / OFF operation of a switch circuit 9 described later.

The local memory 4 is a microprocessor 2
Stores a communication control program to be executed, and also serves as a buffer for buffering transmission / reception data to / from a communication line. Data transmitted to the communication line is stored in the local memory 4 via the upper bus 3, the bus converter circuit 1, and the MPU bus 5, and transmitted to the line I / F circuits 7, 8 under the control of the microprocessor 2. Data received from the communication line is received by the line I / F circuits 7 and 8 and stored in the local memory 4 via the MPU bus 5. Further, under the control of the microprocessor 2, the data is transferred to the upper bus 3 via the bus converter circuit 1.

The line control circuit 6 controls transmission and reception of data using the line I / F circuits 7 and 8 under the control of the microprocessor 2. Also, the transmission data stored in the local memory 4 is fetched and the line I / F circuit 7 or 8 is read.
To transmit the data to the local memory 4, and to store the data received from the line I / F circuit 7 or 8 into the local memory 4.

The line I / F circuits 7 and 8 are connected to the line control circuit 6 to transmit and receive data under the control of the line control circuit 6 and convert transfer data into a signal suitable for the communication line. Converts electrically.

The switch circuit 9 is provided between the data transfer paths 10 and 11, and is in an OFF state during normal operation, that is, the line between the data transfer paths 10 and 11 is in a physically isolated state. The data transfer paths 10 and 11 are physically connected by making a transition to an ON state in accordance with an instruction from the microprocessor 2 during the test operation.

A case in which a loopback test is performed between different lines in the same card will be described with reference to FIGS.

FIGS. 4 and 5 are block diagrams basically showing the same configuration as the configuration shown in FIG.
Two line I / F circuits, two line side connectors, two data transfer paths, one switch circuit, and one SW control signal
This shows a case where two sets are provided.

In FIG. 4, a switch circuit 29 includes a data transfer path 21 connecting the line I / F circuit 17 and the line connector 25, a line I / F circuit 18 and a line connector 26.
And a data transfer path 22 connecting the Similarly, switch circuit 30 is provided between data transfer path 23 connecting line I / F circuit 19 and line connector 27 and data transfer path 24 connecting line I / F circuit 20 and line connector 28. Have been. The switch circuits 29 and 30 are off during normal operation, and are turned off under the control of the microprocessor 2 during test operation.
Transition to the N state.

Next, the operation of switch circuits 29 and 30 will be described with reference to FIG. The data transfer paths 21 and 22 are physically connected by closing the switch circuit 29 from the microprocessor 2 via the SW control signal 31, that is, turning on the switch circuit 29. The state at this time is shown in the upper part of FIG. By performing the loopback test during this time, data is transmitted and received between the line I / F circuit 17 and the line I / F circuit 18 via the data transfer paths 21 and 22.

In this configuration, both full-duplex communication and half-duplex communication can be tested. For example, the line I / F circuit 17 and the line I / F circuit 18 can be tested by the instruction of the line control circuit 15 at each time. By switching one of the circuits for reception and the other for transmission, a test for performing half-duplex communication or full-duplex communication between the line I / F circuits 17 and 18 becomes possible.

Similarly, by closing the switch circuit 30 from the microprocessor 2 via the SW control signal 32, that is, turning on, the data transfer paths 23 and 24 are physically connected. The state at this time is shown in the lower part of FIG. By performing the loopback test during this time, data is transmitted and received between the line I / F circuit 19 and the line I / F circuit 20 through the data transfer paths 23 and 24.

In this configuration, both full-duplex communication and half-duplex communication can be tested. For example, the line I / F circuit 19 and the line I / F circuit 20 can be tested by the instruction of the line control circuit 16 at each time. By switching one of the circuits to the receiving circuit and the other to the transmitting circuit, a test for performing full-duplex or half-duplex data communication between the line I / F circuits 19 and 20 becomes possible.

By the operation of the data communication control device according to the present configuration, a test of a line control circuit and a line I / F connecting an upper bus and a line is performed through a line switch under a program control by a microcomputer without manual operation. Easy.

[Second Embodiment] In the configuration of FIG. 4 shown in the first embodiment, the switch circuit 29 is turned on.
When the switch circuit 30 transitions to the ON state, only the connection between the data transfer paths 23 and 24 is performed. , If you actually get an error in the loopback test,
It cannot be finally determined which line I / F circuit including the data transfer path has failed.

A configuration is conceivable in which a switch circuit is provided so that the data transfer paths can be connected in several patterns so as to be able to separate them. This example will be described with reference to FIG.

The switch circuit 33 provided in FIG.
A switch having two terminals a, b, and c, and a data transfer path 2
The data transfer path 21 is connected to the terminal a, the terminal 23 is connected to the terminal b, and the terminal 22 is connected to the terminal c. SW controlled by microprocessor 2
The ON / OFF operation of the SW circuit 33 is performed via the control signal 31.

The switch circuit 34 has three terminals d,
switches having data transfer paths 22, 23, 2
4, the data transfer path 23 is connected to the terminal d,
2 is connected to the terminal e, and 24 is connected to the terminal f. SW under control of microprocessor (MPU) 2
The ON / OFF operation of the SW circuit 34 is performed via the control signal 32. These switch circuits can take one state as OFF and three states to connect two of the three terminals as ON. For example, according to the 2-bit signal of the SW control signal 32, the connection pattern between the data transfer paths in the SW circuit 33 when in the ON state is as follows.
Connection between terminals a and b, connection between terminals b and c, terminal c and a
And three types of connection.

The case where the switch circuits 33 and 34 are turned ON will be specifically described with reference to FIGS. 7, 8, and 9. FIG. In these figures, a portion shown by a broken line indicates a path that is not connected (data communication is not performed), and a portion shown by a solid line is connected by a switch (data communication is performed). Shows the route.

The connection pattern shown in FIG. 7 is such that the switch circuit 33 connects the terminal a and the terminal b so that the line I / F circuit 1
7 and 19 are physically connected via data transfer paths 21 and 23, and switch I / F circuits 18 and 20 are physically connected via data transfer paths 22 and 24 by switch circuit 34 connecting terminals e and f. This shows the case where the connection is made. Thus, the line I / F circuits 17, 1
9 and a loopback test between the line I / F circuits 18 and 20.

In the connection pattern of FIG. 8, when the switch circuit 33 connects the terminals a and c, the line I / F circuits 17 and 18 are physically connected through the data transfer paths 21 and 22, and the switch circuit 34 is connected. Terminal d and terminal f
By connecting the line I / F circuits 19 and 20
Are physically connected through the data transfer paths 23 and 24. Thus, the line I / F circuit 1
A loopback test can be performed between the circuits 7 and 18 and the line I / F circuits 19 and 20.

In the connection pattern shown in FIG. 9, the switch circuit 33 connects the terminals b and c, and the switch circuit 34 connects the terminals d and e, so that the line I / F circuits 18 and 19 connect the data transfer paths 22 and 23 shows a case where they are physically connected. This enables a loopback test between the line I / F circuits 18 and 19.

As described above, by changing the connection pattern between the data transfer paths using the switch circuit, a test up to the conventional line control circuit and each line I / F circuit or data transfer path that cannot be specified by the configuration of FIG. Can be isolated.

The case where the loopback test is performed between two sets of line I / F circuits using the basic configuration shown in FIG. 1 and the configurations shown in FIGS. 4 to 9 has been described.

[Third Embodiment] Further, as a third embodiment, even if the communication control unit is provided with only one line I / F circuit by the configuration as shown in FIG. Test is possible. A transmission data transfer path 47 is connected to the line connector 48 from the line I / F circuit 44, and a reception data transfer path 46 is connected to the line connector 48 between the data transfer paths 46 and 47. SW circuit 4
5 are provided.

At the time of the test operation, the data transfer paths 46 and 47 are physically connected by the transition of the SW circuit 45 to the ON state in accordance with the instruction of the microprocessor 2, so that the line I / F circuit 44 By transmitting and receiving data, a loopback test on the same line becomes possible.

However, when the loopback test is performed between the two sets of line I / F circuits in FIG. 1, it is possible to perform the loopback test in either half-duplex communication or full-duplex communication. In the configuration of No. 10, since transmission and reception must be performed simultaneously on the same line, a test cannot be performed unless full-duplex communication is possible.

As in the case of the loopback test between different line I / F circuits, the same line I / F
For the case of performing a loopback test in a circuit, RS-2
FIG. 11 shows an example of the connection in the 32-C system. FIG. 11 shows a connection state of each signal when the SW circuit 45 is in an OFF state during a normal operation, but transitions to an ON state in accordance with an instruction from the microprocessor 2.
By switching the switch circuit 45 to the ON state as shown in FIG. 11, a test of full-duplex communication using the same line I / F circuit in the line I / F circuit 44 through the data transfer paths 46 and 47 is performed. It is possible to do.

[Fourth Embodiment] In the configuration described so far, the signal for controlling the switch circuit connecting the line I / F circuits is output from the microprocessor.
As a fourth embodiment, a configuration in which this is output from the line control circuit can be considered. The configuration in this case is shown in FIG.
2, FIG. 13 and FIG.

FIG. 12 is a modification of the configuration of FIG. 4 in which the SW control signal output from the microprocessor 2 is output from the line control circuits 15 and 16. In FIG. 12, the SW circuit 37 is connected to the data transfer path 2
1 and 22, which are connected to the line control circuit 15 via the SW control signal 35, and perform an ON / OFF operation according to the control of the line control circuit 15. The SW circuit 38 is provided between the data transfer paths 23 and 24, is connected to the line control circuit 16 via the SW control signal 36, and performs an ON / OFF operation according to the control of the line control circuit 16.

FIG. 13 is a modification of the configuration of FIG. 6 in which the SW control signal output from the microprocessor 2 is output from the line control circuits 15 and 16. In FIG. 13, the SW circuit 41 is connected to the data transfer path 2
It is provided between 1, 2, and 23, is connected to the line control circuit 15 via the SW control signal 39, and performs ON / OFF operation according to the control of the line control circuit 15. The SW circuit 42 is provided between the data transfer paths 22, 23, and 24, is connected to the line control circuit 16 via the SW control signal 40, and performs an ON / OFF operation according to the control of the line control circuit 16.

FIG. 14 is a modification of the configuration of FIG. 10 in which the SW control signal output from the microprocessor 2 is output from the line control circuit 50. 14, a SW circuit 45 is provided between data transfer paths 46 and 47, is connected to a line control circuit 50 via a SW control signal 51, and performs an ON / OFF operation under the control of the line control circuit 50. .

[0066]

As described above, according to the present invention,
In the conventional loopback test inside the communication control device, it was not possible to detect a fault in the line I / F circuit inside the communication control device. However, by using the switching circuit according to the present invention, these line I / F circuits can be detected. Since it is possible to perform a test in a comprehensive range, it is possible to detect a fault in the line I / F circuit. Therefore, when performing a loopback test inside the communication control device, attach an external line cable or loopback connector. Without detecting a fault inside the communication control device including the line I / F circuit, a high fault detection rate can be easily obtained without manually changing the physical connection.

Further, by controlling the switching circuit on the output side of the line I / F circuit by using a microprocessor or a line control circuit, the connection pattern of the line I / F circuit is changed by using the output signal from these circuits. Since it becomes possible, it becomes possible to perform tests with various connection patterns of the line I / F circuits without manual intervention.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of connection between a switch circuit and a line I / F circuit according to the present invention.

FIG. 3 is a diagram showing a list of RS-232-C pin arrangements;

FIG. 4 is a block diagram showing an embodiment of the present invention.

FIG. 5 is a diagram showing the operation principle of the present invention.

FIG. 6 is a functional block diagram showing another embodiment of the present invention.

FIG. 7 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 8 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 9 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 10 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 11 is a diagram showing an example of connection between a switch circuit and a line I / F circuit according to the present invention.

FIG. 12 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 13 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 14 is a functional block diagram showing an operation principle according to another embodiment of the present invention.

FIG. 15 is a functional block diagram showing one form of a conventional communication control unit.

FIG. 16 is a functional block diagram showing one form of a conventional communication control unit.

FIG. 17 is a diagram illustrating a form of a connector / modem loopback test.

[Explanation of symbols]

1 Bus converter circuit 2 Microprocessor (MPU) 3 Upper bus 4 Local memory 5 MPU bus 6,15,16,50 Line control circuit 7,8,17-20,44 Line I / F circuit 9,29,30,33 , 34,37,38,41,4
2,45 SW circuit 10,11,21-24,46,47 Data transfer path 12,13,25-28,48 Line side connector 14 SW control signal 31,32,35,36,39,40 SW control signal

Claims (5)

[Claims] 1. A communication control apparatus for controlling data communication through a communication line, comprising: a line-side connector connected to a plurality of lines; a plurality of line I / F circuits serving as interfaces connected to the line-side connector; Line control means for transmitting and receiving data to and from a higher-level bus for transmission / reception to / from a line I / F circuit;
A communication control device, comprising: a switch for opening the switch; and short-circuiting the switch during a test. 2. The communication control device according to claim 1, further comprising: a bus converter circuit connected to the upper bus for converting a data structure between the transmitting and receiving devices; a local memory storing a control program; A communication control device, comprising: a microprocessor for controlling the bus converter circuit, the line control means, and the switch according to a control program. 3. The communication control device according to claim 2, wherein the switch is provided between the line-side connector and a plurality of the line-side connectors, and the switch is sequentially switched according to an instruction of the line control means to switch the line. A communication control device for performing a test between a side connector and the line side connector. 4. A communication controller for controlling data communication through a communication line, a line I / F having a line-side connector connected to a transmission / reception line, and a transmission unit and a reception unit serving as an interface connected to the line-side connector. A circuit, line control means for transmitting and receiving data to and from a higher-level bus to and from the line I / F circuit, and a switch for short-circuiting / opening between the transmission unit and the reception unit of the line I / F circuit. A communication control device for short-circuiting the switch during a test by the line control means. 5. The communication control device according to claim 4, wherein said transmission / reception line transmits / receives data from a client, and said upper bus is inserted into a PCI bus slot by a PCI bus to transmit / receive data to / from a server. Wherein the line control means includes a microprocessor and a memory storing an operation procedure of the microprocessor, and the switch is turned on / off by a control signal from the microprocessor.