JP2000174723A - Communication control method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a circuit transmitting a multiplexed signal with the constitution of a small scale, to suppress delay at the time of transmitting the signal to be minimum and to transmit the multiplexed signal on a real time basis. SOLUTION: Input signals Si1-Si4 from respective lines are inputted to a dual port memory 1 and a decoding circuit 3 designates the writing address of data based on the count value of an address counter 2 starting counting. Thus, the respective input signals are simultaneously stored. A decoding circuit 4 designates an address based on the count value and gives the indication of the reading of data. The dual port memroy 1 receiving data outputs data of the respective input signals as output signals So1-So4. An output control circuit 5 outputs an output selection signal Sos selecting/designating any output signal based on the count value. An external output signal So obtained by time- divisionally multiplexing the input signals Si1-Si4 is outputted from a selection circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a communication control technique using a variable TSI (Time Slot Interchange) system for sequentially converting signals of a plurality of lines input at the same speed in a predetermined unit and serially transferring the signals.

[0002]

2. Description of the Related Art In recent years, with the development of multimedia, high-speed multiplexing in communication has been required. In such a situation, the technology of multiplexing signals input from a large number of lines and transmitting the signals in real time is becoming more and more important, but a circuit for multiplexing such signals has a larger circuit size. It is necessary to reduce the size.

[0003] In a conventional communication control device in which many signals of the same speed are input simultaneously in a communication network and output signals are serially transmitted in a time-division manner, a dual port memory is operated while delaying the mutual time of each signal on the input side. I was going to write. Then, after a certain period of time required for writing the simultaneously input signals elapses, an address counter for instructing an output signal is operated, and the count value is decoded and converted to be provided to the dual port memory, thereby performing time division. A multiplexed serial signal was output.

FIG. 3 shows a typical circuit for performing time-division signal permutation conversion in such a conventional communication control apparatus.
The operation time chart is shown in FIG. In these figures, Si1 to Si4 are input signals input from the respective lines at the same timing and at the same speed, and "A" and "A" in FIG.
“A ′”, “B”,..., “D ′” correspond to one unit of signal (signal included in one time slot) in multiplexing. In the circuit of FIG. 3, the input signal Si1 is directly input to the selection circuit 10, and the input signals Si2, Si3, Si4
Are delayed by a predetermined time via delay circuits 11, 12, and 13, respectively, and input to the selection circuit 10. Thus, the input signals Si2 to Si4 are input to the selection circuit 10 as the input signals Si2 'to Si4' delayed as shown in the fifth to seventh stages in FIG.

On the other hand, the address counter 14 starts counting from the time when the input signal is input, and supplies the output count value to the input control circuit 15 and the decode circuit 16 as a write address counter signal Swac (FIG. 1). 4 8th stage). This write address counter signal S
Based on wac, the input control circuit 15 outputs an input selection signal Sis for selecting which input signal is to be written to the dual port memory 17, and the selection circuit 10 outputs the input signal specified by the input selection signal Sis to the dual port memory 17. .
In the input selection signal Sis at the tenth stage in FIG.
"(A)", "i1 (A ')", ..., "i4 (D')" are "A" of the input signal Si1, "A '" of Si1, ..., "D'" of Si4, respectively.
Is designated, and the selection circuit 1
From "0", "A" of the input signal Si1 to "D '" of Si4 are sequentially output as the input signal Si.

[0006] The decode circuit 16 is provided with a dual port memory 17 based on a write address counter signal Swac.
A write address signal Swa for designating a write address
Enter This write address signal Swa corresponds to the ninth in FIG.
As shown in the row, the designated address is gradually incremented as the address counter 14 counts. Thereby, the selection circuit 10
From the input signals Si (“A” of Si1 to Si4)
"D '") are sequentially stored at successive addresses.

The signal output from the dual port memory 17 is controlled by the read address signal Sra output from the decode circuit 18 based on the read address counter signal Srac from the address counter 18. Here, the read address counter signal Srac is a signal that is counted up in the same manner as the write address counter signal Swac, but has a constant value so that reading from the dual port memory 17 does not overtake the above writing. The supply starts with a delay (see the eleventh stage in FIG. 4). or,
The read address signal Sra is a signal for designating a read address in the dual port memory 17, and sequentially designates a predetermined address as the read address counter signal Srac counts up. This addressing is performed so that the input signal of each line is sequentially read out from the dual port memory 17 for each multiplexing unit. Since the input signals of four lines are assumed here, the twelfth stage in FIG. It becomes as shown in.

As described above, the read address signal Sra from the decode circuit 18 causes the dual port memory 1
The signal is read out in the order different from the writing order to the above-described order (see the dashed arrows from the 13th stage and the 10th stage to the same stage in FIG. 4). As a result, an output signal So obtained by time-division multiplexing the input signals Si1 to Si4 is output from the dual port memory 17.

[0009]

In the above-mentioned conventional communication control device, the input signal is converted into serial at the time of input by delaying the signal in a predetermined form, and the read address sequence on the output side is changed. By changing the order, time-division order conversion is performed. For this reason, it is necessary to provide a delay circuit for an input signal from each line other than the first line, and there is a problem that the circuit scale becomes large. In particular, as the number of signal input lines increases, the number of necessary delay circuits also increases in proportion to the increase. Therefore, this problem becomes a major obstacle in multiplexing signals input from many lines.

Further, in the above-described circuit, since each input signal is delayed by each delay circuit and writing to the dual port memory is performed in the serial data format in the line order, reading from the dual port memory is performed. The signal output must be started with a certain delay so as not to overtake the signal. That is, the conventional circuit requires a time to accumulate data in the dual port memory, so that it is not possible to transmit a multiplexed signal in real time, and there is a problem that a certain delay occurs.

The present invention has been made in view of such circumstances, and enables a circuit for transmitting a multiplexed signal to be realized with a small-scale configuration and minimizes a delay in transmitting the signal. It is an object of the present invention to provide a communication control technique capable of transmitting a multiplexed signal in real time.

[0012]

According to the first aspect of the present invention,
A signal from a plurality of lines is simultaneously stored in a predetermined storage area for each predetermined unit signal supplied simultaneously, and the predetermined unit signals of the respective lines stored simultaneously from the predetermined storage area are simultaneously read out, and the readout of them is continued. The predetermined unit signals are output in a fixed order.

According to a second aspect of the present invention, there is provided a storage means for simultaneously storing signals from a plurality of lines in a predetermined storage area for each predetermined unit signal supplied simultaneously, and each of the plurality of signals simultaneously stored from the predetermined storage area. Reading means for simultaneously reading the predetermined unit signal of the line and holding the read state; and the predetermined unit of each line being read while the state is held by the reading means. Output means for outputting signals in a predetermined order.

According to a third aspect of the present invention, in the communication control apparatus according to the second aspect, the storage means includes: an address designating means for designating an address for each of the predetermined unit signals from the plurality of lines; A dual port memory for simultaneously writing the predetermined unit signal to an address designated by the address designating means, wherein the reading means comprises:
Specifying an address of the line where the predetermined unit signal is written to the dual port memory and outputting a signal of the address, and maintaining the state by continuously specifying the address for a certain period of time. Features.

According to a fourth aspect of the present invention, in the communication control apparatus of the second aspect, there is provided an address counter which starts counting from a timing at which the signal is input, and the storage means stores the signal input simultaneously. And a decode circuit for writing a signal input from the address counter to the dual port memory, and the read means converts the signal input from the address counter to the dual port memory. A decoding circuit for reading from memory,
The output means includes a selection circuit for selecting a signal read from the dual-port memory, and an output control circuit for controlling the selection circuit, and changes the order of simultaneously input signals in a time-division manner. And

According to a fifth aspect of the present invention, in the communication control apparatus according to the fourth aspect, a signal output is processed in real time with respect to the signal input.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a communication control device (a time-division signal permutation conversion circuit using a variable TSI method) according to an embodiment of the present invention. In the drawings, the signals corresponding to the respective signals in FIGS. 3 and 4 are denoted by the same reference numerals, but the form of each signal is different from that described above. I do.

In FIG. 1, reference numeral 1 denotes the storage of the data of the input signals Si1 to Si4 at the address specified by the write address signal Swa, and the data of the address specified by the read address signal Sra as the output signals So1 to So4. It is a dual port memory to output. Here, the input signals Si1 to S
i4 is an input signal input from each line at the same timing and at the same speed, and is simultaneously supplied to the dual port memory 1 in parallel as it is as shown. The write address signal Swa and the read address signal Sra are signals for designating an address in the dual port memory 1 and instructing data writing and reading, respectively. , 4 output.

The address counter 2 receives input signals Si1 to S1.
The count-up is started at a timing synchronized with the input signal speed (a timing at which a signal included in one time slot in multiplexing is supplied) from the time when i4 is input, and the output count value is decoded by the decoding circuit 3 or 4 and output control circuit 5. Here, the address counter 2 outputs the output count value to the decode circuit 3 as a write address counter signal Swac from the start to the end of input of a series of continuous input signals supplied in parallel from each line, From the end of input to the end of serial output of all input signals in units of time slots, the output count value is read from the address counter signal Srac.
To the decoding circuit 4 and the output control circuit 5.

The decode circuit 3 outputs a write address signal Swa based on the write address counter signal Swac, and instructs the dual port memory 1 to write the input signals Si1 to Si4 at predetermined addresses. The address specified by the decode circuit 3 is the input signal S
An address corresponding to a storage area having a capacity capable of storing one time slot of the parallel data i1 to Si4 is set, and the dual port memory 1 receiving the data simultaneously writes the data of each input signal to the designated address. Further, the decode circuit 3 increments the designated address with the count-up of the write address counter signal Swac.

The decode circuit 4 outputs a read address signal Sra based on the read address counter signal Srac, and instructs the dual port memory 1 to read and output data stored at a predetermined address. The address specified by the decoding circuit 4 is
An address corresponding to a storage area in which parallel data of the input signals Si1 to Si4 is stored for one time slot,
The dual port memory 1 outputs the parallel data stored at the specified address as output signals So1 to So4. In this case, the dual port memory 1 outputs signals in a data correspondence such that the data of the input signals Si1, Si2, Si3, and Si4 are output signals So1, So2, So3, and So4, respectively. The decode circuit 4 increments the designated address of the read address signal Sra when the count value of the read address counter signal Srac increases by the number of lines.

The output control circuit 5 outputs an output selection signal Sos to the selection circuit 6 based on the read address counter signal Srac. Here, the output selection signal Sos is a signal for instructing to select any one of the output signals So1 to So4 from the dual port memory 1 and to output the same to the outside. The output control circuit 5 outputs the read address counter signal Srac Output signals So1, So2, So3, So4
Are sequentially selected, and when the count-up corresponding to the number of lines is completed, an output selection signal for sequentially selecting again from the output signal So1 is output.

The selection circuit 6 outputs one of the output signals So1 to So4 to the external output signal So according to the output selection signal Sos.
Output as

Next, the operation of the above configuration (contents of the variable TSI system) will be described. FIG. 2 is a time chart showing an example of the operation. In FIG. 2, the horizontal direction corresponds to the time axis.

First, as shown in the first to fourth stages in FIG. 2, the input signals S having the same timing and the same speed are output from each line.
When i1 to Si4 start to be input, at the same time, the address counter 2 starts counting and outputs a write address counter signal Swac, and the decoding circuit 3 receiving it outputs a write address signal Swa (fifth). And the sixth row). In the illustrated input signals Si1 to Si4, "A",
"A '", "B",..., "D'" represent signals for one unit in multiplexing (signals included in one time slot), and the write address counter signal Swac for each unit. Is incremented, and the designated address of the write address signal Swa is incremented.

As a result, the parallel data "A" to "D" are supplied to the dual port memory 1 in the first time slot, and these are designated by the designated address "00".
Are simultaneously written to the storage area. Then, in the next time slot, the parallel data of "A '" to "D'" is supplied, and these are simultaneously written to the storage area of the designated address "01". In this way, the signals supplied simultaneously from the respective lines are sequentially and temporarily stored in the dual port memory 1.

Next, the address counter 2 starts to output the read address counter signal Srac (see the seventh row), and at the same time, the decode circuit 4 outputs the read address signal Sra, and the dual port memory 1 receiving the read address signal Sra Starts to output the output signals So1 to So4 (the eighth stage and the ninth to twelfth
See column.) At this time, the decoding circuit 4 first designates the address "00" in which the data is stored in the above-mentioned first time slot, and determines that the count value of the read address counter signal Srac is "4" (corresponding to four lines). After the data is maintained until the count increases, the address "01" in which the data is stored is designated in the next time slot, and this designation is similarly maintained until the count value increases by "4".

Thus, the read address counter signal S
While the count value of rac is "3" to "6", the output signals So1, So2, So3, and So4 of the dual port memory 1 are maintained at "A", "B", "C", and "D", respectively. And
Next, while the count value is "7" to "10", the output signals So1, So2, So3, and So4 are "A '",
"B '", "C'", and "D '" are retained.

On the other hand, the read address counter signal Srac starts to be input to the output control circuit 5, and at the same time, the output selection signal Sos for sequentially selecting the output signals So1, So2, So3, and So4 starts to be output (the thirteenth stage). reference). In the illustrated output selection signal Sos, “o1”, “o2”, “o3”,
“O4” represents a signal for selectively designating the output signals So1, So2, So3, and So4.

As a result, in the selection circuit 6, the output signal So1 is selected in the time slot in which the count value of the read address counter signal Srac is "3". At this time, "A" output as the output signal So1 is externally output. Output signal S
Output as o. After that, the count value becomes “4”,
In the time slots “5” and “6”, the output signals So2, So3, and So4 are selected, and “B”, “C”,
“D” is output as the external output signal So. And
The output signal So1 is selected again in the time slot where the count value becomes "7" and "A '" is output, and the output signal So is output again in the subsequent time slots of count values "8", "9" and "10". So2, So3 and So4 are selected and "B '",
"C '" and "D'" are output. Fig. 2
The external output signal So whose order has been converted as shown in the fourteenth stage is output from the selection circuit 6.

According to the communication control apparatus, as described above, the input signals Si1 to Si4 are all written into the dual port memory 1 at the same timing, and when these are read, the necessary timing is determined by the address counter 2 and the decoding circuit 4. Generate and convert signal order to time division. That is, signals of the same timing and the same speed input to the dual port memory 1 are counted by the address counter 2, the decode signals on the write side and the read side are input to the dual port memory 1, and the output signal is further selected. The output control circuit 5 performs time division output as a possible state. As a result, an external output signal So obtained by converting the parallel input signals Si1 to Si4 to serial and time-division multiplexed is output. And
As can be seen from FIG. 2, the external output signal So starts to be output immediately after the supply of the input signal, and the delay in transmitting the multiplexed signal is minimized. Further, as can be seen from FIG. 1, the present communication control device does not include a delay circuit as a component. Therefore, a multiplexed signal can be transmitted in real time, and this can be realized with a small-scale circuit configuration.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the number of lines is four.
In the above description, the case where the signal continuously supplied at a time corresponds to two units has been described as an example. However, the present invention is not limited to such a case. Can be applied. In addition, it is possible to similarly multiplex and transmit a subsequent input signal supplied subsequently to the above-mentioned signal.

[0033]

As described above, according to the present invention, signals from a plurality of lines are simultaneously stored in a predetermined storage area for each predetermined unit signal supplied at the same time, and each of the lines simultaneously stored is stored in a predetermined storage area. Since the unit signals are read and held at the same time, and the unit signals being read during the holding are output in a fixed order, the unit signals from a plurality of lines are simultaneously stored without delay, They can be output immediately in a certain order. As a result, it is possible to realize a circuit for transmitting a multiplexed signal with a small-scale configuration that does not require a delay circuit, and to transmit a multiplexed signal in real time while minimizing a delay in transmitting the signal. The effect that it can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication control device according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation example of the communication control device.

FIG. 3 is a block diagram showing a configuration of a typical time-division signal permutation conversion circuit in a conventional communication control device.

FIG. 4 is a time chart showing the operation of the circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dual port memory 2 Address counter 3, 4 Decoding circuit 5 Output control circuit 6 Selection circuit Si1-Si4 input signal So1-So4 output signal So external output signal Sra Read address signal Srac Read address counter signal Swa Write address signal Swac Write Address counter signal

Claims (5)

[Claims] 1. A signal from a plurality of lines is simultaneously stored in a predetermined storage area for each predetermined unit signal supplied at the same time, and the predetermined unit signals of each line stored simultaneously from the predetermined storage area are read out simultaneously. A communication control method comprising: outputting the read predetermined unit signals in a predetermined order. 2. A storage unit for simultaneously storing signals from a plurality of lines in a predetermined storage area for each of predetermined unit signals supplied simultaneously, and the predetermined unit of each line simultaneously stored from the predetermined storage area. Reading means for simultaneously reading out signals and holding the readout state; and while the state is being held by the reading means, the predetermined unit signals of the respective lines being read out in a predetermined order. A communication control device, comprising: an output unit that outputs. 3. The communication control device according to claim 2, wherein said storage means includes an address specification means for specifying an address for each of said predetermined unit signals from said plurality of lines, and stores said predetermined unit signal of each line. A dual port memory for simultaneously writing to an address designated by the address designating means, wherein the reading means designates, in the dual port memory, an address at which the predetermined unit signal of each line is written. A communication control device for outputting a signal of an address and maintaining the state by continuously specifying the address for a certain period. 4. The communication control device according to claim 2, further comprising: an address counter that starts counting from a timing at which the signal is input, wherein the storage unit temporarily stores signals input simultaneously. A memory, and a decoding circuit for writing a signal input from the address counter to the dual port memory, wherein the reading means reads the signal input from the address counter from the dual port memory. A decoding circuit, wherein the output means includes: a selection circuit for selecting a signal read from the dual port memory; and an output control circuit for controlling the selection circuit. A communication control device characterized by changing. 5. The communication control device according to claim 4, wherein a signal output is processed in real time with respect to the signal input.