JP2000174131A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which problems of gate destruction due to antenna effect and crosstalk can be dissolved, and analysis and prevention of problems are easily enabled in an LSI circuit where hierarchical layout is performed, and a manufacturing method of it. SOLUTION: Hierarchical blocks 1 are connected with wiring outside the hierarchical blocks via hierarchical terminals 2, and the respective hierarchical terminals 2 are connected with inner wiring of the hierarchical blocks 1 via exclusive use I/O cells. As a result, wiring in the respective hierarchical blocks is isolated from the wiring outside the blocks, an antenna ratio composed of the ratio of a side area of the wiring and a gate area of a transistor can be easily presumed, gate destruction due to antenna effect can be prevented, crosstalk between wirings can be easily analyzed at the time of design, and generation of crosstalk can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit capable of eliminating gate destruction and crosstalk in a semiconductor integrated circuit having a hierarchical layout, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the progress of semiconductor fine processing technology, the density and integration of LSI circuits have been increasing,
Manufacturing precision of the deep submicron era,
At present, a large-scale integrated circuit exceeding 10 million gates can be mounted on one LSI. If the design of such a large-scale LSI circuit is carried out collectively, the design time becomes enormous. Therefore, most LSI circuits are designed by a hierarchical design method.

[0003]

By the way, in LSI design of deep submicron, various problems which have not been encountered so far have become remarkable. One is the problem of gate destruction due to the antenna effect, and the other is the crosstalk problem. First, the problem of gate destruction due to the antenna effect will be described. In an LSI manufacturing process, a conductor layer is directly irradiated with plasma in the following three processes. That is, etching of the conductor layer, ashing (ashing) of an organic substance (eg, a resist) on the conductor layer, and etching of the contact via. Charges are charged to the conductor layer by the irradiated plasma, and the charges damage the gate oxide film. This seems to be the cause of the gate destruction due to the antenna effect. In particular, in the step of etching the conductor layer, it greatly affects the gate oxide film. The charge is charged by the plasma irradiated from the side surface of the conductor layer after the new pattern is formed on the conductor layer until it is completely separated. On the other hand, since the charge escapes to the drain / source before the pattern is separated, no gate breakdown occurs.

Therefore, the amount of damage to the gate oxide film is
Wiring that is proportional to the side area of the wiring formed on the conductor layer and that is connected only to the gate (this is called an "antenna")
Only matters. The gate breakdown due to the antenna effect can be avoided by improving the manufacturing process or the mask pattern.

[0005] Regarding the improvement of the manufacturing process, a number of solutions have been proposed, such as a method of releasing charges charged in the conductor layer during the etching process and a method of incorporating a protection diode and the like. However, all of these require a large change in the production line of the LSI, resulting in a large cost.

On the other hand, as a method based on improvement of a mask pattern, a method of correcting a wiring pattern in which gate breakdown is likely to occur is known. For example, there is a method in which the wiring pattern is moved to the uppermost layer of the conductor near the root of the “antenna”, and the charged charge is released to the drain / source. In this method, there is no need to change the manufacturing process, so that the cost burden is extremely small.

Here, the collective layout of the LSI circuit is called a flat layout, and the hierarchical layout is called a hierarchical layout. In a method of preventing gate destruction by improving a mask pattern, a problem in performing a hierarchical design is how to recognize an "antenna". In general, "antenna" in the ratio of the lateral area A _sw gate area A _Gate wiring (A _sw / A
_gate ) is defined as the antenna ratio, and a pattern whose value is equal to or more than a certain value is regarded as a risk of gate destruction, and the pattern is corrected.

For example, in an example in which a hierarchical layout as shown in FIG. 8 is performed, an LSI using two-layer wiring is assumed, the area of the gates 3a and 3b is 1, the terminals 2a and 3b of the hierarchical blocks 1a and 1b are set. If the side area of the wiring from 2b to the gate is 10 and all the wirings are formed in the first wiring layer, the hierarchical blocks 1a and 1
b, the antenna ratio of the gates 3a and 3b is (1
0/1 = 10).

[0009] However, the antenna ratio determined in this way has no meaning in most cases. In practice, it is necessary to consider wiring that leads to a higher hierarchy. For example, the wiring from the source 4a of the transistor 4 to the branch point 5 is formed in the second wiring layer, and the other wirings are formed in the first wiring layer on the assumption that the wiring is formed in the first wiring layer. Assuming that the side area of the wiring from to the block terminals 2a and 2b is 100, the antenna ratio of the gates 3a and 3b can be obtained as follows. That is, (10 + 100
+ 10 + 100) / (1 + 1) = 110.

If the wiring from the source 4a to the branch point 5 is formed in the first wiring layer, the charged charges escape to the source 4a, and the antenna ratio becomes zero. This means that the information of the lower layer has to be transmitted to the upper layer in some form, and it is difficult to perform separate processing for each layer. Then, in the worst case, the antenna ratio must be calculated by collective processing from the highest hierarchy.

Next, the problem of crosstalk will be described. Crosstalk refers to a state in which signals on adjacent wirings affect each other and the designed LSI does not operate as intended. Crosstalk includes a net that affects and a net that is affected. It is the affected net that causes unexpected behavior due to crosstalk. Eliminating the nets affected by crosstalk can solve the problem of crosstalk. Generally, the degree of the influence of the crosstalk greatly depends on the slope of the input waveform. That is, if the slope of the waveform of the output signal from the preceding stage is increased for a net affected by crosstalk, the problem of crosstalk is reduced.

For this reason, as a method of alleviating the crosstalk, there are a method of increasing the driving capability of the preceding stage, and a method of inserting a repeater to divide the wiring capacitance. However, there are problems with adapting these methods to a hierarchical layout. For example, in the case of a layout as shown in FIG. 9 having the hierarchical blocks 1a and 1b, it is assumed that crosstalk has occurred in the hierarchical block 1b on the path from the terminal 2b of the hierarchical block to the gate 3b. However, at the stage of setting the layout of the hierarchical block 1b, it is not known whether or not this net is affected by the crosstalk because the driving capability of the preceding stage is unknown. Further, there is a problem that even if a layout is modified in a part other than the user, the influence is exerted. In the hierarchical block 1a, the terminal 2
When the path from “a” to the gate 3a changes, the wiring capacitance connected to it also changes. The influence also affects the input waveform of the cell including the gate 3b. As a result, there is a possibility that the hierarchical block 1b must be modified.

The present invention has been made in view of the above circumstances, and an object of the present invention is to solve a problem of gate destruction and a problem of crosstalk due to an antenna effect in an LSI circuit performing a hierarchical layout, and to analyze and solve the problem. And a method of manufacturing the same.

[0014]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit constituted by using at least two wiring layers, wherein the one integrated wiring layer A circuit block formed of a semiconductor circuit including at least one transistor; at least one input / output terminal arranged around the circuit block; and one terminal arranged around the circuit block, and one terminal connected to the input block. An input / output cell connected to an output terminal, the other terminal connected to a terminal of the transistor via a wiring in the circuit block, and controlling connection between the input / output terminal and a wiring in the circuit block; .

Further, a method for manufacturing a semiconductor integrated circuit according to the present invention is a method for manufacturing a semiconductor integrated circuit using at least two wiring layers, wherein at least one transistor is provided in the one wiring layer. A first step of arranging a circuit block composed of a semiconductor circuit including at least one input / output terminal around the circuit block;
And an input / output cell for controlling the connection between the terminal of the transistor and the input / output terminal of the semiconductor circuit. One terminal of the input / output cell is connected to the terminal of the transistor. Connecting a terminal to the input / output terminal.

In the present invention, preferably, the power supply wiring is arranged so as to overlap with a power supply wiring formed in a wiring layer different from the circuit block.

Further, in the present invention, preferably, the input / output cell is constituted by an input / output buffer.

According to the present invention, in a semiconductor integrated circuit having a so-called hierarchical layout structure in which semiconductor circuits are formed in different wiring layers, respectively, in a circuit block formed in one of a plurality of wiring layers, An input / output cell is provided for separating input / output terminals arranged around the block from circuit elements such as transistors formed inside the circuit block. These input / output cells are composed of, for example, an input / output buffer and are arranged at the periphery of the circuit block. One terminal of the input / output cell is connected to a circuit element such as a transistor via a wiring formed inside the block, and the other terminal is connected to an input / output terminal arranged around the circuit block. .

By constructing the semiconductor integrated circuit in this way, the wiring inside each circuit block and the wiring outside the circuit block are completely separated by the input / output cells, so that the transistors in each circuit block due to the antenna effect are formed. Analysis and elimination of gate destruction and crosstalk can be easily performed. Furthermore, by arranging the input / output cells around the circuit block so as to overlap with the power supply wiring formed in a different wiring layer from other circuit blocks,
An increase in the layout area is suppressed to a necessary minimum.

[0020]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 1, 1
Denotes a hierarchical block, 2 denotes a hierarchical block terminal, and 8 denotes a group of logic cells arranged. FIG. 1 shows a configuration example of a standard cell type integrated circuit having a hierarchical structure in the present invention. The semiconductor integrated circuit of the present embodiment is provided with a logic cell group 8 including normal logic gate cells in addition to the hierarchical block 1. Each hierarchical block terminal 2 is connected to an input / output cell dedicated to the hierarchical block. As shown in the figure, the hierarchical blocks 1 are alternately connected via hierarchical block terminals 2 and wirings formed between the terminals.

FIG. 2 is a diagram showing an image of a hierarchical block in FIG. FIG. 2 shows the configuration of a dedicated input / output cell connected to a hierarchical block terminal 2 arranged around the hierarchical block 1 in further detail. As shown in FIG.
A dedicated input / output cell (hereinafter referred to as a dedicated I / O cell) is connected. Each dedicated I / O cell is constituted by an input, output or bidirectional buffer cell having a common height and various driving capabilities. Note that these dedicated I / O cells are all arranged on the boundary of the hierarchical block 1 and are connected to, for example, wiring between hierarchical blocks via the hierarchical block terminals.

FIG. 2 shows an image of the arrangement of the hierarchical block 1 and the I / O cells dedicated to the hierarchical block provided around the hierarchical block 1, which are different from the actual arrangement.
For example, in FIG. 2, each dedicated I / O cell appears to protrude from the hierarchical block 1, but actually, these dedicated I / O cells overlap with a power supply wiring section running around the hierarchical block 1. The protrusion is very small.

FIG. 3 shows a wiring structure of a dedicated I / O cell connected to the hierarchical block terminal 2 shown in FIG. 3, reference numeral 10 denotes a boundary line of the hierarchical block 1 in FIG. 2, reference numerals 21 and 22 denote hierarchical block terminals, and reference numerals 31 and 32 denote dedicated I / O cells connected to the hierarchical block terminals 21 and 22, respectively. Is shown. Furthermore, V
SS and VDD indicate a common potential wiring and a power supply wiring for supplying the common potential V _SS and the power supply voltage V _DD , respectively. These wirings are respectively formed on the conductor layers.

As shown in FIG. 3, the dedicated I / O cells 31 and 32 are arranged so as to overlap the common potential wiring VSS and the power supply wiring VDD, respectively. For this reason, the protrusions of the hierarchical block terminals 21 and 22 can be small.

FIG. 4 is a layout diagram showing a relationship between a dedicated I / O cell connected to a hierarchical block terminal and a common potential wiring and a power supply wiring running around the hierarchical block. In FIG. 4, reference numeral 20 denotes a hierarchical block terminal, and 30 denotes a dedicated I / O.
O cells, 40 and 42 are contacts, and 50 is a connection terminal to the inside of the hierarchical block.

Power supply line VDD and common potential line VSS
Are formed in a wiring layer belonging to a different hierarchy from the dedicated I / O cell 30. The dedicated I / O cell 30 is arranged so as to overlap with these wirings. Power is supplied to the dedicated I / O cell 30 via contacts 40 and 42. In FIG. 4, the dedicated I / O cell 30
Are connected to external wiring via a hierarchical block terminal 20 and further connected to a circuit inside the hierarchical block via a connection terminal 50.

FIG. 5 shows an arrangement in which the power supply wiring VDD and the common potential wiring VSS have different wiring widths. In FIG. 5, the same components are denoted by the same symbols as in FIG.

As shown in the figure, in this example, the width of the common potential wiring VSS and the power supply wiring VDD is formed wider than that of the arrangement example shown in FIG. 4, so that the connection between the dedicated I / O cell 30 and the power supply wiring VDD is established. , Is different from the arrangement example shown in FIG.
In the present example, the dedicated I / O cell 30 is connected to the contact 42 via the wiring 60, and is connected to the power supply wiring VDD via the contact 42.

FIG. 6 and FIG. 7 show equivalent circuits of the semiconductor integrated circuit of the present embodiment. Hereinafter, FIGS. 6 and 7
A description will be given of the elimination of gate destruction and crosstalk due to the antenna effect in the semiconductor integrated circuit of the present embodiment with reference to FIG.

FIG. 6 shows hierarchical blocks 1a and 1b and gates 3a and 3b formed in these hierarchical blocks, respectively. Note that the gates 3a and 3b are, for example, the gates of transistors forming a semiconductor circuit. As shown, in the hierarchical block 1a, the gate 3a is connected to the dedicated I / O cell 30a via a wiring, and similarly, in the hierarchical block 1b, the gate 3a
b is connected to the dedicated I / O cell 30b via a wiring.

The transistor 4 is a transistor formed in a different wiring layer from the hierarchical block 1a or 1b. The source 4a of the transistor 4 is connected to the branch point 5 via a wiring. The branch point 5 is connected to the hierarchical block terminals 2a and 2b via wiring. The hierarchical block terminal 2a is a dedicated I / O cell 30a.
And the hierarchical block terminal 2b is connected to the dedicated I / O cell 3
0b.

In the semiconductor integrated circuit having the hierarchical block structure shown in FIG. 6, the wiring between the gate 3a in the hierarchical block 1a and the output terminal of the dedicated I / O cell 30a is connected to the input / output terminal by the dedicated I / O cell 30a. It is completely separated from the external line of the hierarchical block 1a connected to 2a. Similarly, in the hierarchical block 1b, the wiring between the gate 3b and the output terminal of the dedicated I / O cell 30b is connected to the external line of the hierarchical block 1b connected to the output terminal 2b by the dedicated I / O cell 30b. Completely separated.

As a result, the wiring between the gate 3a and the hierarchical block terminal 2a in the hierarchical block 1a, the wiring between the gate 3b and the hierarchical block terminal 2b in the hierarchical block 1b, and the source 4a of the transistor 4 from the hierarchical block terminals 2a and 2b The wiring to each is a separate net. Therefore, when calculating the antenna ratio, it is sufficient to calculate independently for each of these three wirings, and it is not necessary to consider wirings of other hierarchical blocks. As a result, the antenna ratio can be easily calculated, and gate destruction due to the antenna effect can be effectively prevented.

In FIG. 7, the hierarchical blocks 1a and 1b
And wirings formed in each of these hierarchical blocks. As shown, in the hierarchical block 1b, a wiring 6a is formed between the dedicated I / O cell 30b and the terminal 3b, and a wiring 6b is formed between the dedicated I / O cell 5b and the terminal 4b. When analyzing the crosstalk between the wires 6a and 6b in the hierarchical block 1b, the dedicated I / O cells 30b and 5 for driving the wires 6a and 6b are used.
Since the driving capability of b is set in advance, it is known at the time of design. For this reason, whether or not crosstalk occurs on the net formed by the wirings 6a and 6b can be grasped at the time of design, and measures can be taken to prevent the occurrence of crosstalk at the design stage.

As described above, according to the present embodiment, each of the hierarchical blocks 1 is connected to the wiring outside the hierarchical block via the hierarchical block terminal 2, and each of the hierarchical block terminals 2 is connected to a dedicated I / O. Since the wiring is connected to the internal wiring of the hierarchical block 1 via the cell, the wiring in each hierarchical block and the wiring outside the block are separated from each other, and the antenna ratio consisting of the ratio of the side area of the wiring to the gate area of the transistor can be easily estimated. Thus, gate destruction due to an antenna effect can be prevented, and furthermore, crosstalk between wirings can be easily analyzed at the time of design, and occurrence of crosstalk can be prevented.

[0036]

As described above, according to the semiconductor integrated circuit and the method of manufacturing the same according to the present invention, it is possible to easily analyze the gate breakdown and the crosstalk due to the antenna effect in the hierarchical layout. There is an advantage that gate destruction and crosstalk due to the antenna effect can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is an image diagram showing an arrangement of a hierarchical block and dedicated I / O cells arranged around the hierarchical block.

FIG. 3 shows a dedicated I / O arranged around a hierarchical block.
FIG. 3 is an arrangement diagram of O cells, power supply lines, and common potential lines.

FIG. 4 is a layout diagram of dedicated I / O cells, power supply lines, and common potential lines.

FIG. 5 is a layout diagram of dedicated I / O cells, power supply wirings having different wiring widths, and common potential wirings.

FIG. 6 is an equivalent circuit for calculating an antenna effect in the semiconductor integrated circuit of the present invention.

FIG. 7 is an equivalent circuit for estimating crosstalk in the semiconductor integrated circuit of the present invention.

FIG. 8 is an equivalent circuit for calculating an antenna effect in a conventional semiconductor integrated circuit.

FIG. 9 is an equivalent circuit for estimating crosstalk in a conventional semiconductor integrated circuit.

[Explanation of symbols]

1, 1a, 1b ... hierarchical block, 2 ... hierarchical block terminal, 3a, 3b ... gate, 4 ... transistors formed in wiring layers other than the hierarchical block, 4a ... source of transistor 4, 5 ... branch point of wiring, 6a, 6b ... wiring, 7
... output circuit, 8 ... logic gate cell group, 10 ... boundary line of hierarchical block, 20, 21, 22 ... hierarchical block terminal, 3
0, 31, 32... Dedicated I / O cells, 40, 42... Contacts, 50... Hierarchical block internal terminals.

Claims (5)

[Claims] 1. A semiconductor integrated circuit configured using at least two wiring layers, a circuit block formed on the one wiring layer and including a semiconductor circuit including at least one transistor; At least one input / output terminal disposed around the block, and one terminal connected to the input / output terminal disposed around the circuit block, and the other terminal connected via wiring in the circuit block. Connected to the terminal of the transistor,
A semiconductor integrated circuit having an input / output cell for controlling connection between the input / output terminal and a wiring in the circuit block. 2. The semiconductor integrated circuit according to claim 1, wherein said input / output cells are arranged so as to overlap a power supply wiring formed on a wiring layer different from said circuit block. 3. The semiconductor integrated circuit according to claim 1, wherein said input / output cell comprises an input / output buffer. 4. A method of manufacturing a semiconductor integrated circuit using at least two wiring layers, wherein a circuit block including a semiconductor circuit including at least one transistor is arranged in the one wiring layer. A first step, a second step of arranging at least one input / output terminal around the circuit block, and an input / output cell for controlling the connection between the terminal of the transistor and the input / output terminal of the semiconductor circuit And a third step of connecting one terminal of the input / output cell to the terminal of the transistor and connecting the other terminal to the input / output terminal. 5. The method of manufacturing a semiconductor integrated circuit according to claim 4, wherein said input / output cell is arranged around said circuit block so as to overlap with a power supply wiring formed in a wiring layer different from said circuit block.