JP2000165291A - Cdma test signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a hardware for a product-sum operation (channel multiplex arithmetic operation) with a small sized and inexpensive configuration. SOLUTION: A CDMA test signal generator is provided with a product-sum operation section 24 that multiplies a weight coefficient set to each channel by test pattern data of each channel that is spread-spectrum-processed and sums the product of each channel over all channels, a modulation section 28 that modulates a carrier frequency signal with output data of the product-sum arithmetic section and an output section 29 that outputs an output signal of the modulation section as a CDMA test signal. In this case, the product-sum operation section 24 consists of product-sum operation memory tables 24a, 24b to which each combination over all channels with respect to all values taken of test pattern data of each channel with respect to each address is assigned and where a product-sum operation result obtained by the combination of the test pattern data is stored in an address location designated by each address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a CDM communication system.
The present invention relates to a mobile terminal test apparatus for testing a mobile terminal employing the A system, and more particularly, to a CDMA test signal generation apparatus incorporated in the mobile terminal test apparatus and transmitting a CDMA test signal to a mobile terminal to be tested.

[0002]

2. Description of the Related Art In recent years, mobile communications such as mobile phones and PHSs have been rapidly spreading. In particular, in the future, digital systems such as PHS will be adopted, and CDMA (code division multiple access) will be used to secure the number of channels.
It is considered that mobile communication using a communication method is widely used.

[0003] Therefore, it is necessary to accurately and quickly carry out a test for correctly operating a mobile terminal possessed by each subscriber used for the mobile communication or a mobile terminal under development.

FIG. 5 is a block diagram showing a schematic configuration of a mobile terminal test apparatus for testing the operation of, for example, a portable telephone as a mobile terminal adopting the CDMA system.

[0005] This mobile terminal test apparatus is roughly divided into
A CDMA test signal generator 2 for transmitting a CDMA test signal a to a terminal under test 1 such as a mobile phone terminal;
CD from terminal under test 1 receiving A test signal a and outputting CDMA measurement signal b corresponding to CDMA test signal a
And a CDMA signal reception analyzer 3 for receiving and analyzing the MA measurement signal b.

In the CDMA test signal generator 2,
Each digital test pattern data of each channel output from the test pattern generation unit 4 is different in PN (pseudo noise) for each channel in the next spread spectrum unit 5.
The spectrum is spread by multiplying the pattern data.

The spread spectrum test pattern data of each channel is multiplied by a weight coefficient corresponding to the corresponding channel for each channel in the following product-sum operation unit 6.
Further, the multiplied product values of the respective channels are added for all the channels for each of the I phase and the Q phase.

The output data added from all the channels output from the product-sum operation unit 6 is shaped by a RN (root Nyquist) filter 7 and then input to a modulation unit 8. The modulator 8 modulates the carrier frequency signal with the input output data (test pattern data after addition) and sends the modulated signal to the output RF (high frequency) interface 9. Output RF
The interface 9 sends the modulated signal output from the modulator 8 to the terminal under test 1 as a CDMA test signal a.

On the other hand, in the CDMA test signal reception analyzer 3, the input RF (high frequency) interface 10
The high-frequency CDMA measurement signal b transmitted from the terminal under test 1 is frequency-converted to a low frequency (intermediate frequency) and transmitted to the next demodulation unit 11. The demodulation unit 11 receives the input CDMA
The measurement signal b is demodulated into a baseband signal and transmitted to the spectrum despreading unit 12.

[0010] The spectrum despreading section 12 performs despreading processing on input data using different PN pattern data for each channel, obtains received data for each channel, and outputs the received data to the next decoding section 13. Send to The decoding unit 13 performs various decoding processes on the input reception data of each channel and sends the data to the analysis unit 14. The analysis unit 14 is a decoding unit 13
Various analyzes such as a transmission error, a bit error, and a signaling test are performed on the received data of each channel decoded in step (1).

The test pattern generator 4, the spread spectrum unit 5, and the product-sum operation unit 6 in the CDMA test signal generator 2 which constitutes one of the mobile terminal test apparatuses having such a configuration are configured as shown in FIG. I have.

In the test pattern generator 4, for example, 6
A test pattern generator 4a is incorporated for each channel. Test pattern generator 4 for each channel
a transmits test pattern data composed of a pair of baseband data I and Q to the multiplier 5a of the corresponding channel in the spread spectrum unit 5.

The multiplier 5a of each channel multiplies the pair of baseband data I and Q by the PN pattern data output from the PN pattern generator 5b to spread the pair of baseband data I and Q. Then, the signal is sent to the weighting unit 6a of the corresponding channel in the next product-sum operation unit 6.

A weighting section 6a for the corresponding channel in the product-sum operation section 6 stores a weighting coefficient memory 6 for each of the input baseband data I and Q spread spectrum.
b is multiplied by the weight coefficient G set for the corresponding channel stored in the corresponding channel, and each multiplied value I for each baseband data I and Q is obtained.
G and QG are sent to the adder 6c.

By setting the weight coefficient G to a different value for each channel, the signal strength indicated by the amplitude of the test signal of each channel can be set to a different value.

The adder 6c includes a weighter 6a for each channel.
Are added for each of the I-phase and Q-phases over all the channels, and the added values ΣIG and ΣQG for each of the I- and Q-phases are added. The calculated value is sent to the next RN filter 7.

Here, the spread spectrum unit 5 is QPSK.
When the system is adopted, the multiplication unit 5 of each channel is used.
Each of the baseband data I and Q output from a is +
Since three types of values 1, 1, and 0 can be taken, each baseband data I, Q is represented by 2 bits. Therefore, each of the baseband data I and Q input to the product-sum operation unit 6 after being spread spectrum can also be represented by 2 bits.

The number of bits required for the added values ΣIG and ΣQG for each of the baseband data I and Q output from the adder 6c is represented by, for example, 16 bits, depending on the dynamic range of the weighting coefficient G to be multiplied. You.

[0019]

However, the CDMA test signal generator 2 constituting one of the mobile terminal test apparatuses shown in FIG. 5 has the following problems to be solved. That is, the CDMA test signal generator 2
As shown in FIG. 6, the product-sum operation unit 6 incorporated in
The test pattern data output from the test pattern generator 4a of each channel is a pair of baseband data I,
In the case where the number of channels is N, the weighting unit 6a composed of a multiplier needs 2N, which is twice the number N of channels. The addition unit 6c adds the multiplication values IG and QG of the baseband data I and Q to the I-phase,
For each Q phase, (N-1) adders are required. Therefore, a total of 2 (N-1) adders are required.

Therefore, in the case of N channels, the product-sum operation unit 6 includes 2N multipliers (weighting units 6a) and 2 (N-1)
Adders are required. For example, in the case of 6 channels,
Twelve multipliers and ten adders are required. Therefore, there is a problem that not only the overall configuration of the product-sum operation unit 6 becomes complicated and large, but also that the manufacturing cost increases significantly.

Further, the process of weighting and adding the baseband data I and Q of each channel after the spread spectrum (ΔIG, ΔQG) is the same process for each of the I phase and the Q phase. Therefore, there is a concern that the circuit configuration of each of the I-phase and the Q-phase may include redundant functions, and that the overall configuration of the product-sum operation unit 6 may be further inefficient.

The present invention has been made in view of such circumstances, and provides a small-sized and inexpensive CDMA test signal generator with a simple configuration by forming a product-sum operation unit in a memory table configuration. With the goal.

[0023]

According to the present invention, there are provided a plurality of test pattern generators for outputting test pattern data comprising a pair of I-phase and Q-phase baseband data for each channel; A test pattern data consisting of a pair of baseband data to be output is multiplied by PN pattern data having different patterns to spread the test pattern data, and a spread spectrum unit for spread spectrum of each test pattern data. The test pattern data including a pair of baseband data of the I phase and the Q phase is multiplied by a weight coefficient set for the corresponding channel, and the multiplied value for each of the I and Q phases of each channel is applied to all the channels. And a sum-of-products operation unit for performing a channel multiplexing operation and summing the carrier frequency signal A quadrature modulation unit, the output signal of the quadrature modulating portion C which modulates the output data of the I-phase and Q-phase calculation section
Output unit for outputting as a DMA test signal
Applied to A test signal generator.

In the CDMA test signal generator according to the first aspect of the present invention, the product-sum operation unit covers all channels in all possible values of each baseband data of each channel for each address. Each combination is allocated, and a pair of multiply-accumulate operation memory tables corresponding to the I-phase and the Q-phase in which the added value obtained by the combination of the baseband data indicated by the corresponding address is stored at the position designated by each address. I have.

In the CDMA test signal generator configured as described above, the test pattern data of each channel subjected to spread spectrum is multiplied by a weighting factor.
The function of adding the multiplied values of the respective channels over all the channels is realized by a product-sum operation memory table.

That is, each test pattern data of each channel output from the spread spectrum unit is input as an address value to an address terminal of the product-sum operation memory table. Then, the corresponding operation result stored at the position specified by the address value is read.

Therefore, the number of multipliers and adders determined according to the number of channels is not required, so that the circuit configuration can be greatly simplified. Each addition value is calculated and stored in advance, and only the stored necessary addition value is read out.

The test pattern data output from the spread spectrum unit is composed of a pair of I-phase and Q-phase baseband data. Therefore, for each I phase and Q phase,
A pair of product-sum operation memory tables is provided.

Further, in the CDMA test signal generator according to the second aspect, the above-mentioned product-sum operation unit is provided for all the channels in all possible values of each baseband data of each channel for each address. One product-sum operation memory table in which each combination is allocated and an added value obtained by a combination of baseband data indicated by the corresponding address is stored at a position specified by each address; and one product-sum operation memory table And a switching unit for time-division use for the I-phase and the Q-phase.

As described above, the process of weighting the baseband data I and Q of each channel after spectrum spreading is the same for each of the I phase and the Q phase. Therefore, in the CDMA test signal generator according to the second aspect, the switching unit uses one product-sum operation memory table in a time-division manner for each of the I phase and the Q phase.

Therefore, the required storage capacity of the product-sum operation memory table can be reduced.

Further, in the CDMA test signal generator according to the third aspect of the present invention, the CDMA test signal generator of the present invention is further provided with each additional value at a position specified by each address of the product-sum operation memory table. An addition value rewriting means for rewriting each addition value when the weight coefficient for each channel is changed is added.

In the thus configured CDMA test signal issuing apparatus, when it is necessary to change the weighting factor for each channel and execute the test, each added value is calculated using the weighting factor changed in advance. , And writing the calculated addition value to the designated position of the corresponding address in the product-sum operation memory table.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a CDMA test signal generator according to a first embodiment of the present invention.

The CDMA test signal generator can transmit, for example, data for a total of six channels. Therefore, in the CDMA test signal generator, six test pattern generators 21 are provided for each channel. Each test pattern generator 21
Are a pair of 2-bit digital baseband data I (I ₁ , I ₂ ,..., I ₆ ), Q (Q ₁ , Q ₂ ,.
And it outputs the test pattern data consisting of Q _6).

The baseband data I (I ₁ , I ₂ ,..., I ₆ ), Q output from each test pattern generator 21
(Q ₁ , Q ₂ ,..., Q ₆ ) are input to the respective spreading sections 22 provided for the I phase (in-phase component) and the Q phase (quadrature component) of the corresponding channel. Each spreading section 22 is supplied with PN pattern data having the same bit period and different bit patterns from the PN pattern generating section 23.

The spreading section 22 performs a complex operation on the baseband data I and Q inputted thereto and the 2-bit PN pattern data supplied from the PN pattern generating section 23 to form a pair of baseband data I and Q. , Q are spread, and new baseband data Ia (Ia ₁ , Ia ₂ ,..., Ia ₆ ) after the spread spectrum is obtained.
Qa (Qa ₁ , Qa ₂ ,..., Qa ₆ ) is sent to the following product-sum operation unit 24. This new baseband data I
Since a and Qa take three values {-1, 0, +1}, they have a 2-bit configuration.

The PN pattern generating section 23 outputs a large number of PN pattern data having the same bit period and different bit patterns to the control section 2 comprising a computer.
6, and is transmitted to each spreading section 22 in synchronization with the clock signal k from the clock generating section 25.

Therefore, each of the spreading sections 22 and the PN pattern generating section 23 constitute a spectrum spreading section that spreads each pattern data output from each of the test pattern generating sections 21 in a spectrum.

The product-sum operation unit 24 is composed of a pair of product-sum operation memory tables 24a and 24b corresponding to the I and Q phases, and implements weighted channel multiplexing. Product-sum operation memory table 24a corresponding to I-phase (in-phase component)
For example, when multiplexing six channels, as shown in FIG. 2A, each address A ₀ , A ₁ ,
... in a position to specify the appropriate address A _0, A _1, corresponding additional value to _{... (ΣIG) 0, (ΣIG} ) 1, ... it is stored.

Each of the 12-bit addresses A ₀ , A ₁ ,
... each digit _{d 1, d 2, d 3} , ..., for each terminal of the d _12, baseband data Ia of two bits from the first two-bit configuration after spreading in each channel _1, Ia _2,
.., Ia ₆ are input.

Therefore, the product-sum operation memory table 24
By constructing a with a 12-digit address space, 6
Baseband data Ia of each channel in channel
Addition values (ΣIG) ₀ and (ΣIG) corresponding to all possible combinations of ₁ , Ia ₂ ,..., Ia _6
1 , ... can be set.

Next, each addition value (@IG) ₀ , (@IG) ₁ ,... Set at the designated position of each address A ₀ , A ₁ ,.
Will be described. That is, as described with reference to FIG.
Weighting factors G preset for each channel of
_{1, G 2, ..., G} 5, G 6 baseband data Ia ₁ of 2-bit configuration after spreading in each channel of the corresponding channel, Ia _2, ..., the multiplication value obtained by multiplying the Ia ₆ (I
a ₁ G ₁ ), (Ia ₂ G ₂ ),..., (Ia ₆ G ₆ ) are added to all the channels 1 to 6 and the following addition value {I
G is written in the designated position of the corresponding address A.

ΣIG = (Ia ₁ G ₁ ) + (Ia ₂ G ₂ ) +...
+ (Ia ₆ G ₆ ) As described above, each baseband data Ia ₁ , Ia ₂ ,..., Ia of each channel output from the spread spectrum unit.
₆ is 1 in the address terminal of the product-sum operation memory table 24a.
It is input as a 2-bit address value. Then, the corresponding addition value ΣIG stored at the position designated by the address value is read out, output from product-sum operation unit 24, and input to RN filter 27a as channel-multiplexed baseband data Ib. .

The product-sum operation memory table 24b corresponding to the other Q-phase (orthogonal component) has, as shown in FIG.
12 bits each address configuration A _0, A _1, to a position where ... is specified, the corresponding address A _0, A _1, corresponding additional value to _{... (ΣQG) 0, (ΣQG} ) 1, ... are stored.

Each of the added values (ＧQG) ₀ , (ＧQG) ₁ ,.
Is the same as that of the sum-of-products operation memory table 24a corresponding to the I-phase (in-phase component), and a description thereof will be omitted.

Therefore, each baseband data Qa ₁ , Qa of each channel output from the spread spectrum unit is output.
_2, ..., 12 Qa ₆ is a product-sum operation memory table 24b
When applied to the address terminals of bits, the respective baseband data Qa _1, Qa _2, ..., the added value that is stored in the designated position of the address A indicated by the value of Qa ₆ sigma
The QG is read out and output from the product-sum operation unit 24, and is input to the RN filter 27b as channel-multiplexed baseband data Qb.

It should be noted that the process of writing the addition values .SIGMA.IG (= Ib) and .SIGMA. The control unit 26 is implemented.

More specifically, in a state where the control unit 26 has set the R / W signal for each of the product-sum operation memory tables 24a and 24b to the write state, the address A is designated, and each addition value ΣIG is applied to the data terminal. (= Ib) and ΣQG (= Qb), and each addition value ΣIG (= I
b), ΣQG (= Qb) is written.

Further, when the weighting method for multiplexing each channel is changed, each addition value ΣIG written in each of the product-sum operation memory tables 24a and 24b of the product-sum operation unit 24 is used.
(= Ib) and ΣQG (= Qb) are changed, but in such a case, the same processing procedure is performed.

In the control section 26 composed of a computer, the weighting factors G ₁ , G ₂ ,
…, G ₅ , G ₆ , each addition value ΣIG
(= Ib) and ΣQG (= Qb) are stored. For example, when the operator gives weighting coefficients G ₁ , G ₂ ,..., G ₅ , G ₆ for each channel, ΣIG (= Ib) and ΣQG (= Qb) are automatically calculated, and are automatically written into the product-sum operation memory tables 24a and 24b.

The channel-multiplexed baseband data Ib and Qb output from the product-sum operation unit 24 are R
After the waveforms are shaped by the N filters 27a and 27b, they are input to the quadrature modulator 28. The quadrature modulator 28 quadrature modulates the carrier frequency signal with the baseband data Ib, Qb,
Output to the RF (high frequency) interface 29. The output RF interface 29 sends the modulated signal output from the quadrature modulator 28 as a CDMA test signal a to the terminal under test.

The thus configured CD of the first embodiment
In the MA test signal generator, the baseband data Ia (Ia ₁ , Ia _{1)
a 2, ..., Ia 6)} , Qa (Qa 1, Qa 2, ..., Qa
₆ ) are multiplied by weighting factors G ₁ , G ₂ ,..., G ₅ , G ₆ , and the multiplied value (Ia
₁ G ₁ ), (Ia ₂ G ₂ ),..., (Ia ₆ G ₆ ), (Qa
₁ G ₁ ), (Qa ₂ G ₂ ),..., (Qa ₆ G ₆ ) are added over all channels, and the added values (ΣIG) ₀ , (ΣIG) ₁ ,
積 (ΣQG) ₀ , (ΣQG) ₁ ,...
The function 4 is a product-sum operation memory table 2 for each of the I-phase and the Q-phase.
4a and 24b.

Accordingly, since the number of multipliers and adders determined according to the number of channels is not required, the product-sum operation unit 24
Can be dramatically simplified. Specifically, in the case of the above-described six channels, the product-sum operation memory table 24
Each of a and 24b can be realized by a memory element having an 8K address.

Further, since the necessary added value stored is merely read out without actually performing the calculation, the reliability of the output CDMA test signal can be improved.

The weighting factors G ₁ ,
If it becomes necessary to perform the test while changing G ₂ ,..., G ₅ , G ₆ , the control unit 26 operates to use each of the added values {IG , ΣQG and each calculated addition value ΣIG , ΣQG are automatically written into the product-sum operation memory tables 24a, 24b at the designated positions of the corresponding addresses. Therefore, the weight coefficient G for each channel can be easily changed.

However, when the weight is changed, it is not possible to continuously output the transmission code, but the present invention is applied to a mobile terminal test device (for example, a signal tester) which does not need to change the weight on the way. Can be.

(Second Embodiment) FIG. 3 is a block diagram showing a schematic configuration of a CDMA test signal generator according to a second embodiment of the present invention. CDM of the first embodiment shown in FIG.
The same parts as those of the A test signal generator are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part will be omitted.

In the CDMA test signal generator according to the second embodiment, the product-sum operation unit 24 includes one product-sum operation memory table 24c and the product-sum operation memory table 2c.
4c, and a switching circuit 2d disposed after the product-sum operation memory table 24c.
4e.

As shown in FIG. 4, the sum-of-products operation memory table 24c of the CDMA test signal generator of the first embodiment shown in FIG.
It has the same configuration as 24b.

As described above, when the respective values of the baseband data Ia and Qa of each channel after the spread spectrum are equal, the respective added values ΣIG and ΣQG after the addition are also equal.

The switching circuit 24d receives the I signal from the control unit 26.
Each baseband data I after the spread spectrum of each channel inputted to the address terminal of the product-sum operation memory table 24c according to the switching command I / Q corresponding to the phase and the Q phase.
a and Qa are switched by time division.

On the other hand, the switching circuit 24e responds to the switching command I / Q for the I-phase and the Q-phase from the control unit 26, and outputs each addition value output from the data terminal (output terminal) of the product-sum operation memory table 24c. Is the RN assigned to each of the I phase and the Q phase.
The input is switched to the filters 27a and 27b.

The control unit 26 controls each baseband data I,
At twice the sample rate (chip rate) of Q,
The switching circuits 24d and 24e are switched synchronously. Therefore, each of the switching circuits 24d and 24e is an I-phase (in-phase component).
During the period of switching to the side, the product-sum operation memory table 24c stores the baseband data Ia of each channel.
Is input, and the addition value メ モ リ IG (= Ib) is input from the product-sum operation memory table 24c to the RN filter 27a.

Conversely, during a period in which each of the switching circuits 24d and 24e is switched to the Q phase (quadrature component) side, the baseband data Qa of each channel is input to the product-sum operation memory table 24c, and the same From the product-sum operation memory table 24c to the RN filter 27b, the addition value ΣQG (= Q
b) is input.

That is, in the CDMA test signal generator of the second embodiment, one product-sum operation memory table 24c is used by time-sharing the I-phase (in-phase component) and the Q-phase (quadrature component). I am trying to do it. Therefore, the storage capacity required for the product-sum operation unit 24 can be reduced by half compared with the first embodiment.

[0067]

As described above, the CDMA of the present invention
The test signal generator multiplies the spread spectrum test pattern data of each channel by a weighting factor set for the corresponding channel, and adds the multiplied value of each channel over all channels. The sum operation unit (channel multiplex operation unit) is configured by a product-sum operation memory table in which the value of the input test pattern data is used as an address, and the product-sum operation result is stored in the address value.

Therefore, a small and inexpensive channel multiplexing operation unit can be realized with a simple configuration.

Further, the storage contents of the product-sum operation memory table can be rewritten. Therefore, each weight coefficient set for each channel can be easily changed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a CDMA test signal generator according to a first embodiment of the present invention;

FIG. 2 is a diagram showing storage contents of a product-sum operation memory table formed in the CDMA test signal generator.

FIG. 3 is a block diagram showing a schematic configuration of a CDMA test signal generator according to a second embodiment of the present invention;

FIG. 4 is a diagram showing storage contents of a product-sum operation memory table formed in the CDMA test signal generator.

FIG. 5 is a block diagram showing a schematic configuration of a general mobile terminal test apparatus.

FIG. 6 is a block diagram showing a schematic configuration of a conventional CDMA test signal generator.

[Explanation of symbols]

 Reference Signs List 21 test pattern generation unit 22 signal synthesis unit 23 PN pattern generation unit 24 sum-of-products calculation unit 24a, 24b, 24c sum-of-products calculation unit memory table 24d, 24e switching circuit 25 clock generation unit 26 control unit 27a, 27b RN filter 28 ... Quadrature modulator 29 ... Output RF interface

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kazufumi Yuzuki, 2-10-1, Toranomon, Minato-ku, Tokyo NTT Mobile Communications Network Co., Ltd. (72) Inventor Akihiro Higashi 2-chome Toranomon, Minato-ku, Tokyo No. 10-1 NTT Mobile Communication Network Co., Ltd. (72) Inventor Shunsuke Kiyo 2-10-1 Toranomon, Minato-ku, Tokyo F-term (reference) 5K022 EE01 EE02 EE21 EE22 5K067 AA41 BB02 CC10 EE02 LL08

Claims (3)

[Claims] 1. A plurality of test pattern generators for outputting test pattern data comprising a pair of I-phase and Q-phase baseband data for each channel, and a pair of test pattern generators output from each test pattern generator. A spread spectrum unit (22, 23) for multiplying test pattern data consisting of baseband data by PN pattern data having different patterns to spread the spectrum of each test pattern data; The test pattern data including a pair of baseband data of the I phase and the Q phase is multiplied by a weight coefficient set for the corresponding channel, and the multiplied value for each of the I and Q phases of each channel is applied to all the channels. And a sum-of-products operation unit (24) for performing channel multiplexing operation over the carrier frequency signal. A CDMA test signal generator comprising: a quadrature modulator (28) for modulating with I-phase and Q-phase output data of a calculator; and an output unit (29) for outputting an output signal of the quadrature modulator as a CDMA test signal. In the above, the product-sum operation unit (24) assigns, to each address, each combination of all possible values of each baseband data of each channel over all channels, and designates each combination by each address. A pair of sum-of-products operation memory tables (24
a, 24b). A CDMA test signal generator. 2. A plurality of test pattern generators (21) for outputting test pattern data comprising a pair of I-phase and Q-phase baseband data for each channel, and a pair of test pattern generators output from each test pattern generator. A spread spectrum unit (22, 23) for multiplying test pattern data consisting of baseband data by PN pattern data having different patterns to spread the spectrum of each test pattern data; The test pattern data including a pair of baseband data of the I phase and the Q phase is multiplied by a weight coefficient set for the corresponding channel, and the multiplied value for each of the I and Q phases of each channel is applied to all the channels. And a sum-of-products operation unit (24) for performing channel multiplexing operation over the carrier frequency signal. A CDMA test signal generator comprising: a quadrature modulator (28) that modulates the output data of each of the I and Q phases of a calculator; and an output unit (29) that outputs the output signal of the quadrature modulator as a CDMA test signal. In the apparatus, the product-sum operation unit (24) assigns each combination of all possible values of each baseband data of each channel over all channels to each address, and designates each combination by each address. One sum-of-products operation memory table (24c) storing the added value obtained by the combination of the baseband data indicated by the corresponding address at the set position, and using this one sum-of-products operation memory table for the I phase and the Q phase A CDMA test signal generator comprising a switching section (24d, 24e) for use in a time-division manner. 3. An addition value rewriting means (26) for rewriting each addition value at a position designated by each address of the product-sum operation memory table to each addition value when a weight coefficient for each channel is changed. 2. The method according to claim 1, wherein
Or the CDMA test signal generator according to 2.