JP2001339365A - Modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a modulator whose circuit scale and the power consumption are reduced and in which fine adjustment of transmission power is made possible. SOLUTION: A multiplier 11 multiplies transmission data by a spread code and a multiplier 17 multiplies control data by the spread code. A complex arithmetic section 44 applies complex number arithmetic operation of a scramble code to each output of the multipliers 11, 17 to generate data of a real part and an imaginary part by each channel. Raised COS filters 51-54 respectively apply band limit to each of output data of each channel from the complex arithmetic section 44. Multipliers 71-74 multiply output data from the filters 51-54 by gain factors, respectively. An adder 81 sums the data of the real part from the multipliers 71, 73 and an adder 82 sums the data of the imaginary part from the multipliers 72, 74.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator used for wireless communication and the like, and more particularly to a W-CDMA.
(Hybrit Phase) used for (Wideband CDMA)
Shift Keying) modulator.

[0002]

2. Description of the Related Art Conventionally, in a communication system using the W-CDMA system, in reception (communication from a master unit to a slave unit), a transmission channel and a control channel are time-divisionally inserted into the same channel as the transmission channel. Have been. On the other hand, in transmission (communication from the slave unit to the master unit), the HPS
K modulation is used.

[0003] The HPSK modulation is a modulation method in which multi-channel spread data is converted into a vector value having orthogonal components, and this is further rotated using a scramble code. When HPSK modulation is used for normal transmission (single mode), it is composed of two channels, a transmission channel and a control channel. In this state, when the transmission channels are superimposed, a multi mode is set.

[0004] Specific examples of the multi mode include a case where data relating to an image is transmitted at the same time as voice and a case where data relating to a mail is transmitted simultaneously with the voice. At this time,
Since the amount of data to be transmitted differs between voice and image, voice data is transmitted at low speed and image data is transmitted at high speed. This transmission data rate is variable in the range of 15 kbps to 960 kbps, and the chip rate (spreading code rate) is 3.8.
At 4 MHz, one data is spread at a rate of 256 chips to 4 chips.

[0005] In such communication, at the high speed, reception becomes difficult on the receiving side, so that the transmitting side varies the transmission power according to the transmission data rate. That is, the speed of the transmission data rate is proportional to the magnitude of the transmission power, and the transmission power is controlled to increase as the transmission data rate increases, thereby facilitating reception during high-speed communication. These functions were originally entrusted to the high frequency region.
-When the CDMA system is used, the baseband region plays a role to support multi-mode. The transmission gain that makes the transmission power variable is called β, and a voltage is output in the baseband unit. Therefore, the β value is proportional to the transmission data rate and is set at β = 0 to 15 (4 bits).

Next, an example of the configuration of a conventional HPSK modulator will be described with reference to FIGS. FIG.
Shows an example of the configuration of the HPSK modulator in the case of the multi-mode. This HPSK modulator has six transmission channels 1 to 6 for inputting transmission data and one control for inputting control data as shown in FIG. Channel 7 and each transmission data DPDCH inputted to transmission channels 1 to 6
Multipliers 1 to 16 multiply transmission data spreading codes Cd1 to Cd6 by multipliers 11 to 16, respectively. Each output from the multipliers 11 to 16 is
Gain factor βd1 that determines transmission power from 1-26
~ Βd6.

The control data DPCCH input to the control channel 7 is multiplied by the control data spreading code Cc by the multiplier 17, and the output from the multiplier 17 is multiplied by the gain factor βc by the multiplier 27. It has become. The output data of the multipliers 21, 23 and 25 are added by an adder 31, and the added data I is added to an adder 34.
Is output to Multipliers 22, 24, 2
The output data 6 and 27 are added by an adder 32, and the added data Q is multiplied by an imaginary number j by a multiplier 33 and output to an adder 34. The adder 34 arranges the input addition data I on the integer axis, and the multi-bit complex data I
+ JQ is generated and output.

The complex data I + jQ from the adder 34 is
The multiplier 35 multiplies the scramble code Sn and outputs the result. The output data from the multiplier 35 is band-limited by the raised COS filter 36 and output. In FIG. 6, a complex operation unit 37 is configured by the multipliers 33 to 35.

The above is the outline of the configuration of the HPSK modulator in the case of the multi-mode. However, in the detailed explanation of the operation, the HPSK modulator in the case of the single mode as shown in FIG. FIG. 7 will be described. The HPSK modulator shown in FIG. 7 is obtained by omitting the adders 31 and 32 from the HPSK modulator of FIG. 6 and extracting components necessary for two channels for the single mode.

More specifically, the multipliers 11, 17, 2
Reference numerals 1 and 27 are composed of exclusive OR circuits. The multiplier 33, the adder 34, and the multiplier 35
Is composed. The raised COS filter 36 uses a general FIR filter, and can perform calculation by convolution integration. Next, the operation of the HPSK modulator having such a configuration and shown in FIG. 7 will be described.

Now, the transmission data DPDCH1 is the multiplier 1
When it is input to 1, the transmission data DPDCH1 is multiplied by the transmission data spreading code Cd1. Here, the transmission data DPDCH1 has a data rate of 15 kbps or more.
This is 1-bit data of 960 kbps. The spreading code Cd for transmission data has a chip rate of 3.84 MH.
This is 1-bit data of z.

The control data DPCCH is supplied to the multiplier 17
, The control data DPCCH is multiplied by the control data spreading code Cc. Here, the control data DPCCH is 1-bit data having a data rate of 15 kbps. Also, the control data spreading code Cc
Is 1-bit data with a chip rate of 3.84 MHz.

When the output of the multiplier 11 is input to the multiplier 21, it is multiplied by a gain factor βd1 which determines transmission power. When the output of the multiplier 17 is input to the multiplier 27, the output of the multiplier 17 is multiplied by a gain factor βc that determines transmission power. Here, the gain factors βd1 and βc are 2560
It consists of a frame rate of × 15 chips,
Bit data.

The output data I of the multiplier 21 is I = Cd1
Xβd1 × DPDCH1, which is 5-bit data that changes for each chip rate. The output data Q of the multiplier 27 becomes Q = Cc × βc × DPCCH and 1
It becomes 5-bit data that changes for each chip rate. The output data I of the adder 31 shown in FIG.
d1 × βd1 × DPDCH1) + (Cd3 × βd3 × D
(PDCH3) + (Cd5 × βd5 × DPDCH5). The output data Q of the adder 32 shown in FIG.
= (Cc × βc × DPCCH) + (Cd2 × βd2 × D
(PDCH2) + (Cd4 × βd4 × DPDCH4).

The output data I of the multiplier 21 is input to the adder 34, and the output data Q of the multiplier 27 is multiplied by the imaginary data j by the multiplier 33 and input to the adder 34. In the adder 34, the output data I from the multiplier 21 and the output data jQ from the multiplier 33 are added. Therefore, the output data I from the multiplier 21 is output from the adder 34.
Are arranged on the integer axis, and the output data Q of the multiplier 27 is arranged on the imaginary axis.
+ JQ is output.

When the complex data I + jQ is input to the multiplier 35, the complex data I + jQ is multiplied by the scramble code Sn, thereby generating and outputting the complex data I '+ jQ' shifted in phase by (2n + 1) π / 4. Here, the scramble code Sn is complex data having a chip rate of 3.84 MHz, and is composed of 1-bit data. Also,
The complex data I '+ jQ' consists of 6 bits each.
In the case of the multi mode shown in FIG.

In the baseband region, it is difficult to perform calculations using complex numbers. Therefore, the complex operation unit 37 does not perform the complex number operation as described above, but uses the following equation (1):
Data I 'and Q' are calculated in advance by integers as in equation (2). Then, it is general to make a complex number by a quadrature transformer (not shown) in the intermediate frequency (IF) or high frequency (RF) region at the subsequent stage.

I ′ = SIn × I + SQn × Q (1) Q ′ = SIn × Q−SQn × I (2) where SIn is integer data of the scramble code Sn, and SQn is imaginary data of the scramble code Sn. Complex data I ′ + jQ ′ output from multiplier 35
Is band-limited by the raised COS filter 36,
This band-limited output data Iout + jQout is output to a D / A converter (not shown) at the subsequent stage. An FIR filter is used as the raised COS filter 36, and convolution integration is performed. Now, when the impulse length of the FIR filter is 10 chips and the coefficient is 10 bits, even in the case of the single mode, even if it is the single mode, the integer part is 1
10 multipliers of 0 × 6 bits, adder 9 of 15 bits
Is required, and the equivalent is required for the imaginary part.

[0019]

As described above, according to the conventional HPSK modulator, convolution integration must be performed using a multi-bit input FIR filter, and the circuit scale and power consumption increase. There was an inconvenience. Further, the number of bits of the gain factors βd and βc that determine the transmission power is from 0 to 15, making it difficult to fine-tune them.
If the number of bits is increased, there is a problem that a new inconvenience of increasing the circuit scale occurs.

Furthermore, since the band of the data after the complex operation is limited by the complex operation unit 37, the power consumption cannot be reduced even when the number of communication channels such as a single mode is small. Therefore, the present invention has been made in view of the above points,
It is an object of the present invention to provide a modulator capable of reducing the circuit scale and power consumption and finely adjusting transmission power.

[0021]

Means for Solving the Problems In order to solve the above-mentioned problems and achieve the object of the present invention, each of the inventions according to claims 1 to 6 is configured as follows. That is, the invention according to claim 1 includes a spreading code multiplication unit that multiplies transmission data by a spreading code, a complex operation unit that performs a complex operation on a scramble code on an output signal of the spreading code multiplication unit and converts the output signal into complex data. , A filter for band-limiting complex data from the complex operation unit, and a gain multiplication unit for multiplying an output of the filter by a gain factor for determining transmission power.

According to a second aspect of the present invention, in the modulator according to the first aspect, the transmission data, the spreading code,
Each of the scramble codes is 1-bit data. According to a third aspect of the present invention, in the modulator according to the second aspect, the spreading code multiplication unit and the complex operation unit are configured by an exclusive OR circuit.

According to a fourth aspect of the present invention, in the modulator according to the second or third aspect, the filter is a raised COS filter and is constituted by a 1-bit input FIR filter. It is assumed that. According to a fifth aspect of the present invention, in the modulator according to any one of the first to fourth aspects, the modulator further comprises a gain factor generator that generates the gain factor. At the beginning of the operation, at the end of the operation, or when changing the gain factor.
An up / down counter for generating an output corresponding to a set gain factor, and a digital filter for band-limiting the output of the up / down counter.

As described above, in each of the first to fifth aspects of the present invention, the input signal is multiplied by the spread code, and then the scramble code is converted to complex data by performing a complex operation.
This complex data is band-limited. For this reason,
The filter can be a 1-bit input. As a result, the circuit scale of the filter is reduced, the overall circuit size is reduced, and the overall power consumption can be reduced.

In each of the first to fifth aspects of the present invention, the multiplication processing of the gain factor is performed in a portion near the final stage of the modulation processing. For this reason, even if the gain factor for determining the transmission power is greatly expanded, the influence on the circuit is small, and the transmission power can be finely adjusted. Further, according to the fifth aspect of the present invention, since the envelope control is performed when the gain factor is changed, deterioration of the switching spurious can be reduced by the envelope control.

According to a sixth aspect of the present invention, there is provided a spread code for receiving control data relating to a control channel and transmission data relating to at least one transmission channel, and multiplying the control data and the transmission data by respective spreading codes. A multiplication unit, a complex operation unit that performs a complex operation on each output of the spreading code multiplication unit and the scramble code, and expands the data of the real part and the data of the imaginary part for each channel; A raised COS filter that band-limits each output data of the channel, a gain factor multiplier that multiplies each output data of each channel of the filter by a gain factor, and a real part of each channel of the gain factor multiplier. An addition unit that adds data and adds data of each imaginary part of each channel. And it is characterized in that there was example.

As described above, according to the sixth aspect of the present invention,
After multiplying the control data and the transmission data by the respective spreading codes, the scramble code is subjected to a complex operation to develop the data of the real part and the data of the imaginary part for each channel, and then the band is limited by a raised COS filter. I made it. For this reason, the raised COS filter can be input with 1 bit. As a result, the circuit scale of the filter is reduced, the overall circuit size is reduced, and the overall power consumption can be reduced.

Further, in the invention according to claim 6, the multiplication processing of the gain factor is performed in a portion near the final stage of the modulation processing. For this reason, even if the gain factor for determining the transmission power is greatly expanded, the influence on the circuit is small, and the transmission power can be finely adjusted.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of the first embodiment of the modulator of the present invention will be described with reference to the block diagram of FIG. The HPSK modulator according to the first embodiment has a configuration in a single mode, and as shown in FIG.
Multipliers 11 and 17, complex operation unit 44 including multipliers 41 to 43, raised COS filters 51 to 54, envelope generators 61 and 62, multipliers 71 to 74,
At least adders 81 and 82 are provided.

Each of the multipliers 11 and 17 is constituted by an exclusive OR circuit (exclusive OR circuit). Each of the multipliers 41 to 43 is constituted by an exclusive OR circuit or two exclusive NOR circuits. Raised COS filters 51 to 54 are composed of 1-bit input FIR filters. More specifically, the multiplier 11 multiplies the transmission data DPDCH1 input via the transmission channel 1 by the transmission data spreading code Cd1, and outputs data I = Cd1 × DPD.
CH1 is output to the multiplier 41. Here, the transmission data DPDCH1 is, for example, 1-bit data having a data rate of 15 kbps to 960 kbps. The transmission data spreading code Cd is, for example, 1-bit data having a chip rate of 3.84 MHz. For this reason, the output data I of the multiplier 11 becomes 1-bit data and changes every chip.

The multiplier 17 multiplies the control data DPCCH input via the control channel 7 by the control data spreading code Cc, and outputs the output data Q = Cc × DPCC.
H is output to the multiplier 42. here,
The control data DPCCH has a data rate of 15 k, for example.
This is 1-bit data of bps. The control data spreading code Cc has, for example, a chip rate of 3.84 MHz.
Is 1-bit data. Therefore, the output data Q of the multiplier 17 becomes 1-bit data, and changes for each chip.

The multiplier 41 multiplies the output data I from the multiplier 11 by a scramble code Sn to perform a complex number operation, and obtains real part data Ii1 = SIn × I and imaginary part data Iq1 = SQn × Q. , And outputs 1-bit complex data. Here, the scramble code Sn has, for example, a chip rate of 3.84 MH.
z is complex data consisting of 1 bit. SIn is the integer data of the scramble code Sn, and SQn is the imaginary data of the scramble code Sn.

The multiplier 42 outputs to the multiplier 43 output data jQ obtained by multiplying the output data Q from the multiplier 17 by an imaginary number j. The multiplier 43 multiplies the output data jQ from the multiplier 42 by a scramble code Sn to perform a complex number operation, and obtains real part data Qi1.
= SIn × Q and imaginary part data Qq1 = −SQn × I, each of which outputs 1-bit complex data.

The raised COS filters 51 and 52 output multi-bit data Ii2 and Iq2 obtained by band-limiting the output data Ii1 and Iq1 of the multiplier 41. The raised COS filters 53 and 54 output tabit data Qi2 and Qq2 obtained by band-limiting the output data Qi1 and Qq1 of the multiplier 43. In this example, the raised COS filters 51 to 54
Uses a 10-bit impulse response FIR filter, so that its output data Ii2, Iq2, Qi2,
Qq2 has 10 bits.

The envelope generator 61 starts the transmission, stops transmission, or changes the gain factor βd1.
The gain factor βd1 ′ that is smoothly envelope-controlled as described later is output to the multipliers 71 and 72, respectively. When the transmission is started, stopped, or when the gain factor βc is changed, the envelope generator 62 controls the gain factor β that is smoothly controlled as described later.
c ′ is output to multipliers 73 and 74. The above-mentioned gain factors βd1 ′ and βc ′ are factors for determining the transmission power, and in this example, are 7 bits (0 to 6).
The data is extended up to 3) so that the transmission power can be finely adjusted.

The multiplier 71 includes the raised COS filter 5
1 and the envelope generator 61
Is multiplied by a gain factor βd1 ′ to generate multi-bit data Ii3, which is output to the adder 81. The multiplier 72 multiplies the output data Iq2 from the raised COS filter 52 by the gain factor βd1 ′ from the envelope generator 61 to generate multi-bit data Iq3 and outputs it to the adder 82. It has become.

The multiplier 73 includes the raised COS filter 5
3 is multiplied by the gain factor βc ′ from the envelope generator 62 to generate multi-bit data Qi3 and output it to the adder 81. The multiplier 74 multiplies the output data Qq2 of the raised COS filter 54 by the gain factor βc ′ from the envelope generator 62, generates multi-bit data Qq3, and outputs it to the adder 82. It has become.

The adder 81 generates multi-bit output data Iout = Ii3 + Qi3 obtained by adding the output data Ii3 of the multiplier 71 relating to the data channel and the output data Qi3 of the multiplier 73 relating to the control channel. Is output. The adder 82
Output data Iq3 of multiplier 72 over the data channel
And the output data Qq of the multiplier 74 for the control channel.
3 and multi-bit output data Qout =
Iq3 + Qq3 is generated and output.

Further, the output data Iout of the adder 81
And the output data Qout of the adder 82 are each
It is D / A converted by an / A converter (not shown) and sent to a high frequency unit. In addition, the envelope generators 61 and 62, the multipliers 71 to 74, the adders 81 and 82
In the present embodiment, is constituted by a digital circuit, but may be constituted by an analog circuit.

Next, the raised COS filters 51-54
Will be described with reference to FIG. The raised COS filters 51 to 54 are composed of 1-bit input FIR filters, and as shown in FIG. 2, an n-bit shift register 511 and n ROMs (read ROMs).
(Only memory) 512 and an adder 513.

Here, the impulse response length is (n + 1)
An example of an FIR filter of symbol, quadruple zero insertion interpolation will be described. At this time, t = 0 to 3
repeat. Output FIROUT (t) of FIR filter
Is a multi-bit impulse response h (4n
+ T) and the 1-bit output D of the n-bit shift register
The result of the cumulative addition of (n) is obtained.

FIROUT (t) = Σ [h (4n + t) × D (n)] (3) Here, n in the above equation is n = 0 to (the number of symbols−1). That is, when t = 0, FIROUT (0) = h (0) × D (0) + h (4) × D (1) + h (8) × D (2) +.
+ H (4n) × D (n) When t = 1, FIROUT (1) = h (1) × D (0) + h (5) × D (1) + h (9) × D (2) + ...
When + h (4n + 1) x D (n) t = 2, FIROUT (2) = h (2) x D (0) + h (6) x D (1) + h (10) x D (2) +
… + H (4n + 2) × D (n) When t = 3, FIROUT (3) = h (3) × D (0) + h (7) × D (1) + h (11) × D (2) +
The convolution integration is performed at a speed of four times the data rate, that is, + h (4n + 3) × D (n).

Here, since D (n) is 1-bit code data, if inverted data of an impulse response is prepared, FIROUT (t) = Σ [h ′ (4n + t)], and if D (n) = 0, h ′ (4n + t) = h
(4n + t), if D (n) = 1, h ′ (4
n + t) =-h (4n + t).

Therefore, the raised COS filters 51 to 5
4 is an n-bit shift register 5 as shown in FIG.
11, n ROMs 512, and an adder 513. Next, a specific configuration of the envelope generators 61 and 62 will be described with reference to FIG.

The envelope generators 61 and 62 have the same configuration except that the gain factor to be set is different. Therefore, only the configuration of the envelope generator 61 will be described. That is, as shown in FIG. 3, the envelope generator 61 includes a comparator 611, an up / down counter 612, and a digital filter 613.

The comparator 611 compares the set gain factor β with the output of the up / down counter 612 and outputs the result of the comparison. The count value of the up / down counter 612 increases or decreases in accordance with the output from the comparator 611, and the count value is output to the digital filter 613. The digital filter 613 includes an up / down counter 61
2 is band-limited.

The envelope generator 61 having such a configuration
Then, the gain factor βd set in the comparator 611
However, for example, when βold is changed to βnew as shown in FIG. 4, the up / down counter 612 operates,
When the counted value becomes βnew, the up / down counter 612 ends the counting operation. At this time, the output of the up / down counter 612 corresponds to a ramp waveform as shown in FIG. However, since the digital filter 613 limits the band of the ramp waveform,
A waveform corresponding to a smooth waveform as shown in FIG. 4B is obtained.

Note that the envelope generators 61 and 62
When transmission starts, when transmission stops, or gain factor βd
1, since it operates only when βc is changed, power consumption is not required. Next, an operation example of the HPSK modulator according to the first embodiment having such a configuration will be described.

Now, the transmission data DPDCH1 is the multiplier 1
1 is multiplied by the transmission data spreading code Cd1, and the output data I = Cd1 ×
DPDCH1 is output. This output data I becomes 1-bit data and changes every chip. When the control data DPCCH is input to the multiplier 17, it is multiplied by the control data spreading code Cc, and the output data Q = Cc × DPCCH is output from the multiplier 17. This output data Q becomes 1-bit data and changes every chip.

The output data I from the multiplier 11 is
When it is input to 1, a complex number operation is performed by multiplying by a scramble code Sn composed of complex data. As a result of this complex number operation, the multiplier 41 outputs 1-bit real part data Ii1 = SIn × I and 1-bit imaginary part data Iq1 = SQn × Q, respectively, in a raised CO
Output to S filters 51 and 52. Here, SIn is the integer data of the scramble code Sn, and SQn is the imaginary data of the scramble code Sn.

The output data Q from the multiplier 17 is
When input to 2, the imaginary number j is multiplied, and the output data jQ is output from the multiplier 42. The output data j
When Q is input to the multiplier 43, a complex number operation is performed by multiplying the multiplier 43 by a scramble code Sn composed of complex data. As a result of this complex number operation, the multiplier 43 outputs the 1-bit real part data Qi1 = SIn × Q and the 1-bit imaginary part data Qq1 = −SQn × I to the raised COS filters 53 and 54, respectively. Is output.

When the output data Ii1 and Iq1 of the multiplier 41 are input to the raised COS filters 51 and 52, the band is limited here, and the band-limited multi-bit data Ii2 and Iq2 are multiplied by multipliers 71 and 72, respectively. Is output to When the output data Qi1 and Qq1 of the multiplier 43 are input to the raised COS filters 53 and 54, the band is limited here, and the band-limited multi-bit data Qi2 and Qq2 are sent to the multipliers 73 and 74, respectively. Is output.

When the output data Ii2 from the raised COS filter 51 and the gain factor βd1 ′ from the envelope generator 61 are input to the multiplier 71, the multiplier 71 multiplies them and outputs multi-bit data Ii3. And outputs it to the adder 81. Raised CO
When the output data Iq2 from the S filter 52 and the gain factor βd1 ′ from the envelope generator 61 are input to the multiplier 72, the multiplier 72 multiplies them to generate multi-bit data Iq3. Is output to the adder 82.

When the output data Qi2 of the raised COS filter 53 and the gain factor βc 'from the envelope generator 62 are input to the multiplier 73, the multiplier 73 multiplies them to generate multi-bit data Qi3. And outputs it to the adder 81. Raised C
The output data Qq2 of the OS filter 54 and the gain factor βc ′ from the envelope generator 62 are
, The multiplier 74 multiplies them to generate multi-bit data Qq 3, and outputs this to the adder 82.

When the output data Ii3 of the multiplier 71 relating to the data channel and the output data Qi3 of the multiplier 73 relating to the control channel are inputted to the adder 81, the adder 81 adds them and multi-bits them. Output data Io
ut = Ii3 + Qi3 is generated and output to the next stage. Therefore, the adder 81 outputs data obtained by adding each data relating to the real part of each channel.

When the output data Iq3 of the multiplier 72 relating to the data channel and the output data Qq3 of the multiplier 74 relating to the control channel are input to the adder 82, the adder 82 adds them and multi-bits them. Output data Qo
ut = Iq3 + Qq3 is generated and output to the next stage. For this reason, the adder 82 outputs data obtained by adding each data relating to the imaginary part of each channel.

As described above, in the first embodiment, for each data of two communication channels, the spread code is multiplied, and then the scramble code is converted to complex data by performing a complex number operation and converted (developed). Each data of the real part and the imaginary part of the complex data is band-limited. For this reason, the raised COS filters 51 to 54 can be input with one bit, so that the circuit scale of the filter is reduced, the overall circuit size is reduced, and the overall power consumption can be reduced.

Further, in the first embodiment, the multiplication processing of the gain factor, which is a determining factor of the transmission power, is performed in a portion close to the final stage of the modulation processing, so that the gain factor can be easily increased to 4 bits or more. The effect on the circuit is small even if it is expanded. Therefore, fine adjustment of the transmission power is possible. Therefore, the accuracy of the transmission power according to the transmission rate is increased, transmission close to the theoretical value is possible, and the transmission power can be kept constant in each mode.

Further, in the first embodiment, since the envelope control is performed when the gain factor is changed, the deterioration of the switching spurious can be reduced by the envelope control. Next, a configuration of the second exemplary embodiment of the present invention will be described with reference to FIG. The HPSK modulator according to the second embodiment is of a multi-mode case, and as shown in FIG. 5, a configuration of a portion related to transmission channels 2, 3,... Is added to the configuration of FIG. It is.

That is, in the second embodiment, by adding even-numbered transmission channels 2, 4,..., Each transmission channel has a multiplier 12A, a multiplier 42A, and a multiplier 42A, as shown in FIG. 43A, a raised COS filter 53A, a raised COS filter 54A, an envelope generator 62A, a multiplier 73A, and a multiplier 74A are added.

Also, by adding odd transmission channels 3, 5,..., Each of the transmission channels has a multiplier 11A, a multiplier 41A, and a raised COS, as shown in FIG.
A filter 51A, a raised COS filter 52A,
An envelope generator 61A, a multiplier 71A, and a multiplier 72A are added. Since the configuration of the other parts is the same as the configuration of each part of the first embodiment in FIG. 1, the same components are denoted by the same reference numerals and description thereof will be omitted.

In the second embodiment having such a configuration, the operation of each unit relating to the odd transmission channels 3, 5,... Added in accordance with the multimode is performed by the multiplier 11 relating to the transmission channel 1 in FIG. , Multiplier 41, raised C
The operations of the OS filters 51 and 52, the envelope generator 61, and the multipliers 71 and 72 are basically the same as those of the first embodiment.

On the other hand, the operation of each unit related to the even transmission channels 2, 4,... Is different from the transmission data DPDCH2.
Are basically the same as the operations of the respective units, and therefore, the description thereof is omitted. Therefore, in the case of the second embodiment,
The adder 81 adds each data of the real part of each channel output from the multipliers 71, 71A, 73, 73A,
The sum data Iout is output. The adder 82
Adds the data of the imaginary part of each channel output from the multipliers 72, 72A, 74, 74A, and outputs the added data Qout.

As described above, since the second embodiment includes the configuration of the first embodiment, the same operation and effect as those of the first embodiment can be obtained. Further, in the second embodiment, since data processing is performed for each communication channel, it is possible to completely power down data processing of unused channels. Therefore, when the single mode is frequently used, power consumption can be reduced.

[0065]

As described above, claims 1 to 5 are described.
In each of the inventions described above, the input signal is multiplied by the spreading code, and then the scramble code is converted into complex data by performing a complex number operation, and the complex data is band-limited. For this reason, it is possible to input a 1-bit filter, and as a result, the circuit size of the filter is reduced, the overall circuit size is reduced, and the overall power consumption can be reduced.

In each of the first to fifth aspects of the present invention, the multiplication processing of the gain factor is performed at a portion close to the final stage of the modulation process. Even if it is expanded, the influence on the circuit is small, and the transmission power can be finely adjusted. further,
In the invention according to claim 5, since the envelope control is performed when the gain factor is changed, deterioration of the switching spurious can be reduced.

In the invention according to claim 6, the control data and the transmission data are each multiplied by a spreading code, and then a scramble code is subjected to a complex number operation and expanded into real part data and imaginary part data for each channel. After that, the band is limited by the raised COS filter. For this reason, the raised COS filter can be input with 1 bit. As a result, the circuit scale of the filter is reduced, the overall circuit size is reduced, and the overall power consumption can be reduced.

Furthermore, in the invention according to claim 6, since the multiplication processing of the gain factor is performed in a portion near the final stage of the modulation processing, even if the gain factor for determining the transmission power is greatly expanded. The influence on the circuit is small, and the transmission power can be finely adjusted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a specific configuration of a raised COS filter shown in FIG.

FIG. 3 is a block diagram showing an example of a specific configuration of the envelope generator shown in FIG.

FIG. 4 is a waveform chart showing waveforms at various parts of the envelope generator shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a conventional HPSK modulator in a multi-mode case.

FIG. 7 is a block diagram of the HPSK modulator in a single mode.

[Explanation of symbols]

 11, 17 Multiplier 41 to 43 Multiplier 44 Complex operation unit 51 to 54 Raised COS filter 61, 62 Envelope generator 71 to 74 Multiplier 81, 82 Adder 511 Shift register 512 ROM 513 Adder 611 Comparator 612 Up / Down counter 613 Digital filter

Claims (6)

[Claims] A spread code multiplication unit for multiplying transmission data by a spread code; a complex operation unit for performing a complex operation on a scramble code for an output signal of the spread code multiplication unit and converting the output signal to complex data; And a gain multiplying unit that multiplies the output of the filter by a gain factor that determines transmission power. 2. The modulator according to claim 1, wherein the transmission data, the spreading code, and the scrambling code are each 1-bit data. 3. The modulator according to claim 2, wherein the spreading code multiplication unit and the complex operation unit are configured by an exclusive OR circuit. 4. The modulator according to claim 2, wherein the filter is a raised COS filter, and is configured by a 1-bit input FIR filter. 5. The apparatus according to claim 1, further comprising: a gain factor generator configured to generate the gain factor, wherein the gain factor generator is configured to change a gain factor according to a set gain factor when starting the operation, ending the operation, or changing the gain factor. 5. An up / down counter for generating an output, and a digital filter for band-limiting the output of the up / down counter. A modulator as described. 6. control data for a control channel;
Transmission data relating to at least one transmission channel is input, a spreading code multiplication unit that multiplies the control data and the transmission data by a spreading code, respectively, a complex number operation of each output of the spreading code multiplication unit and a scramble code, For each channel, a complex operation unit that expands into real part data and imaginary part data, a raised COS filter that band-limits each output data of each channel from the complex operation unit, and each channel of the filter A gain factor multiplier for multiplying each output data by a gain factor, and an adder for adding data of each real part of each channel of the gain factor multiplier and adding data of each imaginary part of each channel. A HPSK modulator, comprising: