JP2000165200A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a noise by cutting off a peak current flowing to an external power supply resulting from switching in a semiconductor integrated circuit. SOLUTION: The inside of the semiconductor integrated circuit is divided into a circuit 2 with high switching frequency such as a clock tree and other circuit 3, a capacitor 4 is provided between an internal power supply terminal 101 and an internal ground terminal 102 of the circuit 2 with high switching frequency, a power supply interruption means 6 is provided between an internal power supply line 11 of the circuit 2 with high switching frequency and an internal power supply line 10 from an external power supply terminal 8 and the moment the circuit 2 with high switching frequency is switched by the power supply interruption means 6, the connection between the external power supply terminal 8 and the internal power supply terminal 101 is interrupted. Through the configuration above, flowing of an internal power supply current to an external power supply at the moment of switching can be prevented so as to reduce a noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit for reducing power supply noise caused by transistor switching.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit (CMOS integrated circuit), as shown in FIG. 6, a peak current is generated at an external power supply terminal every time switching is performed in synchronization with a clock, which becomes high-frequency noise and causes malfunction of the set. In order to cut this, a filter using a capacitor is conventionally formed on the power supply wiring inside the semiconductor integrated circuit.

[0003]

However, since there is a loss in the characteristics of an actual capacitor, the impedance becomes higher than that of an ideal capacitor at a certain frequency. Therefore, high-frequency components cannot be sufficiently cut at frequencies of several tens of MHz or more. Further, the operating frequency of semiconductor integrated circuits is increasing year by year, and when the high frequency components of noise due to switching increase, it becomes impossible to sufficiently cut the noise.

An object of the present invention is to reduce a noise by cutting a peak current flowing to an external power supply due to switching in such a semiconductor integrated circuit.

[0005]

In a semiconductor integrated circuit according to the present invention, a capacitor is provided between an internal power supply terminal and an internal ground terminal in the semiconductor integrated circuit, and the external power supply terminal is connected to the external power supply terminal at the moment of switching synchronized with a clock. A power supply disconnecting means for disconnecting the connection between the internal power supply terminals is provided.

According to the present invention, a semiconductor integrated circuit capable of cutting a peak current flowing to an external power supply due to switching and reducing noise can be obtained.

[0007]

DETAILED DESCRIPTION OF THE INVENTION According to the first aspect of the present invention, a capacitor is provided between an internal power supply terminal and an internal ground terminal in a semiconductor integrated circuit, and an external power supply terminal is connected to the external power supply terminal at the moment of switching synchronized with a clock. The power supply disconnecting means for disconnecting the connection between the internal power supply terminals is provided, and the connection between the external power supply terminal and the internal power supply terminal is disconnected at the moment of switching synchronized with the clock by the power supply disconnection means. By doing so, the internal power supply current at the moment of switching is prevented from flowing to the external power supply, which has the effect of reducing noise.

According to a second aspect of the present invention, in the first aspect of the present invention, the power supply disconnecting means has a plurality of switches, and connects the external power supply terminal to the internal power supply terminal. The switch is configured to be sequentially connected with a time interval, and when connecting the external power supply terminal and the internal power supply terminal, by connecting the switches sequentially with a time interval, the external power supply is connected. This has the effect that the flowing current is smoothed and noise can be further reduced.

The invention according to claim 3 is the invention according to claim 1, wherein the power supply disconnecting means has a second capacity, and charges the second capacity by the external power supply terminal. ,
The charge of the second capacitor is charged to a capacitor (first capacitor) provided between the internal power supply terminal and the internal ground terminal. By charging the first capacitor, the voltage of the internal power supply becomes higher than the voltage of the external power supply, thereby preventing the switching speed from being impaired. In addition, since the electric charge is always drawn from the external power supply terminal, the external power supply terminal This has the effect that current flows constantly and noise can be greatly suppressed.

An embodiment of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

The semiconductor integrated circuit 1 of the present invention is divided into a circuit 2 having a high switching frequency such as a clock tree and a circuit 3 other than the switching circuit. The internal power supply terminal (VDD2) 101 and the internal A capacitor (first capacitor) 4 is connected between the ground terminal (GND) 102 and the other internal power supply terminal (VDD1) of the circuit 3
The capacitor 5 is connected between 103 and the internal ground terminal (GND) 104.

The semiconductor integrated circuit 1 includes a power supply disconnecting means 6 having one end connected by an internal power supply terminal (VDD2) 101 and an internal power supply line 11 of the circuit 2 having high switching frequency, An external ground terminal (GND) 7 connected to an internal ground terminal (GND) 102 and other internal ground terminals (GND) 104 of the circuit 3 by an internal ground line 9; Internal power supply terminal (VD
D1) 103 and an external power supply terminal (VDD) 8 connected by the internal power supply line 11 are provided. Internal power supply terminal (VDD2) 101 of circuit 2 with high switching frequency
To the internal power supply line 1 from the external power supply terminal (VDD) 8
0, power is supplied via the power supply disconnecting means 6 and the internal power supply line 11. The capacitors 4 and 5 are formed in the internal power supply lines 10 and 11 and the internal ground line 9 of the circuit 2 and the other circuits 3 that frequently switch.

The power supply disconnecting means 6 will be described in detail with reference to FIGS. The power supply disconnecting means 6 disconnects the external power supply terminal 8 from the internal power supply terminal 101 at the moment when the circuit 2 having a high switching frequency switches, thereby preventing a peak current from flowing to the external power supply terminal 8. After disconnecting the connection with the external power supply terminal 8,
By gradually recovering the connection with the external power supply, the current flowing to the external power supply terminal 8 is to be smoothed.

In FIG. 2, reference numeral 17 denotes a clock generator for generating a clock. The clock generator 17 propagates a clock tree from a clock source oscillation signal a output from the clock generator 17 to form a clock signal b. The signal a propagates through the delay element 13 and the exclusive logic element 14, and the external power terminal 8 and the internal power terminal 101
A switch signal c, which is a timing for disconnecting the electrical connection with the switch, is formed. This switch signal c is
As shown in the figure, the clock signal b is formed at a timing earlier than the switching.

In FIG. 2, reference numerals 301 to 305 denote transistors (an example of a switch) interposed between the internal power supply line 11 and the internal power supply line 10 for connecting / disconnecting the internal power supply line 11 and the internal power supply line 10. The transistors 301 to 305 are connected in parallel. 307, 309, 312, 315, 318 are transistors 30
A transistor for turning off each of 1 to 305, 306
, 308, 311, 314, and 317 are transistors 301 to 3
Transistors for turning on 05, 310, 313, 316,
319 is a delay element, and the delay elements 310, 313, 316
, 319, the transistors 308, 311, 314, 317 for turning on the transistors 301 to 305 are turned on with a time delay (later).
.. 305 are sequentially turned on after a certain time.

The operation timing of the power-off means 6 is
This will be described with reference to FIG. Here, an embodiment of a semiconductor integrated circuit operating at 40 MHz is shown, the current consumption is 100 mA, the capacitance of the capacitor 4 is 2500 pF,
The impedance when all of the transistors 301 to 305 are turned on is set to 0.87Ω.

First, near the time t1, the clock source oscillation signal a changes from a low level (hereinafter referred to as L) to a high level (hereinafter referred to as L).
H). Then, a switch signal c is output, and at time t2, the clock signal b changes from L to H,
The circuits 2 having a high switching frequency are simultaneously switched. By outputting the switch signal c at the timing of the time t1, the transistors 307, 309, 312, 315, 3
18 is turned on, the gate voltages of the transistors 301 to 305 are all L, and the transistors 301 to 305 are turned off. Between time t1 and time t3, the external power supply terminal 8
The internal power supply terminal 101 and the internal power supply terminal 101 are completely disconnected, and the circuit 2 with high switching frequency obtains the power supply current from the capacitor 4. Therefore, the potential VDD2 of the internal power supply terminal 101 drops sharply at the timing of time t2. Here, the voltage drops from 5V to 4.5V.

Next, at time t3, the transistor 306 turns on, and the transistor 301 turns on. Here, the impedance of the transistor 301 is 4Ω. About 2.
A current of 125 mA to 100 mA flows to the external power supply terminal 8 for 3 nsec.

Next, 2.3 ns from the timing of time t3
At the timing t4 after the delay of ec, the transistor 308 turns on and the transistor 302 turns on. Here, the combined impedance of the transistors 301 and 302 is 3Ω. 133mA-100m for about 2.2nsec
A current flows to the external power supply terminal 8.

Next, 2.2 ns from the timing of time t4
At the timing t5 after the delay of ec, the transistor 311 turns on and the transistor 303 turns on. Here, the combined impedance of the transistors 301, 302 and 303 is 2Ω. 150 mA to 10 for about 2 nsec
A current of 0 mA flows to the external power supply terminal 8.

Next, 2 nsec from the timing of time t5
At the delayed timing t6, the transistor 314 turns on, and the transistor 304 turns on. Here, the combined impedance of the transistors 301, 302, 303 and 304 is 1.3Ω. 15 for about 2.25 nsec
A current of 0 mA to 100 mA flows to the external power supply terminal 8.

Finally, 2.25 from the timing of time t6
At timing t7 delayed by nsec, the transistor 317
Is turned on, and the transistor 305 is turned on. Here, the combined impedance of the transistors 301, 302, 303, 304, and 305 is 0.87Ω. About 2.7
A current of 150 mA to 34 mA flows to the external power supply terminal 8 for 5 nsec.

As described above, the connection between the external power supply terminal 8 and the internal power supply terminal 101 is cut off by the power supply disconnecting means 6 at the moment when the circuit 2 having high switching frequency switches, so that a peak current flows through the external power supply terminal 8. Noise can be reduced. Further, after the connection to the external power supply terminal 8 is cut off, the transistors 301 to 305 are connected in sequence with a time interval, so that the connection with the external power supply is gradually restored, so that the external power supply current flowing to the external power supply terminal 8 is restored. Is smoothed, and noise can be further reduced.

In the first embodiment, the power supply disconnecting means 6 is constituted by the five transistors 301 to 305. If the power supply disconnecting means 6 is further divided, the current difference generated when each transistor is turned on can be reduced. In addition, the external power supply current can be smoothed. Also, from time t1 to t
Although no current flows during the period 3, it is possible to keep the external power supply current flowing by minimizing this period. [Second Embodiment] FIG. 4 is a circuit diagram of a power supply disconnecting means of a semiconductor integrated circuit in place of the power supply disconnecting means of the first embodiment.

The power supply disconnecting means 6 'according to the second embodiment comprises:
The operation speed is to be guaranteed by preliminarily charging the capacitor 4 with a charge corresponding to the voltage drop due to the switching of the circuit 2 having a high switching frequency.

The power supply disconnecting means 6 'extracts electric charge from the external power supply terminal 8 and alternately injects the electric charge into the capacitor 4.
And two charge injection circuits 50 and 51. In FIG. 4, 501, 502, 503, 504, 507, 508, 509
, 510 are transistors which have the internal timing signal φ1 or the internal timing signal φ input to the gate.
2. Here, as shown in FIG. 5, the internal timing signals φ1 and φ2 are two-phase clocks having a shorter cycle than the clock signal b, and may be formed by an inverter chain or the like independently of an external clock. An appropriate signal such as a circuit may be used.
At the moment when the clock signal b changes, the transistor 50
2 and 508 mask the internal timing signals φ1 and φ2 using the switch signal c (FIG. 2). This is to prevent a current from flowing from the external power supply terminal 8 at the moment when the circuit 2 with high switching frequency switches. In FIG. 4, reference numerals 506 and 511 denote capacitors (second capacitors) for injecting charges into the capacitor 4.

At the timing of internal timing signal φ1 (when high level H), transistors 501, 504, 508
, 509 are on, the charge injection circuit 50 extracts electric charge from the external power supply terminal 8 and charges the capacitor 506, and the charge injection circuit 51 injects electric charge from the capacitor 511 to the capacitor 4. At the timing of the internal timing signal φ2 (when high level H), the transistor 502
, 503, 507, and 510 are on, and the charge injection circuit 51 extracts charges from the external power supply terminal 8 and
511 is charged, and the charge injection circuit 50 injects charge from the capacitor 506 to the capacitor 4.

The operation timing of the power-off means 6 'will be described with reference to FIG. Here, the capacitance of the capacitor 4 is 2000 pF, the capacitance of the capacitors 506 and 511 is 500 pF, and the transistors 502 and 5
The impedances R1, R2 of 03, 508, 509 are each 10Ω, and the impedances R3, R4 of the transistors 501, 504, 507, 510 are 14.44Ω, respectively. 4 having the above values is 107.5.
It has a current supply capability of mA.

First, since the clock signal b switches at time T 1, the circuit 2 with high switching frequency obtains the power supply current from the capacitor 4. Therefore, the internal power supply terminal
The potential of 101 drops sharply at time T1. Here, 5.
The voltage drops from 5V to 5V.

Next, when the internal timing signal φ1 becomes H at the timing of time T2, the capacitor 4 is charged by the charge injection circuit 51. During that time, the charge injection circuit 50 charges the capacitor 506 with the current from the internal power supply line 10 and the internal ground line 9. Here, the period during which the internal timing signal φ1 is H is 2 nsec, during which the charge injection circuit 51 injects a charge of 0.224 n coulombs into the capacitor 4, and the charge injection circuit 50 sets the capacitor 506
To charge. Thereafter, the charge injection circuits 50 and 51 alternately repeat charging of the capacitor 4 and charging of the capacitors 506 and 511. At time T8, the internal power supply terminal 101
Is 5.5 V, the clock signal switches again, and the potential of the internal power supply terminal 101 becomes 5 V.

As described above, in the power supply disconnecting means 6 'in the second embodiment, the voltage of the internal power supply line 11 can be kept higher than the voltage of the external power supply by injecting the electric charge into the capacitor 4. Therefore, the internal power supply line 11
Can be guaranteed at 5V operation speed, even if the voltage of
Loss of switching speed can be prevented. In addition, since one of the charge injection circuits 50 and 51 always extracts electric charge from the external power supply terminal 8, the external power supply terminal 8
, A current flows constantly, and noise can be largely suppressed.

[0032]

As described above, according to the present invention, the internal power supply current at the moment of switching can be prevented from flowing to the external power supply, and noise can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a main part circuit diagram of the semiconductor integrated circuit.

FIG. 3 is a diagram showing an operation timing of a power-off means of the semiconductor integrated circuit.

FIG. 4 is a circuit diagram of power-off means of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an operation timing of a power supply disconnecting means of the semiconductor integrated circuit.

FIG. 6 is a diagram showing operation timing of a conventional semiconductor integrated circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Circuit with high switching frequency 3 Other circuits 4, 5 Capacitor 6, 6 'Power-off means 7 External ground terminal 8 External power terminal 9 Internal ground line 10, 11 Internal power line 13, 310, 313, 316,319 delay element 14 exclusive logic element 17 clock generator 50,51 power supply injection circuit 101,103 internal power supply terminal 102,104 internal ground terminal 301-305 transistors 306,308,311,314,317 transistors 307,309, 312, 315, 318 Transistors 501, 502, 503, 504, 507, 508, 509, 5
10 Transistors 506, 511 Capacitor a Clock source oscillation signal b Clock signal c Switch signal

Claims (3)

[Claims] A power supply disconnecting means for providing a capacitor between an internal power supply terminal and an internal ground terminal in a semiconductor integrated circuit and disconnecting a connection between an external power supply terminal and the internal power supply terminal at the moment of switching synchronized with a clock. A semiconductor integrated circuit, comprising: 2. The power supply disconnecting means includes a plurality of switches, and when the external power supply terminal and the internal power supply terminal are connected, the switches are sequentially connected with an interval. The semiconductor integrated circuit according to claim 1. 3. The power supply disconnecting means has a second capacitance, charges the second capacitance with the external power supply terminal,
2. The semiconductor integrated circuit according to claim 1, wherein the charge of said second capacitance is charged to a capacitance provided between said internal power supply terminal and an internal ground terminal.