JP2000163981A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a satisfactory rewrite operation, regardless of the variance of power voltage in a rewrite mode by generating the voltage via a voltage generating circuit based on the power voltage. SOLUTION: When 1st and 2nd pulse signals of a boosting pulse signal CLK that is generated by a boosting pulse generator 3 are set at 'H' and 'L' respectively, the potential of a power line VPI rises. When the 1st and 2nd pulse signals are set at 'L' and 'H' respectively, the charge value is accumulated and transmitted to the line VPI from a power voltage Vcc. Then a high voltage is supplied to the outside of a positive voltage generation part 4 through the line VPI. Thus, the high voltage set based on the voltage Vcc is outputted to the line VPI from the part 4, and the line VPI is controlled at a fixed voltage level by a 1st voltage control circuit 1. The voltage state applied to a memory cell in a rewrite mode is varied according to the power voltage, and the difference of applied voltage is kept constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an electrically rewritable nonvolatile semiconductor memory device having a voltage generating circuit for generating a potential higher than a power supply voltage.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices are capable of retaining stored information even when the power is turned off, and thus have been widely applied to information systems and communication systems. Above all, the flash EEPROM realizes low cost by reducing the memory cell size by erasing the entire chip or in units of blocks, and the demand is rapidly expanding.

As a new flash memory system, a system using a P-channel transistor in an N-type substrate is known.

FIG. 16 shows a conventional P-type flash EEPROM.
1 shows a schematic cross section of an OM memory cell. This figure 1
6, the memory cell is a conductive semiconductor substrate NW
And a drain region D and a source region S formed of a counter-conduction type high-concentration impurity region formed on the surface of the substrate NW, and a channel region formed between the drain region D and the source region S. A floating gate FG is formed on the gate 71 via a gate insulating film 72, and a control gate CG is formed on the floating gate FG via an interlayer insulating film 73.

In the nonvolatile memory cell having such a structure, the threshold value of the memory cell changes according to the charge stored in the floating gate FG. The injection and extraction of electrons into and from the floating gate FG are performed as follows. That is, the operation of injecting electrons into the floating gate FG is called writing,
The injection of electrons into the floating gate FG increases the threshold value of the memory cell. The operation of extracting electrons from the floating gate FG is called erasing, and by extracting electrons from the floating gate FG, the threshold value of the memory cell decreases.

In a write operation, the source region S is released, and a high voltage of approximately -5 V is applied to the drain region D and approximately 8 V is applied to the control gate CG. Under this voltage condition, a high electric field is generated near the drain region D, and a band-to-band tunnel current is generated between the drain region D and the substrate NW. At this time, electrons flowing from the drain region D to the substrate NW are excited and become hot electrons. The hot electrons are accelerated by the high electric field generated by the high voltage applied to the control gate CG, jump over the potential barrier by the gate insulating film 72, and are injected into the floating gate FG.

In a state where electrons are injected into the floating gate FG, the threshold value of the memory cell is increased, and the characteristics of the memory cell are in a write state shown in FIG.

In the erasing operation, the drain region D is brought into a floating state, a voltage of about 8 V is applied to the source region S and the substrate NW, and a voltage of about-is applied to the control gate CG.
Apply a voltage of 8V. Under this voltage condition, a high electric field is applied to gate insulating film 72 between floating gate FG and source region S, a Fowler-Nordheim tunnel current flows, and electrons accumulated in floating gate FG are transferred to substrate NW. Pulled out. In a state where electrons are extracted from the floating gate FG, the threshold value of the memory cell is low, and the characteristics of the memory cell are as shown in FIG.
The erase state shown in FIG.

In a read operation of data stored in a memory cell, a ground potential is applied to a control gate CG of a selected memory cell as a selection potential, a source region S is set to a power supply voltage Vcc, and a drain region D Is supplied with a potential of about 1V.

Under these voltage conditions, when the selected memory cell is in the written state, the source region S and the drain region D of the memory cell are conductive, and when the selected memory cell is in the erased state, The source region S and the drain region D of the cell become non-conductive. A sense amplifier connected to the memory cell detects a current flowing between the source region S and the drain region D of the selected memory cell, and converts the current into a logical voltage level of "L" or "H". Output.

Next, the configuration of a conventional flash memory array will be described with reference to FIG. Where M (00) -M
(11) is the above-mentioned memory cell having a double gate structure, which is arranged at the intersection of a plurality of word lines WL (0) to WL (1) and a plurality of bit lines BL (0) to BL (1). Have been. Each of the memory cells M (00) to M (11)
Are arranged such that a drain and a source are opposed to memory cells facing each other in the same bit string, and a drain D and a source S of the opposed memory cells are configured to share a diffusion layer NW. The control gates CG of the memory cells on the same row are connected to the corresponding word lines WL (0) to WL (0).
Commonly connected to WL (1). The drain D of the memory cell in the same column is connected to the corresponding bit line BL (0)
To BL (1). The sources S of the memory cells in the same row are commonly connected to a source line SL.

Next, a conventional flash memory device will be described with reference to FIG. Here, reference numeral 120 denotes a memory cell array having the above-described configuration. Row decoder 121
Receives the row address Ra (0: i) and selects one of the word lines WL (0) to WL (n). The column decoder 122 outputs the column address Ca (0: j)
And a selection signal is given to the column switch 123. The column switch 123 receives a selection signal from the column decoder 122, and receives bit lines BL (0) to BL (k).
Are selectively connected to the data bus DB. Data bus DB
Is connected to a read / write circuit 124, and inputs / outputs data to / from a data input / output pin Dio via the read / write circuit 124. IO is the data. Source line switch 125 is connected to positive booster circuit 126 via potential line VP8, and also has source line SL
Through the memory cell array 120. Substrate potential control circuit 127 is connected to positive booster circuit 126 via potential line VP8 and to memory cell array 120 via substrate NW. A negative booster circuit 128 is connected to the row decoder 121 via a potential line VN8 and connected to a read / write circuit 124 via a potential line VN5.

At the time of writing to the memory cell, the positive booster circuit 126 and the negative booster circuit 128 operate, and the potential line VP8
About 8 V and about −5 V to the potential line VN5 are applied to the memory cells, respectively, to perform a write operation. At the time of erasing, the positive booster circuit 126 and the negative booster circuit 128 operate, and about 8 V is applied to the potential line VP8.
About -8 V is output to N8 and is applied to each memory cell to perform erasing.

Next, a method of controlling the boosted voltage in the conventional positive booster circuit 126 and negative booster circuit 128 will be described with reference to FIG. In FIG. 20, VPI denotes a power supply line to which a potential higher than the power supply voltage Vss is supplied. DIO3 is a diode, which is connected to the power supply line VPI and the power supply potential V.
The N-type element is connected to the power supply line VPI, and the P-type element is connected to the power supply potential Vss.

A voltage higher than the power supply voltage Vss is applied to the power supply line VPI. When the potential difference between power supply line VPI and power supply voltage Vss exceeds breakdown voltage Vbd3 of diode DIO3, breakdown current Ibd3 flows from VPI to Vss, and power supply line V
The potential of PI decreases. Also, the breakdown current Ib
Due to d3, the potential of the power supply line VPI is
Is lower than the breakdown voltage Vbd3 of
Breakdown current Ibd3 from PI to Vss stops, and the potential of power supply line VPI rises. By repeating such an operation, the potential of the power supply line VPI is kept constant.

[0016]

FIG. 21 shows voltages at various parts in a memory cell of a flash EEPROM having a conventional configuration.

Here, with reference to FIG. 21, a problem in the above-described nonvolatile semiconductor memory device including the conventional power supply control circuit will be described. In the memory cell of FIG. 21, at the time of writing, -5.5 V is applied to the drain D, and the power supply voltage Vcc (2.5 V to> 3.3 V) is applied to the substrate NW. Here, when the power supply voltage Vcc fluctuates to the higher voltage side, the potential difference ΔV between the drain D and the substrate NW (7.5 V to> 8.
3V) increases, and depending on the voltage, a breakdown occurs in the NW between the drain D and the substrate, which causes a problem that correct writing cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to enable writing to be performed satisfactorily irrespective of fluctuations in power supply voltage during rewriting in a flash memory.

[0019]

According to the present invention, there is provided an electrically rewritable semiconductor device comprising a voltage generating circuit for generating a voltage having an absolute value larger than a power supply voltage. In the storage device, the voltage generated by the voltage generation circuit is configured to be based on the power supply voltage.

According to the present invention, by adopting the above configuration,
(1) In a voltage generation circuit, it is possible to perform generated voltage control corresponding to a change in power supply voltage, and (2) In a nonvolatile semiconductor memory device having a voltage generation circuit, a voltage state applied to a memory cell at the time of rewriting Can be varied according to the power supply voltage.

[0021]

According to the present invention, there is provided an electrically rewritable semiconductor memory device comprising a voltage generating circuit for generating a voltage having an absolute value larger than a power supply voltage. The voltage generated by the circuit is configured to be based on the power supply voltage.

This makes it possible to control the generated voltage in the voltage generation circuit in accordance with the fluctuation of the power supply voltage. Therefore, in the semiconductor memory device provided with the voltage generation circuit, the voltage state applied to the memory cell at the time of rewriting is changed to the power supply voltage. It is possible to keep the difference in the applied voltage at the time of writing of the memory constant regardless of the fluctuation of the power supply voltage, and the writing corresponding to a wide range of power supply voltage is realized. Become.

According to a second aspect of the present invention, a boost controller for controlling an output voltage from the voltage generating circuit is provided between a power supply voltage and a potential line forming an output section of the voltage generating circuit. In this case, a diode is connected.

Thus, when the output voltage from the voltage generation circuit exceeds a certain value, a breakdown current flows through the diode, so that the dynamic output voltage is kept constant.

According to a third aspect of the present invention, the voltage generating circuit is at least one of a positive voltage generating circuit for generating a positive potential and a negative voltage generating circuit for generating a negative potential.

This makes it possible to generate a voltage suitable for a write operation to the memory.

According to a fourth aspect of the present invention, the voltage generating circuit has a positive voltage generating circuit for generating a positive potential and a negative voltage generating circuit for generating a negative potential. The circuit is configured as a power supply at the time of writing.

Thus, a voltage suitable for a write operation to the memory can be generated.

In portable equipment and information equipment, the power supply used has been reduced in voltage in order to reduce the power consumption of the system, and a conventionally used 5V power supply has been reduced to a 3V or less power supply. Efforts to lower it are in progress.

Flash EEPROM according to the present invention
Has a power supply for rewriting inside the chip. That is, a voltage generating circuit for generating a high voltage or a negative voltage to be supplied to the memory cell during the rewriting operation is provided.

FIG. 7 shows a flash EEP according to the present invention.
FIG. 2 shows a block diagram of a ROM. 7, reference numeral 51 denotes a positive voltage generating circuit, which is a conventional positive booster circuit 1 shown in FIG.
26 is provided. A negative voltage generating circuit 52 is provided in place of the conventional negative boosting circuit 128 shown in FIG. 7, other members are the same as those shown in FIG. 19, and are denoted by the same reference numerals as those shown in FIG.

FIG. 2 shows the structure of the positive voltage generating circuit 51. Here, 1 is a first step-up control circuit, 3 is a step-up pulse generation circuit, 4 is a positive voltage generation unit, and 5 is a high voltage control circuit. FIG. 1 shows a configuration of the first boosting control circuit 1. Here, VPI is a first power supply line to which a potential higher than the power supply voltage Vcc is supplied. DIO1 is a diode and the power supply line V
PI is arranged between power supply voltage Vcc, the N-type element is connected to power supply line VPI, and the P-type element is connected to power supply voltage Vcc.
Connected to cc.

FIG. 3 shows a voltage transition of the first boosting control circuit 1. Hereinafter, the operation of the first boosting control circuit 1 will be described with reference to FIGS. This operation itself is described in FIG.
0 is the same as the operation of the conventional circuit shown in FIG.

That is, as shown in FIG.
A voltage higher than the power supply voltage Vcc is applied to I, and the potential difference between the power supply line VPI and the power supply voltage Vcc is changed to a diode DIO.
1, when the voltage of power supply line VPI exceeds a certain positive potential VPP, breakdown current Ibd1 flows from power supply line VPI to Vcc, and the potential of power supply line VPI Decrease. If the potential difference between the power supply line VPI and the power supply voltage Vcc falls below the breakdown voltage Vbd1 of the diode DIO1 due to the breakdown current Ibd1, the breakdown current Ibd1 from the power supply line VPI to Vcc stops, and the power supply line VPI Potential rises.
By repeating such an operation, the positive potential VPP of the power supply line VPI becomes a constant potential difference V
bd1 is kept.

In the present invention, the operation itself of the diode DIO1 of the first boosting control circuit 1 is the same as that of the prior art. On the other hand, the voltage generated by the positive voltage generation circuit 51 having the first boost control circuit 1 varies with the fluctuation of the power supply voltage Vcc by using the power supply voltage Vcc as a reference. However, this is a difference from the conventional one. Details on this point will be described later.

FIG. 5 shows the negative voltage generating circuit 52. Here, 2 is a second booster control circuit, 3 is a booster pulse generator, 6 is a negative voltage generator, and 7 is a negative voltage control circuit.

FIG. 4 shows the configuration of the second booster control circuit 2. Here, VNI is a power supply line to which a negative potential is supplied.
DIO2 is a diode, and includes a power supply line VNI and a power supply voltage Vc.
c and the P-type element is connected to the power line VN
I and the N-type element is connected to the power supply voltage Vcc.

FIG. 6 shows a voltage transition of the second boosting control circuit 2. Here, similarly, when a negative voltage is applied to power supply line VNI and the potential difference between power supply line VNI and power supply voltage Vcc exceeds breakdown voltage Vbd2 of diode DIO2, that is, the absolute value of the voltage of power supply line VNI Exceeds a certain absolute value of the negative potential VNN,
Breakdown current Ibd2 from Vcc to power supply line VNI
Flows, and the potential of the power supply line VNI decreases. When the potential difference between the power supply line VNI and the power supply voltage Vcc falls below the breakdown voltage Vbd2 of the diode DIO2 due to the breakdown current Ibd2, the breakdown current Ibd2 from Vcc to the power supply line VNI stops, and the power supply line VNI Potential rises. By repeating such an operation, the negative potential VNN of the power supply line VNI becomes the power supply voltage VNN.
cc is maintained to have a constant potential difference Vbd2.

In the present invention, the operation of the diode DIO2 of the second boosting control circuit 2 is the same as that of the prior art in the case of the negative voltage. The voltage generated by the generation circuit 52 is
By using the power supply voltage Vcc as a reference, the power supply voltage Vc
The fact that it fluctuates in response to the fluctuation of c is a difference from the conventional one. Details on this point will be described later.

With the above operation, the power supply lines VPI,
Both VNIs are controlled so that the potential difference from the power supply voltage Vcc is kept constant. Next, the operation of the voltage generation circuit 51 will be described in detail. The boosting pulse generation circuit 3 in the power supply generation circuit 51 is configured as shown in FIG. In FIG. 8, cont is a pulse generation control signal, CLK_A is a first boosting pulse signal, CLK_B
Is a second step-up pulse signal. The first boosting pulse signal CLK_A and the second boosting pulse signal CLK_B have phases opposite to each other. These boost pulse signals CL
K_A and CLK_B are generated by the ring oscillator composed of NAND1 and INV1 to INV4 by setting the pulse generation control signal cont to “H”.

FIG. 9 shows the structure of the positive voltage generator 4 and DI
O11 to O16 are diodes, and CAP11 to CAP are capacitors for storing charge for boosting. Diodes DIO11-
16 are connected in series with each other, and the P side of this series circuit is connected to the power supply voltage Vcc, and the N side is connected to the power supply line VPI. The capacitors CAP11 to CAP16 are provided corresponding to the diodes DIO11 to DIO16, respectively.
N11 to N15 are nodes, respectively. Capacity CAP11,
The first boost pulse signal C is supplied to CAP13 and CAP15.
LK_A is supplied and the capacitances CAP12, CAP14, C
The AP 16 is supplied with the second boost pulse signal CLK_B.

FIG. 10 shows the potentials of the nodes N11 to N15 and the power supply line VPI at the time of the positive boosting operation of the positive voltage generator 4, and the arrows in the figure indicate the potentials of the nodes N11 to N1.
5 indicates that the potential of No. 5 is increased by the capacitors CAP11 to CAP16.

Hereinafter, the positive boosting operation will be described with reference to FIGS. 9 and 10. Here, when the first boosting pulse signal CLK_A generated from the boosting pulse generating circuit 3 becomes “H” and the second boosting pulse signal CLK_B becomes “L”, the capacitors CAP11, CAP13, CAP1
The electric charge is stored in 5. That is, nodes N11 and N1
3. The potential of N15 increases. At this time, the electric charge moves in the direction of the nodes N11 to 12, N13 to N14, and N15 to VPI in the forward connection of the diodes, so that the potentials of N12, N14 and the power supply line VPI also increase. Here, the power supply voltage Vcc from the node N11 and the power supply voltage Vcc from N13, which are in a reverse connection relationship of the diode, and N15.
Does not move in the direction from to N14.

Next, when the first boosting pulse signal CLK_A becomes "L" and the second boosting pulse signal CLK_B becomes "H", the capacitors CAP12, CAP14,
Electric charges are stored in the CAP 16. The charge at this time is a charge amount including the charge accumulated by the previous operation. As in the previous operation, the power supply voltage Vcc, which is the forward connection of the diode, is set to 1 from the nodes N11 and N12.
3. The charge moves from N14 to N15. Thereafter, by repeating the same operation, the electric charge becomes Vcc-> N.
11-> N12 ...->N16-> VPI, and a high voltage is supplied to the outside of the positive voltage generator 4 through the power supply line VPI.

As described above, the high voltage based on the power supply voltage Vcc is output from the positive voltage generator 4 to the power supply line VPI. At this time, the power supply line VPI is controlled to a constant voltage by the first voltage control circuit 1. .

FIG. 11 shows the configuration of the high voltage control circuit 5.
Here, RES1 and RES2 are resistors and the power supply line VPI
And the power supply voltage Vcc, and determines the output voltage to the potential line VP8 according to the ratio of the resistance values of the two. That is, when a voltage is applied to the power supply line VPI, a voltage (for example, 8 V) necessary for writing to the memory is output to the potential line VP8 by resistance division. The voltage output to the potential line VP8 can be adjusted by the ratio between the resistors RES1 and RES2.

The potential line VP8 generated as described above
Since the reference voltage is entirely the power supply voltage Vcc, the voltage fluctuates according to the fluctuation of the power supply voltage Vcc.

Next, the operation of the negative voltage generating circuit 52 shown in FIG. 5 will be described. FIG. 12 shows details of the negative voltage generator 6 in the negative voltage generator 52, and FIG. 13 shows the boosting operation of the negative voltage generator 6.

In FIG. 12, DIOs 21 to 26 are diodes, and CAPs 21 to 26 are capacitors for storing charge for boosting. The diodes DIO21 to DIO26 are connected in series with each other. The N side of this series circuit is connected to the reference voltage Vss, and the P side is connected to the power supply line VPI. The capacitors CAP21 to CAP26 are provided corresponding to the respective diodes DIO21 to DIO26. N21 to N25 are nodes, respectively. Capacity CAP21, CAP23, CAP
25 is supplied with a first boosting pulse signal CLK_A, and the capacitors CAP22, CAP24 and CAP26 are supplied with a second boosting pulse signal CLK_B.

FIG. 13 shows each node N in the negative boosting operation.
21 to N25 and the potential of the power supply line VNI.
The arrow in the figure indicates that the potential of each of the nodes N21 to N25 is the capacitance CAP.
It shows that it descends by 21-26.

Hereinafter, the negative boosting operation will be described with reference to FIGS. That is, the negative voltage generator 6
Also in the case, the transfer of electric charge occurs according to the same principle as that of the positive voltage generation unit 4. However, since Vss is the reference voltage, the potential does not rise, and instead, N21->
N22-> ... N26-> The potential of VNI relatively decreases. Since the reference voltage Vss is normally 0 V, a negative voltage is output from VNI.

As described above, the power supply line VN
When a negative voltage is output to I, the power supply line VNI is controlled to a constant negative voltage by the second voltage control circuit 2. FIG.
4 shows a configuration of the negative voltage control circuit 7. Here RES1
1, RES12 and RES13 are resistors and the power supply line VP
It is arranged between I and the power supply voltage Vcc, and determines the output voltages VN5 and VN8 according to the ratio of the respective resistance values.

In such a configuration, when a voltage is applied to VNI, the resistors RES11, RES12, RES1
3 by VN8 and VN5
Voltages required for writing (for example, -8 V and -5 V) are output. Here, the negative voltages output from VN8 and VN5 are resistors RES11, RES12 and RES1.
It can be adjusted by a ratio of 3.

The voltages VN8 and VN5 generated as described above are all set to the reference voltage Vc.
Since the value is c, the values of VN8 and VN5 also fluctuate in accordance with the fluctuation of the power supply voltage Vcc.

Next, the operation of the flash EEPROM circuit according to the present invention will be described with reference to FIG. Here, in the writing state, VP8 is 8V and VN5 is -5V.
Are output from the positive voltage generation circuit 51 and the negative voltage generation circuit 52, respectively. Then, 8 V is applied to the word line WL through the row decoder 121, and -5 V is applied to the bit line BL from the read / write circuit 124 via the column switch 123, and writing is performed on the memory cell array 120.

FIG. 15 shows a cross section of each memory cell in the memory cell array 120. As shown, at the time of writing, -5 V is applied to the drain D and the control gate CG is applied.
8V, the source S is released, and Vcc is applied to the substrate NW. Thereby, writing is performed by injection of electrons by hot electrons based on a band-to-band tunnel current generated near the drain D. Here, the voltages applied to the respective nodes are controlled based on the power supply voltage Vcc as described above. Therefore, the potential difference between the drain D and the substrate NW is always constant, and even if the value of the power supply voltage Vcc greatly varies, the drain D
It does not exceed the breakdown voltage between the substrate and the substrate NW, while ensuring a potential difference of 13 V required for writing.

Here, the voltage values are assumed to be -5 V, -8
Although V and the like are used, it goes without saying that the present invention can be applied to any other values.

[0058]

According to the novel technology disclosed in the present invention, in an electrically rewritable semiconductor memory device provided with a voltage generating circuit for generating a voltage having an absolute value larger than a power supply voltage, Since the voltage generated by the voltage generation circuit is configured to be based on the power supply voltage, the voltage generation circuit can perform the generated voltage control corresponding to the fluctuation of the power supply voltage, and therefore, the semiconductor including the voltage generation circuit In a storage device, a voltage state applied to a memory cell at the time of rewriting can be changed according to a power supply voltage. Therefore, a difference in applied voltage at the time of writing to a memory can be kept constant regardless of a change in power supply voltage. Thus, writing corresponding to a wide range of power supply voltages can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a boost control circuit for a positive voltage generation circuit in a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of the positive voltage generation circuit.

FIG. 3 is a diagram showing a voltage transition of the boost control circuit of FIG. 1;

FIG. 4 is a diagram illustrating a configuration of a boosting control circuit for a negative voltage generating circuit in the semiconductor memory device according to the embodiment of the present invention;

FIG. 5 is a diagram showing a configuration of the negative voltage generation circuit.

FIG. 6 is a diagram showing a voltage transition of the boost control circuit of FIG. 4;

FIG. 7 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

8 is a diagram showing a specific configuration of a boosting pulse generating circuit in the positive voltage generating circuit of FIG. 2;

9 is a diagram illustrating a configuration of a positive voltage generation unit in the positive voltage generation circuit of FIG. 2;

FIG. 10 is a timing chart of a positive boosting operation of the positive voltage generator of FIG. 9;

11 is a diagram showing a configuration of a high voltage control circuit in the positive voltage generation circuit of FIG.

FIG. 12 is a diagram showing a configuration of a negative voltage generator in the negative voltage generator of FIG. 5;

FIG. 13 is a timing chart of a negative boosting operation of the negative voltage generator of FIG. 12;

14 is a diagram showing a configuration of a negative voltage control circuit in the negative voltage generation circuit of FIG.

FIG. 15 is a schematic sectional view of a memory cell in the semiconductor memory device of FIG. 7;

FIG. 16 is a schematic sectional view of a memory cell of a conventional flash EEPROM.

17 is a diagram showing a change in characteristics of the memory cell of FIG. 16 due to rewriting.

FIG. 18 is a diagram showing a configuration of a conventional flash memory array.

FIG. 19 is a block diagram of a conventional flash memory device.

20 is a diagram showing a configuration of a boost voltage control circuit in the flash memory device of FIG. 19;

FIG. 21 is a schematic sectional view of a memory cell in the flash memory device of FIG. 19;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first step-up control circuit 3 step-up pulse generation circuit 4 positive voltage generator 5 high voltage control circuit 51 positive voltage generation circuit Vcc power supply voltage VPI power supply line

Claims (4)

[Claims] 1. An electrically rewritable semiconductor memory device comprising a voltage generation circuit for generating a voltage having an absolute value larger than a power supply voltage, wherein the voltage generated by the voltage generation circuit is the power supply voltage. A semiconductor memory device characterized by being configured to use a voltage as a reference. 2. A diode forming a boost control device for controlling an output voltage from the voltage generating circuit is connected between a potential line forming an output section of the voltage generating circuit and a power supply voltage. 2. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor memory according to claim 1, wherein the voltage generating circuit is at least one of a positive voltage generating circuit generating a positive potential and a negative voltage generating circuit generating a negative potential. apparatus. 4. A voltage generating circuit having a positive voltage generating circuit for generating a positive potential and a negative voltage generating circuit for generating a negative potential, wherein the positive voltage generating circuit and the negative voltage generating circuit are a power supply for writing. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured as: