JP2000163875A - Digital signal processor and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital signal processor and reproducing device in which reproducing continuously the negative maximum value is prevented, and peripheral devices are not destroyed. SOLUTION: A sector 17 switches selectively a one bit digital signal Ds from a signal processing circuit 15 or a mute signal DM from a mute signal generating section 16. And when reset operation is performed for the signal processing circuit 15, the selector 17 is switched to the mute signal DM from the one bit digital signal Ds'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device for performing predetermined signal processing on an input 1-bit digital signal obtained by ΔΣ modulation, and to a digital signal processing device obtained by ΔΣ modulation prerecorded on a recording medium. And a reproducing apparatus for reproducing the 1-bit digital signal.

[0002]

2. Description of the Related Art Recently, it has been considered to apply a 1-bit audio signal obtained by subjecting an analog audio signal to delta-sigma (ΔΣ) modulation to a high-quality sound recorder or data transmission. The 1-bit audio signal obtained by ΔΣ modulation has a sampling frequency of 44.1 KHz compared to a so-called multi-bit digital signal having a sampling frequency of 44.1 KHz and a data word length of 16 bits, which has been used for conventional digital audio. 6 of
It has a very high sampling frequency and a short data word length, such as four times the data word length, and has a wide transmittable frequency band. This one
The bit audio signal is recorded on an optical disc, for example.

In an optical disk on which this 1-bit audio signal is recorded, there are only binary values of +1 and -1.
Is recorded as a digital “1” and −1 is recorded as a digital “0”.

For this reason, digital data "00000"
If a signal such as "0000 ..." is recorded on the optical disc, when the signal is reproduced by a reproducing device (player) and converted into an analog audio signal by a D / A converter, a large noise may be generated. There is a risk of damaging the speaker.

[0005] In a 1-bit audio signal, there is no value corresponding to 0 of PCM data, and in order to completely eliminate sound in the audible band, “+ 1−1 + 1−1 + 1−1 + 1−1.
.., “+ 1 + 1-1-1 + 1 + 1-1-1...” Or “+ 1-1-1 + 1−1 + 1 + 1−1.
Need to play. This silence data is “010101010...” And “11001” in digital signals, respectively.
1001100 ... "or" 10010110 ...
Hereafter, these signals represent no signal, and are referred to as mute patterns.

FIG. 6 shows the configuration of an audio disk player for reproducing the optical disk. The audio disc player 70 reads a 1-bit audio signal recorded on an optical disc 71 by an optical pickup 72 and an RF circuit 73, and performs predetermined signal processing such as error correction and decoding by a signal processing unit 74 to perform a 1-bit music signal. D ₁ is passed to the 1-bit D / A converter 75. The 1-bit D / A converter 75 converts the 1-bit music signal D ₁ into an analog signal by performing waveform shaping and high-frequency noise removal processing, and supplies the analog signal to the output terminal 76.

[0007]

When the power is carelessly turned on and off by the audio disc player 70 shown in FIG. 6, the signal processing unit 74 is reset. While the reset is taking, 1-bit music signal D ₁ is often fixed to 0 or 1. That is, for example, when the power is turned off by the audio disc player 70, if the signal processing unit 74 is reset before the analog music signal output is electrically muted, the
The bit music signal D ₁ is fixed to 0 and “00000000 ·
Is converted into an analog audio signal by the 1-bit D / A converter 45, and a continuous maximum negative value may be reproduced. For this reason, the audio disc player 70 may generate a large noise. ,
There is a risk of damaging the speaker.

In the signal processing section 74, a shift register is often used to adjust the timing of a 1-bit music signal or to perform parallel-serial conversion. However, since this shift register is normally all initialized to 0 or 1 by reset, immediately after the reset of the signal processing unit 74, the sequence of the negative maximum value of “000000000... It will be output.

However, since the signal processing section 74 usually has many setting registers and the like, it is unavoidable that resetting is not performed. Also, in the shipping inspection of the signal processing section 74, an output signal sequence for signal processing is not generated. In order to determine whether or not the output expected value sequence matches the prepared one, an internal register and a frequency divider must be initialized.

[0010] The present invention has been made in view of the above circumstances, and even if the signal processing unit is reset,
It is an object of the present invention to provide a digital signal processing device and a reproducing device that prevent reproduction of a continuous negative maximum value and do not destroy peripheral devices.

[0011]

According to the present invention, there is provided a digital signal processing apparatus for performing predetermined signal processing on an input 1-bit digital signal obtained by ΔΣ modulation. And a no-signal generating means for generating a no-signal 1-bit digital signal representing a no-signal state, wherein the number of occurrences of “0” and “1” within the predetermined period is equal;
The input 1-bit digital signal subjected to the predetermined signal processing by the signal processing means and the non-signal 1 from the non-signal generation means
Switching means for selectively switching between the digital signal and the bit digital signal, and when the signal processing means is reset, the switching means is switched from the input 1-bit digital signal to the non-signal 1-bit digital signal. Switch to.

Here, the signal processing device initializes a register in the signal processing means to a 1-bit digital signal sequence representing a no-signal state when a reset operation is performed on the signal processing means.

[0013] Further, in order to solve the above-mentioned problem, a reproducing apparatus according to the present invention provides a ΔΣ previously recorded on a recording medium.
In a reproducing apparatus for reproducing a 1-bit digital signal obtained by modulation, a reproducing means for reproducing the 1-bit digital signal from the recording medium, and a predetermined signal for the 1-bit digital signal reproduced by the reproducing means Signal processing means for performing processing; "0" and "1" within a predetermined period;
No-signal generating means for generating a no-signal 1-bit digital signal representing a no-signal state in which the number of occurrences is equal to each other, an input 1-bit digital signal subjected to predetermined signal processing by the signal processing means, and the no-signal generation Switching means for selectively switching between a no-signal 1-bit digital signal from the means and a reset operation for the signal processing means;
Control means for controlling switching of the switching means from the input 1-bit digital signal to the non-signal 1-bit digital signal.

Here, when a reset operation is performed on the signal processing means, the reproducing apparatus initializes a register in the signal processing means to a 1-bit digital signal sequence representing a no-signal state.

That is, the present invention outputs a no-signal 1-bit digital signal from the no-signal generating means or a signal equivalent thereto when a reset operation is performed on the signal processing means or immediately after the reset operation.

When the signal processing means is inspected at the time of shipping, other components constituting the digital signal processing device and the reproducing device, for example, a clock divider for supplying a clock to the no-signal generating means, an output terminal side All the flip-flops and the like are initialized, but the reset is not applied to the clock frequency divider and the flip-flops in the normal use.

The signal processing means sets all the built-in shift registers to "0" or "1" when the reset is applied.
, But is initialized along a signal indicating a no-signal state, that is, a mute pattern.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG. 1, data is input from a data input terminal IN11.
Input 1-bit digital signal D _IN obtained by ΔΣ modulation
For, for example, performing predetermined signal processing such as decoding processing for encryption, fader processing, and gain control processing,
1-bit digital output signal D is applied to data output terminal OUT21
A digital signal processing device 10 for supplying _SOUT .

The digital signal processor 10 has a clock input terminal CLK12, a reset terminal RST13, and a test terminal TEST14 in addition to the data input terminal IN11 and the output terminal OUT21.

The digital signal processing device 10 internally performs the above-described predetermined signal processing on the input 1-bit digital signal D _IN input from the data input terminal IN11 to perform 1-bit processing.
Signal processing circuit 15 for outputting a bit digital signal D _S
And a mute signal generator 1 for generating a mute signal D _M , that is, a no-signal 1-bit digital signal representing a no-signal state, in which the number of occurrences of “0” and “1” within a predetermined period is equal.
6 and the 1-bit digital signal D from the signal processing circuit 15
A selector 17 for switching the mute signal D _M from _S and mute signal generation unit 16 selectively, when a reset operation is performed on the signal processing circuit 15, the 1-bit digital signal switching of the selector 17 It switched to mute signal D _M from the D _S '.

The reset operation is performed by supplying "0" corresponding to a reset control signal to a reset terminal RST13 from a controller (not shown).

The digital signal processing device 10 includes an OR circuit 18 having an inverting input terminal 18H, a clock frequency divider 19 having a reset terminal 19R, and a flip-flop 20 having a reset terminal 20R. ing.

Here, the input 1-bit digital signal D
A ΔΣ modulator that generates _IN will be described with reference to FIG. The ΔΣ modulator 23 includes an adder 25, an integrator 26,
It comprises a one-bit quantizer 27 and a one-sample delay unit 29. The added output of the adder 25 is supplied to an integrator 26, and the integrated output from the integrator 26 is a 1-bit quantizer 27
Supplied to The quantized output of the one-bit quantizer 27 is derived from an output terminal 28, while the one-sample delay 29
, Is fed back to the adder 25, and is added to the analog audio signal supplied from the input terminal 24. The added output from the adder 25 is integrated by the integrator 26. Since the integrated output from the integrator 26 is quantized every sample period by the 1-bit quantizer 27, it is possible to output 1-bit quantized data, that is, the 1-bit digital signal from the output terminal 28. it can.

In the signal processing circuit 15 in FIG.
It contains the shift register 30 shown in FIG. The output signal of the shift register 30 is connected to the output of the signal processing circuit 15.

The shift register 30 is a serial input / serial output type shift register in which flip-flops 32, 34, 36 with reset terminals R and flip-flops 33, 35, 37 with preset terminals PR are alternately connected.

The mute signal generating section 16 uses a combinational circuit for the frequency-divided clock output from the clock frequency divider 19 and uses "555555 (H) ...", ie, "010101".
.. "Are generated.

A clock having a predetermined frequency is input to a clock input terminal CLK12 of the digital signal processing device 10 shown in FIG. When a reset operation is performed, “0” is input from a controller (not shown) to the reset terminal RST13. “1” is input to the test terminal TEST14 when performing inspection at the time of collection. Data output terminal
The 1-bit output signal D _SOUT output from OUT21 is D /
It is supplied to the A converter.

The operation of the digital signal processing device 10 having the above-described configuration will be described below for the case of inspection at the time of shipment and the case of normal use.

At the time of shipment, before mounting the digital signal processing device 10 as an IC in, for example, an audio disc player or the like, which will be described later, an inspection is performed to determine whether the digital signal processing device 10 normally operates in synchronization with a clock. The clock divider 19 divides the clock supplied to the clock input terminal CLK12 by, for example, 1 /
The frequency is divided by 2 and supplied to the mute signal generator 16. The mute signal generator 16 outputs 1 /
A mute signal is generated in synchronization with the divide-by-2 clock. At this time, since it is determined that the mute signal is generated based on either the rising edge or the falling edge of the clock, the falling or rising edge of the edge must be determined accurately. Therefore, the clock divider 19 must be initialized at the time of inspection. The same applies to the initialization of the flip-flop 20.

When the digital signal processing device 10 is inspected at the time of shipment, a controller (not shown) is connected to a test terminal TEST.
14 is supplied with "1". In this state, the reset terminal RS
When "0" is supplied to T13, the output of the OR circuit 18 becomes "0". As a result, the clock divider 19 and the flip-flop 20 are initialized, and a predetermined test can be performed.

On the other hand, during normal use, in the digital signal processor 10, the test terminal TEST14 is fixed to "0". The selector 17, muting from the mute signal generating unit 16 when the select 1-bit digital signal D _S from the signal processing circuit 15 when the signal is "1" which is input to the reset terminal RST 13, "0" selects the signal D _M.

During normal use, when "0" is input to the reset terminal RST13 from the controller and the digital signal processing device 10 is reset, the output of the OR circuit 18 remains "1". The frequency divider 19 and the flip-flop 20 are not initialized, and only the signal processing circuit 15 is initialized. In the shift register 30 shown in FIG. 3 in the signal processing circuit 15, the flip-flops 32, 34 and 36 with the reset terminal R are initialized to "0", and the flip-flops 33 and 3 with the preset terminal PR.
5, 37 are initialized to "1", and the other registers are initialized to predetermined values. The selector 17 selects the mute signal D _M from the mute signal generator 16.

As a result, the reset terminal RST13 becomes "0"
During it, from 1-bit music signal output terminal OUT21 continuously output mute signal D _M is silence.

Next, the reset operation is complete, when the "1" to the reset terminal RST13 from the reset state is input, the selector 17 selects the 1-bit digital signal output D _S from the signal processing circuit 15. This signal processing circuit 15
Is provided with a shift register 30. Since the shift register 30 has been initialized according to the mute pattern at the time of the previous reset, when the reset is released and the shift operation is performed, the initialized data string is output.

Here, the timing at which the register in the signal processing circuit 15 is initialized to a 1-bit digital signal sequence representing a no-signal state is such that the reset of the signal processing circuit 15 is released and the switching of the selector 17 is performed by the input 1-bit signal. What is necessary is just before returning to the digital signal side.

Thus, the 1-bit music signal output terminal OUT
21 outputs a signal equal to the mute signal until steady data comes out even after the reset is released.

Note that the mute signal generator 16 outputs "cc
ccccc (H)... ", ie," 110011001
... May be generated. Also, a mute signal with a mute pattern of “100.
", That is," 1001011010010110 ...
A mute signal "" may be generated.

If the mute signal generator 16 is, for example, "969"
6969 (H)... ", Ie," 10010111010
When the mute signal “01010...” Is generated, the configuration of the shift register provided in the signal processing circuit 15 is changed to the shift register 40 as shown in FIG.

The shift register 40 has a preset terminal P
R flip-flop 42 with R, D flip-flops 43 and 44 with reset terminal R, D flip-flop 45 with preset terminal PR, D flip-flop 46 with reset terminal R, and preset terminal P
This is a serial input serial output type shift register in which D flip-flops 47 and 48 with R and a D flip-flop 49 with reset terminal R are connected in series.

In normal use, when "0" is input to the reset terminal RST13 and the digital signal processing device 10 including the signal processing circuit 15 having the shift register 40 shown in FIG. 18 remains at "1", the clock divider 19 and the flip-flop 20 are not initialized and the signal processing circuit 15
Only are initialized. In the shift register 40 of FIG. 4 in the signal processing circuit 15, the flip-flops 42, 45, 47, and 48 with the preset terminal PR are initialized to "1", and the flip-flops 43 and 44 with the reset terminal R are reset.
46 and 49 are initialized to "0", and the other registers are initialized to predetermined values. The selector 17 selects the mute signal D _M from the mute signal generator 16.

As a result, the reset terminal RST13 becomes "0"
, "1969969 (H) ...", ie, "1001" from the 1-bit music signal output terminal OUT21.
011010010110 ... "mute signal D _M continues to be output that.

Next, the reset operation is complete, when the "1" to the reset terminal RST13 from the reset state is input, the selector 17 selects the 1-bit digital signal output D _S from the signal processing circuit 15. This signal processing circuit 15
Is provided with a shift register 40. In the shift register 40, since each register was initialized along the mute pattern "96969 (H)..." At the time of the previous reset, the shift register 40 was initialized when the reset was released and the shift operation was performed. Output data strings.

Thus, the 1-bit music signal output terminal OUT
From 21, the initialization signal is equal to the mute signal D _M until after a reset release also comes out constant data is output as the signal D _SOUT.

As described above, according to the digital signal processor 10 shown in FIG. 1, the mute signal from the mute signal generator 16 can be output when the reset operation is performed on the signal processing circuit 15 or immediately after the reset. . For this reason, even if the signal processing circuit 15 is reset, it is possible to prevent the continuous reproduction of the negative maximum value from being reproduced, and the peripheral device is not destroyed.

When the digital signal processing device 10 is inspected at the time of shipment, a clock frequency divider 19 for supplying a clock to other units constituting the digital signal processing device, for example, a mute signal generating unit 16, an output terminal side Are initialized, but the clock divider 19 and the flip-flop 20 are not reset during normal use.

Since the signal processing circuit 15 initializes the built-in shift register 30 or 40 according to the mute pattern when the reset is applied, the mute signal is output when the reset is released and the shift operation is performed. Is done. As a result, a mute signal is output from the 1-bit music signal output terminal OUT21 until steady data comes out even after reset release.

The digital signal processing device 10 is preferably applied to an audio disc player 51 as shown in FIG. Specifically, the audio disc player 51 is used as a second signal processing unit that performs a decoding process, a fader process, and the like for encryption. Hereinafter, the digital signal processing device 10 is referred to as a second signal processing unit 1.
Description will be made assuming 0.

This audio disc player 51
A 1-bit audio signal obtained by ΔΣ modulation recorded in advance on the optical disk 52 is reproduced. For this reason,
An optical pickup 53 for reading an RF signal from an optical disc 52; an RF circuit 54 for shaping the read RF signal by the optical pickup 53 or amplifying a focus error signal FE or a tracking error signal TE; EFM + demodulation processing and R
EC called S (Read Solomon)-PC (Product Code)
A first signal processing unit 55 that performs C processing, the second signal processing unit 10, and a 1-bit D / A converter that converts a 1-bit digital signal from the second signal processing unit 10 into an analog audio signal 56. An analog audio signal from the 1-bit D / A converter 56 is supplied to an output terminal 5
7 is supplied.

The audio disc player 51
Is the focus error signal F amplified by the RF circuit 54.
E. Servo circuit 58 for generating focus servo, tracking servo and thread servo signals for optical pickup 53 based on tracking error signal TE.
A drive circuit 59 for driving the optical pickup 53 based on the servo signals from the servo circuit 58; and a spindle motor 60 for rotating the optical disk 52 by the drive circuit 59.

The audio disc player 5
1 decodes a subcode such as time information demodulated by the first signal processing unit 55 to control each unit, and sends a reset signal RST / to a second signal processing unit (digital signal processing unit) 10.
A system controller 61 that supplies a test signal TEST to control switching of the selector 17 shown in FIG. 1 inside the second signal processing unit 10, a display unit 62 connected to the system controller 61, and an input operation from the user. And a key operation unit (key) 63 for receiving.

The second signal processing section 10 is connected to a DRAM 64 serving as a buffer for performing the second signal processing while storing the processing signal from the first signal processing section 55.

The detailed configuration of the second signal processing unit 10 is the same as the configuration of the digital signal processing device 10 shown in FIG.
That is, the signal processing circuit 15 that performs predetermined signal processing, for example, decoding processing or fader processing for encryption, on the processing signal from the first signal processing unit 55, the mute signal generation unit 16, and the selector 17 Become. Also,
An OR circuit 18 having an inverting input terminal 18H, a clock frequency divider 19 having a reset terminal 19R, and a flip-flop 20 having a reset terminal 20R are provided.

When the audio disc player 51 is normally used, a system reset is inadvertently performed. When "0" is input to the reset terminal RST13 from the system controller 61, the output of the OR circuit 18 becomes " Since it remains at 1 ", the clock divider 19 and the flip-flop 20 are not initialized, and only the signal processing circuit 15 is initialized. In the signal processing circuit 15, in the shift registers 30 and 40 shown in FIGS. 3 and 4, the flip-flops with the reset terminal R are initialized to “0”, and the flip-flops with the preset terminal PR are set to “1”. Initialized, other registers are initialized to predetermined values. The selector 17 selects the mute signal D _M from the mute signal generator 16.

As a result, the reset terminal RST13 becomes "0".
During it, from 1-bit music signal output terminal OUT21 continuously output mute signal D _M is silence.

Next, the reset operation is complete, when the "1" to the reset terminal RST13 from the reset state is input, the selector 17 selects the 1-bit digital signal output D _S from the signal processing circuit 15. This signal processing circuit 15
Is provided with a shift register 30 or 40. In the shift register 30 or 40, since each register is initialized along the mute pattern at the time of the previous reset, when the reset is released and the shift operation is performed, the data string as initialized is output. .

Thus, the 1-bit music signal output terminal OUT
From 21, the mute signal _DM is output even after the reset release until the steady data comes out. These mute signals are converted into analog signals by a 1-bit D / A converter 56 and supplied to an output terminal 57.

As described above, according to the audio disc player 51 shown in FIG. 5, when the signal processing circuit 15 of the second signal processing section 10 is reset, the mute signal from the mute signal generation section 16 is output. An analog signal is output from the output terminal 57.

Since the signal processing circuit 15 initializes the built-in shift register 30 or 40 according to the mute pattern when the reset is applied, when the reset operation is canceled and the shift operation is performed, the shift operation is equal to the mute signal. A signal is output. This allows 1-bit music signal output terminal OU
From T21, a mute signal is output until steady data comes out even after reset release.

Therefore, even when a reset operation is performed on the signal processing circuit 15 or after the reset is released, it is possible to prevent the continuous reproduction of the negative maximum value from being reproduced, and the peripheral device is not destroyed.

[0060]

According to the present invention, it is possible to prevent the continuous reproduction of the negative maximum value from being reproduced when the reset operation is performed or immediately after the reset is released. Therefore, when a system reset is inadvertently applied or when the power is turned off, a huge noise is not generated and peripheral devices are not destroyed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 shows an input 1 supplied to the digital signal processing device.
FIG. 3 is a block diagram illustrating a detailed configuration of a ΔΣ modulator that generates a bit digital signal.

FIG. 3 is a circuit diagram showing a specific example of a shift register inside a signal processing circuit constituting the digital signal processing device.

FIG. 4 is a circuit diagram showing another specific example of the shift register.

FIG. 5 is a block diagram showing a configuration of an audio disc player using the digital signal processing device shown in FIG. 1;

FIG. 6 is a block diagram showing a configuration of a conventional audio disc player.

[Explanation of symbols]

10 digital signal processing device, 15 signal processing circuit, 1
6 Mute signal generator, 51 audio disc player, 61 system controller

Claims (6)

[Claims] 1. A signal processing means for performing predetermined signal processing on an input 1-bit digital signal obtained by ΔΣ modulation, wherein the number of occurrences of “0” and “1” within a predetermined period is made equal.
A no-signal generating means for generating a no-signal 1-bit digital signal indicating a no-signal state; an input 1-bit digital signal subjected to predetermined signal processing by the signal processing means; and a no-signal 1 from the no-signal generating means.
Switching means for selectively switching between a digital signal and a bit digital signal, wherein when the signal processing means is reset, the switching means is switched from the input 1-bit digital signal to the no-signal 1-bit digital signal. A digital signal processing device characterized by controlling. 2. The method according to claim 1, wherein when a reset operation is performed on the signal processing means, a register in the signal processing means is initialized to a 1-bit digital signal sequence representing a no-signal state. Digital signal processing equipment. 3. The timing of initializing a register inside the signal processing means to a 1-bit digital signal sequence representing a no-signal state is such that the reset of the signal processing means is released and the switching of the switching means is performed by the input one-bit signal. 3. The digital signal processing apparatus according to claim 2, wherein the processing is performed before returning to the digital signal side. 4. A reproducing apparatus for reproducing a 1-bit digital signal obtained by ΔΣ modulation recorded in advance on a recording medium, comprising: reproducing means for reproducing the 1-bit digital signal from the recording medium; A signal processing means for performing predetermined signal processing on the reproduced 1-bit digital signal; and making the number of occurrences of “0” and “1” within a predetermined period equal.
A no-signal generating means for generating a no-signal 1-bit digital signal indicating a no-signal state; an input 1-bit digital signal subjected to predetermined signal processing by the signal processing means; and a no-signal 1 from the no-signal generating means.
Switching means for selectively switching between bit digital signals; and when the signal processing means is reset, switching of the switching means is controlled from the input 1-bit digital signal to the no-signal 1-bit digital signal. A reproducing device comprising: 5. The signal processing means according to claim 4, wherein when a reset operation is performed on said signal processing means, a register in said signal processing means is initialized to a 1-bit digital signal sequence representing a no-signal state. Playback device. 6. A timing for initializing a register in the signal processing means to a 1-bit digital signal sequence representing a no-signal state is such that the reset of the signal processing means is released and the switching of the switching means is performed by the control means. Input 1 above
6. The reproducing apparatus according to claim 5, wherein the reproduction is performed before returning to the bit digital signal side.