JP2000163461A - Timing simulator and timing simulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately and speedily specify delay data including the internal delay time of cells corresponding to the wiring form of cells by specifying the delay data including the internal delay time of cells from parameters including the number of branches and load capacity of wiring connected to the post step of cells. SOLUTION: This timing simulator is composed of a display, keyboard, mouse and control part with a built-in hard disk storing the net list or formula of a semiconductor integrated circuit. Concerning such a timing simulator, the formula specifying the relation between the load capacity and internal delay time Td of cells 50 is prepared by the values of a number (n) of branches of wiring connected to the rear step of cells 50. Then, the number (n) of branches and load capacity of wiring connected to the post step of respective cells 50 are found from the net list of the semiconductor integrated circuit described at a gate level and according to the prepared formula, for each cell 50, the internal delay time Td is specified from the found number (n) of branches and load capacity of wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing simulator and a timing simulation method for executing a timing simulation for specifying an internal delay time _Td of each cell from a netlist of a circuit described at a gate level.

[0002]

2. Description of the Related Art Conventionally, a timing simulator has been known as one of analysis tools used in designing a semiconductor integrated circuit. The timing simulator is an analysis tool used when obtaining the internal delay time _Td of a cell and the output through _Tout of a signal from a netlist of a circuit described at a gate level.

[0003] Figure 14 is a cell 500 having a wiring load capacitance C represented by the pie-shaped model in a subsequent stage, the signal input through T _in to input node 501 of the cell 500,
The signal of the output through _Tout output from the output node 502 and the internal delay time _Td of the cell 500 are shown. The internal delay time _Td is the time required for a signal to pass through a cell. The load capacitance C refers to the sum of the wiring capacitances to one or more cells connected downstream of the cell of interest. The input slew T _in or output through T _out, the level of the signal output from the input signal or cell cell, L the H, or, when the transition from L to H, the level of the signal is given (For example, in the case of L = 0v and H = 5v, the range of 0.5v to 4.5v).

In a timing simulator, the following two methods are used to specify delay data including at least the internal delay time _Td of a cell from parameters including at least a load capacitance C obtained from a netlist of a circuit described at a gate level. Methods are known.

In the first method, a primary expression for specifying the internal delay time Td is created from the load capacitance C from the circuit simulation result, and the load capacitance C is obtained from a netlist of the semiconductor integrated circuit described at the gate level. According to the linear equation created above, the internal delay time _Td of the cell is obtained from the load capacity C of each cell obtained above (for example, Nishikubo, "Introduction to Circuit Simulator SPICE", p16,
(See Japan Industrial Technology Center publication.)

The second method, advance to create a table that identifies the internal delay time of the cell from the circuit simulation results from the load capacitance C and input through T _in T _d and output through T _out, written at the gate level The load capacitance C and the input slew T _in of each cell are obtained from the netlist of the circuit, and the internal delay time T of the cell is calculated based on the load capacitance C and the input slew T _{in of the} obtained cell by referring to the table created above.
a method of obtaining the _d and output through T _out (e.g., see JP-A 9-319776 JP).

[0007]

In the conventional timing simulator, the load capacitance C of the cell of interest is obtained based on the total wiring length L of at least one cell connected to the subsequent stage, and the obtained load capacitance C is obtained. C, or, from the load capacitance C and input through T _in, the internal delay time of the cell T _d, or had to identify the internal delay time T _d and output slew T _out.

However, the load capacitance C varies depending not only on the total length L of wirings up to one or more cells connected in the subsequent stage, but also on the value of the number n of branches of the wiring connected in the subsequent stage. Hereinafter, when the wiring length to the cell connected to the subsequent stage is fixed at 12 mm and the form of the wiring is variously changed, the output through _Tout and the internal delay time _{Td of the} cell obtained by the actual circuit simulation are obtained. Is considered.

[0009] As shown in FIG.
When a 1 mm long wiring 803 represented by a pie-shaped wiring model element having a capacity of 0.1642 pf is connected in 12 stages in parallel, that is, the number of branches n = 12
In this case, the value of the output slew T _out is t _out, and the value of the internal delay time T _d of the cell is t _d .

[0010] As shown in FIG.
01, the same wiring as the wiring 803 having a length of 1 mm
When the serially connected ones are connected in parallel in six stages, that is, when the number of branches of the wiring connected in the subsequent stage is n = 6, the output through T _out is 1.001 × t _out , and the internal delay time T of the cell
_d was 0.996 × t _d .

As shown in FIG. 15C, the cell 8
01, the same wiring as the wiring 803 having a length of 1 mm
When the serially connected ones are connected in parallel in four stages, that is, when the number of branches of the wiring connected in the subsequent stage is n = 4, the output through T _out is 1.005 × t _out and the internal delay time T of the cell
_d became the 0.989 × t _d.

As shown in FIG. 16A, the cell 8
01, when the same wiring as the 1 mm-long wiring 803 shown in FIG. 15A is connected in series with four connected in series, that is, the number of branches of the wiring connected to the subsequent stage The output slew T _out when n = 3 is 1.008 ×
t _out, the internal delay time T _d of the cell, became the 0.979 × t _d.

As shown in FIG. 16B, the cell 8
01, the same wiring as the 1 mm long wiring 803 shown in FIG. 15A is connected in two stages in parallel, ie, the number of branches of the wiring connected to the subsequent stage. output through T _out of the case of n = 2 is, 1.020 ×
t _out, the internal delay time T _d of the cell, became the 0.951 × t _d.

As shown in FIG. 16C, the cell 8
01, the output through when the same wiring as the 1 mm long wiring 803 shown in FIG. 15A is connected in series, that is, when the number of branches of the wiring connected at the subsequent stage is n = 1. T _out is 1.063 × t _out , the internal delay time T of the cell
_d was 0.800 × t _d .

As described above, even if the total length L of the wiring connected to the subsequent stage of the cell 801 is the same, the difference in the value of the branch number n of the wiring connected to the subsequent stage causes a difference _in the value of the output through T _in . There is a difference of about 6% and a difference of about 20% in the internal delay time _Td of the cell. Thus, seeking load capacitance C from the sum L of the wiring length connected to the rear stage of the cell, the calculated load capacitance C internal delay time of the cells T _d or based on, the internal delay time T _d and the output of the cell in the above conventional timing simulator identifies the through T _out, it is impossible to obtain accurate simulation results.

It is an object of the present invention to provide a timing simulator for accurately and promptly specifying delay data including the internal delay time _Td of a cell in accordance with the number of branches of a wiring connected to a subsequent stage of the cell. And

[0017]

A first timing simulator according to the present invention uses at least parameters including a branch number n and a load capacitance C of a wiring connected to a subsequent stage of a cell.
Specifying means for specifying delay data including at least the internal delay time _Td of the cell; and determining the number of branches n and the load capacitance C of the wiring connected to the subsequent stage of each cell from a netlist of the semiconductor integrated circuit described at the gate level. The delay means including at least the internal delay time _Td of the cell is specified from the parameters including at least the number of branching lines n and the load capacitance C obtained by the analysis means by the analysis means to be obtained and the identification means for each cell. And timing simulation means for executing a timing simulation.

A second timing simulator according to the present invention, in the first timing simulator, wherein, as the specifying means, the load capacitance C is used to determine the internal delay time of the cell according to the number of branches n of the wiring connected to the subsequent stage of the cell. A storage device for storing a plurality of formulas for specifying T _d , wherein the timing simulation means includes, for each cell, a branch number n of the wiring determined by the analysis means among the plurality of formulas stored in the storage device; According to the formula corresponding to
, The internal delay time _Td is specified as delay data.

The third timing simulator of the present invention is the above-mentioned second timing simulator, further comprising a branch number n of a wiring connected to a succeeding stage of each cell from a netlist of the semiconductor integrated circuit described at a transistor level. The circuit simulation means for executing the circuit simulation for calculating the load capacitance C and the internal delay time _Td of the cell, and the result of the circuit simulation by the circuit simulation means, for each value of the branch number n of the wiring connected to the subsequent stage of the cell. The present invention is characterized in that it comprises formula formulating means for preparing a plurality of formulas for specifying the internal delay time _Td of the cell from the load capacity C, and storing the prepared formulas in the storage device.

The fourth timing simulator of the present invention is the first timing simulator according to the first timing simulator, wherein, as the specifying means, the load capacitance C and the input through T _in are determined for each value of the branch number n of the wiring connected to the subsequent stage of the cell. A storage device for storing a plurality of tables for specifying the internal delay time _Td and the output slew _Tout of the cell, wherein the timing simulation means includes, for each cell, among the plurality of tables stored in the storage device, refers to the table corresponding to the branch number n of wires obtained by the analysis means, the internal delay time from the input through T _in the signal input to the load capacitance C and the cell was determined by the analysis means T _d and output through T _out is specified as delay data.

According to a fifth timing simulator of the present invention, in the fourth timing simulator, the number of branches n of wirings connected to the subsequent stage of each cell is further calculated from a netlist of the semiconductor integrated circuit described at the transistor level. A circuit simulation means for executing a circuit simulation for calculating the load capacitance C, the input slew T _in , the internal delay time _Td of the cell, and the output slew T _out ; the storage device a plurality of tables to create a plurality of tables, created to identify the load capacitance C and the internal delay time of a cell from the input through T _in T _d and output through T _out to a value different branch number n of wiring lines And a table creating means for storing the information in the table.

According to the sixth timing simulator of the present invention, for each value of the branch number n of the wiring connected to the subsequent stage of the cell,
First specifying means for specifying a load capacitance C from a total wiring length L to one or more cells connected to a subsequent stage, and delay data including at least an internal delay time _Td of the cell from a parameter including at least the load capacitance C A second specifying means for specifying the sum, a analyzing means for obtaining a total L of wiring lengths to one or more cells connected to the subsequent stage of each cell from a netlist of the semiconductor integrated circuit described at the gate level, The first specifying means specifies the load capacitance C of each cell from the total wiring length L to one or more cells connected to the subsequent stage of each cell obtained by the analyzing means, and the second specifying means specifies the load capacitance C of the cell. A timing simulation for specifying delay data including at least a cell internal delay time _Td from a parameter including the load capacitance C specified by at least the first specifying unit is executed. And timing simulation means.

The first timing simulation method according to the present invention is characterized in that a parameter including at least a branch number n and a load capacitance C of a wiring connected to a subsequent stage of a cell and delay data including at least an internal delay time _Td of the cell. A first step of specifying a relationship, a second step of obtaining a branch number n and a load capacitance C of a wiring connected to a subsequent stage of each cell from a netlist of the semiconductor integrated circuit described at a gate level, and According to the relationship specified in the first step, the delay data including at least the internal delay time _Td of the cell is specified from at least the parameter including the number n of wiring branches and the load capacitance C obtained in the second step. It is characterized by comprising three steps.

According to a second timing simulation method of the present invention, in the first timing simulation method, in the first step, the load capacitance C and the cell capacity may be changed according to the number of branches n of the wiring connected to the subsequent stage of the cell. identify internal delay relationship between time T _d of the aforementioned third step, the according to the specific relationship in the first step, the number of branches n and load of wiring connected to the subsequent stage of each cell was examined in the second step The internal delay time _Td is specified from the capacitance C.

According to a third timing simulation method of the present invention, in the first timing simulation method, in the first step, the load capacitance C and the input capacitance are determined for each value of the branch number n of the wiring connected to the subsequent stage of the cell. internal delay time of the through-T _in a cell T _d and output through T
_out is specified, and in the third step, the first
According to the relationship specified in the step, the internal delay time T _{d is} calculated from the number of branches n of the wiring connected to the subsequent stage of each cell, the load capacitance C, and the input slew T _{in of the} signal input to the cell, which are examined in the second step. And an output through _Tout is specified.

According to the fourth timing simulation method of the present invention, the total L of the wiring lengths to one or more cells connected to the subsequent stage and the load capacitance are determined for each value of the branch number n of the wiring connected to the subsequent stage of the cell. A first step of specifying a relationship with C, a second step of specifying a relationship between a parameter including at least the load capacitance C, and delay data including at least an internal delay time _Td of the cell, and a description at a gate level. From a netlist of the semiconductor integrated circuit, a third step of obtaining a total wiring length L to one or more cells connected to the subsequent stage of each cell, and, for each cell, according to the relationship specified in the first step, The load capacitance C of each cell is specified from the total wiring length L obtained in the third step, and
According to the relationship specified in the step, a fourth step of specifying delay data including at least the internal delay time _Td of the cell from at least the parameter including the specified load capacitance C in accordance with the relation specified in the step.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) Outline of the Invention FIG. 1 shows a cell 50 in which three wirings represented by a pie-shaped model are connected in parallel at the subsequent stage, and input to an input node 51 of the cell 50. signal input through T _in, the output node 5
2 shows the signal of the output through _Tout output from 2 and the internal delay time _Td of the cell 50.

As shown in FIG. 1, a state in which three wirings represented by a pie-shaped model are connected in parallel at the subsequent stage of the cell 50 is shown in FIG. There is. The internal delay time _Td is the time required for a signal to pass through a cell. The load capacitance C refers to the sum of the wiring capacitances to one or more cells connected downstream of the cell of interest. And input through T _in or output through T _out is,
When the level of the signal input to the cell or the level of the signal output from the cell changes from H to L or from L to H, the level of the signal is within a predetermined range (for example, L = 0v, H =
In the case of 5v, it means the time required to change by the range of 0.5v to 4.5v).

The timing simulator of the present invention uses at least the branch number n and the load capacitance C of the wiring connected downstream of the cell 50 as parameters for specifying delay data including the internal delay time _Td of the cell 50. At least the internal delay time T _{d of the} cell is accurately and promptly determined according to the value of the number of branches n of the wiring connected to the subsequent stage of the cell 50.
Is characterized by specifying delay data including Less than,
The timing simulator according to the first to fourth embodiments having the above features will be described with reference to the accompanying drawings.

(2) Embodiment 1 The timing simulator 100 according to Embodiment 1
Formulas for specifying the relationship between the load capacitance C and the internal delay time _Td of the cell are created for each value of the number n of branches of the wiring connected to the subsequent stage of the cell, and a formula is specified from the netlist of the semiconductor integrated circuit described at the gate level. The number of branches n and the load capacitance C of the wiring connected to the subsequent stage of each cell are obtained, and the number of branches n and the load capacitance C of the wiring obtained above are calculated for each cell according to the created formula.
A timing simulation for specifying an internal delay time _Td from the timing simulation.

(2-1) Overall Configuration FIG. 2 shows a timing simulator 1 according to the first embodiment.
It is a figure which shows the whole structure of 00. The timing simulator 100 includes a display 101 functioning as a man-machine interface, a keyboard 103 and a mouse 104, and a control unit 102 containing a hard disk 105 (not shown) for storing a netlist and mathematical formulas of a semiconductor integrated circuit. Is done.

FIG. 3 is a diagram showing the internal configuration of the control unit 102 surrounded by a dotted line. As shown in FIG.
Is composed of a hard disk 105, a ROM 107 and a RAM 108 with a central processing unit (hereinafter referred to as a CPU) 106 as a center. The hard disk 105
First mathematical formula creation processing described below (FIG. 4, step S
The netlist of the semiconductor integrated circuit described at the transistor level used in 1), the netlist of the semiconductor integrated circuit described at the gate level used in the first timing simulation (FIG. 5, step S10), and the creation of the first mathematical expression The data of a plurality of formulas created in the processing is stored. The ROM 107 stores a program for a first mathematical expression creation process and a program for a first timing simulation executed using a plurality of mathematical expressions created by the first mathematical expression creation process. The CPU 106 has a ROM 107
Is read into the RAM 108 to execute the first mathematical expression creation processing and the first timing simulation.

(2-2) First Formula Creation Process FIG. 4 is a flowchart of the first formula creation process (step S1) executed by the CPU 106. Display 1
The process waits until the first mathematical expression creation process start button (not shown) displayed on 01 is selected by the keyboard 103 or the mouse 104 (NO in step S2). The start button of the mathematical formula creation process is the keyboard 103 or the mouse 10
4 (YES in step S2), the hard disk 105 stores the netlist of the semiconductor integrated circuit described at the transistor level prepared for formula creation.
To the RAM 108 (step S3). ROM
The execution program of the circuit simulator written in 107 is read out to the RAM 108, and the above-described step S3 is executed.
A circuit simulation for calculating the number of branches n, the load capacitance C, and the internal delay time _Td of the wiring connected to the subsequent stage of each cell is executed from the netlist read in step S4 (step S4).

In the following steps S5 to S9, the internal delay time T _d of the cell is determined by the load capacitance C for each value of the branch number n of the wiring connected to the subsequent stage of the cell, based on the result of the circuit simulation executed in the step S4.
(Hereinafter, also referred to as a calculation formula of the load capacity C), and writes the data of the calculated calculation formula of the load capacity C to the hard disk 105 and stores them.

First, the value of a variable n representing the number of branches is initialized to 1 (step S5). From the result of the circuit simulation, a relational expression between the load capacitance C and the internal delay time _Td of the cell when the number of wiring branches is n, that is, a calculation expression of the load capacitance C is created by using, for example, the least square method. (Step S
6). The data of the calculation formula of the load capacity C created in step S6 is stored in the hard disk 105 (step S7). When the value of the variable n representing the number of branches is not the maximum value N (where N ≧ 1) of the predetermined number of branches (NO in step S8), after adding 1 to the variable n (step S9), Returning to S6, processing for creating a formula for calculating the load capacitance C when the number of wiring branches is n is performed. If the value of the variable n has reached the maximum value N (YES in step S8), the process ends.

The above-described first mathematical expression creation processing (step S1)
May be automatically executed when the timing simulator 100 is started. In this case, once a formula for calculating the load capacitance C is created for each value of the number n of wiring branches, the netlist of the semiconductor integrated circuit described at the transistor level stored in the hard disk 105 for formulating is prepared. Until is updated, a configuration in which the first mathematical expression creation process is not executed may be adopted.

In addition, instead of a netlist of a semiconductor integrated circuit described at a transistor level, a circuit simulator for performing a circuit simulation on an actual circuit is prepared, and connected to the subsequent stage of each cell using the circuit simulator. A configuration may be adopted in which a circuit simulation for calculating the number n of wiring branches, the load capacitance C, and the internal delay time _Td is executed, and the result of the circuit simulation is output to the CPU 106. In this case, the CPU 106 creates a calculation formula of the load capacitance C for each value of the number n of wiring branches from the circuit simulation result output from the circuit simulator, and calculates the load capacitance C generated for each value of the number n of wiring branches. The calculation formula data is written to the hard disk 105 and stored.

(2-3) First Timing Simulation FIG. 5 is a flowchart of a first timing simulation (step S10) executed by the CPU 106. First, the process waits until a first timing simulation start button (not shown) displayed on the display 101 is selected by the keyboard 103 or the mouse 104 (NO in step S11). When the first timing simulation start button is selected by the keyboard 103 or the mouse 104 (YE in step S11)
S), the netlist of the semiconductor integrated circuit described at the gate level is read from the hard disk 105 into the RAM 108, and the branch number n and the load capacitance C of the wiring connected to the subsequent stage of each cell are obtained from the read netlist (step S12). . In step S12, the load capacity C
Is calculated based on the total length L of wirings to one or more cells connected in the subsequent stage. The data of the calculation formula of the load capacity C created in the first mathematical formula creation process (FIG. 4, step S1) is read from the hard disk 105 to the RAM 108 (step S13).

The following steps S14 to S17
Then, for each cell, according to the calculation formula of the load capacitance C corresponding to the branch number n of the wiring checked in step S12,
The internal delay time _Td is specified from the load capacitance C obtained in step S12.

First, the value of a variable S representing the number of a cell having an external signal input terminal is initialized to 1 (step S14). The delay time _Td is specified from the load capacitance C according to the calculation formula of the load capacitance C corresponding to the branch number n of the wiring connected to the subsequent stage of the S-th cell (step S15). If the value of the variable S is not _{Smax indicating} the last cell number of the semiconductor integrated circuit described at the gate level (NO in step S16), after adding 1 to the value of the variable S (step S17), Returning to step S15,
Subsequently, according to the calculation formula of the load capacitance C corresponding to the branch number n of the wiring connected to the subsequent stage of the S-th cell, the load capacitance C
From the delay time _Td . If the value of the variable S has reached _Smax (YES in step S16), the process ends.

For example, as shown in FIG. 6A, a 1 m delay model represented by a pi-type delay model is provided between a cell 201 of interest and a cell 202 connected downstream of the cell 201.
When two wirings m are connected in series, the total length L of the wirings is calculated in step S12 according to the calculation formula of the load capacitance C for the branch number n = 1 of the wiring connected at the subsequent stage.
The internal delay time _Td of the cell is obtained from the load capacity C specified based on 2 mm.

As shown in FIG. 6B, a 1 mm delay model represented by a pie-type delay model is provided between the cell 203 of interest and the cells 204 and 205 connected to the subsequent stage of the cell 203. Are connected in parallel in two stages, the number of branches of the wiring connected at the subsequent stage is calculated based on the total wiring length L = 2 mm in step S12 according to the formula for calculating the load capacitance C for n = 2. The internal delay time _Td of the cell is obtained from the load capacitance C specified by the above.

The first timing simulation process (FIG. 5, step S10) may be configured to be automatically executed subsequent to the above-described first mathematical expression creation process (step S1 in FIG. 4).

As described above, in the timing simulator 100, the relational expression for specifying the internal delay time _Td of the cell from the load capacitance C for each value of the number of branches n of the wiring connected at the subsequent stage for the timing simulation, That is, a formula for calculating the load capacity C is prepared. Then, in the first timing simulation, for each cell, the internal delay time T of the cell is calculated based on the load capacitance C by referring to the calculation formula of the load capacitance C for each value of the branch number n of the wiring connected to the subsequent stage. _d
Is executed. As a result, compared to a conventional timing simulator that executes a timing simulation for specifying the internal delay time _Td of the cell only from the load capacitance C without considering the value of the number of branches n of the wiring connected at the subsequent stage. An accurate timing simulation result can be obtained.

(3) Embodiment 2 A timing simulator 300 according to Embodiment 2
A plurality of tables for specifying the relationship between the load capacitance C and the input slew T _in and the internal delay time T _d and the output slew T _out of the cell are created for each value of the number of branches n of the wiring connected to the subsequent stage of the cell. From the netlist of the semiconductor integrated circuit described by the level, the number of branches n, the load capacitance C, and the input through T _in of the wiring connected to the subsequent stage of each cell are obtained, and for each cell, among the plurality of tables created above, refers to the table corresponding to the branch number n of wires obtained above, to perform a second timing simulation to identify the internal delay time T _d and output slew T _out from the load capacitance C and input through T _in determined above.

The configuration of the timing simulator 300 according to the second embodiment is the same as that of the timing simulator 100 according to the first embodiment shown in FIGS. 2 and 3. In the following description, each component of the timing simulator 300 is referred to as the timing simulator 100.
It is represented using the same reference number as.

The hard disk 105 is used for a netlist of a semiconductor integrated circuit described at a transistor level used in a first table creation process (FIG. 7, step S20) to be described later, and for a second timing simulation (FIG. 9, step S30). A netlist of the semiconductor integrated circuit described at the gate level and data of a plurality of tables created in the first table creation process are stored.
The ROM 107 stores a program for a first table creation process and a second timing simulation program to be executed using a plurality of tables created by the first table creation process. The CPU 106
The program written in M107 is stored in RAM 108
To perform the first table creation processing and the second timing simulation.

(3-1) Table Creation Processing FIG. 7 is a flowchart of the first table creation processing (step S20) executed by the CPU 106. The first table creation processing start button (not shown) displayed on the display 101 is the keyboard 103 or the mouse 104.
Waits for selection by the user (N in step S21).
O). When the first table creation processing start button is selected by the keyboard 103 or the mouse 104 (YES in step S21), the netlist of the semiconductor integrated circuit described at the transistor level prepared for table creation is transferred from the hard disk 105 to the RAM 108. (Step S22). The execution program of the circuit simulator written in the ROM 107 is stored in the RAM 108
From the netlist read in step S22, the number of branches n of the wiring connected to the subsequent stage of each cell, the load capacitance C, the input through T _in , the output through T _out ,
Then, a circuit simulation for calculating the internal delay time _Td is executed (step S23).

The following steps S24 to S28
Then, based on the result of the circuit simulation executed in step S23, as shown in the following FIG. 8, the internal delay of the cell from the load capacitance C and the input through T _in is determined for each value of the branch number n of the wiring connected to the subsequent stage of the cell. A plurality of tables for specifying the time _Td and the output through _Tout are created, and data of each table created for each value of the number n of wiring branches is written to the hard disk 105 and stored.

First, the value of a variable n representing the number of branches of the wiring connected to the subsequent stage is initialized to 1 (step S24). From the results of the above circuit simulation, the number of wiring branches is n
In the case of creating a table that identifies the internal delay time of the cell from the load capacitance C and input slew T _in T _d and output through T _out (step S25). Step S above
The data of the table created in step 25 is stored in the hard disk 105 (step S26). The value of the variable n representing the number of branches is the maximum value N (where N
If ≧ 1) (NO in step S27), 1 is added to the variable n (step S28), and then step S28 is performed.
Returning to 25, subsequently, in the case of a branch number n of wires, and create a table that identifies the load capacitance C and the internal delay time of a cell from the input through T _in T _d and output through T _out. If the value of the variable n has reached the maximum value N (YES in step S27), the process ends.

The first table creation process (step S20) may be automatically executed when the timing simulator 300 is started. In this case,
Once a table is created for each value of the wiring branch number n,
A configuration in which the first table creation processing is not executed until the netlist of the semiconductor integrated circuit described at the transistor level stored in the hard disk 105 for creating the table is updated may be adopted.

Also, instead of a netlist of a semiconductor integrated circuit described at the transistor level, a circuit simulator for performing a circuit simulation for an actual circuit is prepared, and connected to the subsequent stage of each cell using the circuit simulator. Number of wiring branches n, load capacitance C, input through T _in ,
A configuration may be adopted in which a circuit simulation for calculating the output through T _out and the internal delay time T _d is executed, and the result of the circuit simulation is output to the CPU 106. In this case, based on the circuit simulation result output from the circuit simulator, the CPU 106 determines the load capacitance C and the input through T _in for each value of the branch number n of the wiring connected to the subsequent stage of the cell, as shown in FIG. Then, a table for specifying the internal delay time _Td and output through _Tout of the cell is created, and the data of each table created for each value of the number n of wiring branches is written to the hard disk 105 and stored.

(3-2) Second Timing Simulation FIG. 9 is a flowchart of a second timing simulation (step S30) executed by the CPU 106. First, the process waits until a second timing simulation start button (not shown) displayed on the display 101 is selected by the keyboard 103 or the mouse 104 (NO in step S31). When the second timing simulation start button is selected by the keyboard 103 or the mouse 104 (YE in step S31)
S), the netlist of the semiconductor integrated circuit described at the gate level is read from the hard disk 105 into the RAM 108, and the branch number n and the load capacitance C of the wiring connected to the subsequent stage of each cell are checked from the read netlist (step S32). . In step S32, the load capacitance C is determined based on the total length L of one or more cells connected to the subsequent stage. In the first table creation process (FIG. 7, step S20), the data of each table created for each value of the branch number n of the wiring connected at the subsequent stage is read from the hard disk 105 to the RAM 108 (step S33).

The following steps S34 to S37
Then, for each cell, of the plurality of tables read in step S33, for each cell,
Refers to the table corresponding to the number of branches n of wires was examined in 32, identifies the internal delay time T _d and output slew T _out from the load capacitance C and input through T _in.

First, the value of a variable S representing the number of the cell from the cell having the external signal input terminal is initialized to 1 (step S34). Referring to the table corresponding to the number n of branches of the wiring connected to the subsequent stage of the S-th cell, the load capacitance C and the input through T _in (S-1 of the signal output from the (S-1) -th cell are checked in step S32. identifying the time delay from the output corresponding to the through T _out) T _d and output through T _out (corresponding to the input through T _in the S + 1-th cell) (step S35). Step S3 above
In 5, the case of variable S = 1, i.e., the input slew T _in the first cell uses the input slew T _in the external signal input to the input terminal.

If the value of the variable S is not _Smax representing the last number of the cell of the semiconductor integrated circuit described at the gate level (NO in step S36), 1 is added to the value of the variable S (step S36). S37) Returning to step S35, referring to the table corresponding to the branch number n of the wiring connected to the subsequent stage of the S-th cell,
The load capacitance C and the delay time from the input through T _in T _d and output through T _out was examined in 32 performs a process of identifying. When the value of the variable S reaches _Smax (step S3
(YES at 6), ends the process.

For example, as shown in FIG. 6A, a 1-m delay model represented by a pie-type delay model is provided between a cell 201 of interest and a cell 202 connected to the subsequent stage of the cell 201.
When two wirings m are connected in series, the table for the branch number n = 1 of the wiring connected at the subsequent stage is referred to,
Determining the load capacity C and the internal delay time of a cell from the input through T _in T _d and output through T _out is specified based on the total L = 2 mm of wire length in step S32.

Further, as shown in FIG. 6B, a 1 mm delay model represented by a pie-type delay model is provided between the cell 203 of interest and the cells 204 and 205 connected downstream of the cell 203. Are connected in parallel in two stages, the table for the number of branches n = 2 of the wires connected in the subsequent stage is referred to, and in step S32, the total length L of the wires is determined.
= Internal delay time from the load capacitance C and input slew T _in the particular cell on the basis of 2 mm T _d and output through T _out
Ask for.

The second timing simulation process (FIG. 9, step S30) may be configured to be automatically executed following the first table creation process (FIG. 7, step S20).

As described above, in the timing simulator 300, for the second timing simulation, the internal delay time of the cell from the load capacitance C and the input through T _in is determined for each value of the number of branches n of the wiring connected to the subsequent stage. A table for specifying _Td and output through _Tout is prepared. In the second timing simulation, the load capacitance C and the input slew T are determined for each cell by referring to the table and for each value of the number of branches n of the wiring connected to the subsequent stage.
identifying the internal delay time of the cell T _d and output through T _out from _in. By adopting this configuration, the first embodiment
It is possible to specify the accurate internal delay time _Td of the cell according to the value of the number of branches n of the wiring connected at the subsequent stage, similarly to the timing simulator 100 according to the first embodiment.

(4) Embodiment 3 A timing simulator 350 according to Embodiment 3
A plurality of relational expressions for calculating the load capacitance C from the total length L of the wirings connected to the subsequent stage of the cell for each value of the number n of branches of the interconnection connected to the subsequent stage of the cell (hereinafter referred to as a calculation expression of the load capacitance C)
And one relational expression for specifying the internal delay time _Td from the load capacitance C (hereinafter referred to as a calculation expression of the internal delay time _Td ). Then, from the netlist of the semiconductor integrated circuit described at the gate level, for each cell,
The total number L of the wiring branch number n and the wiring length is obtained, and according to the calculation formula of the load capacitance C corresponding to the obtained wiring branch number n,
The load capacitance C is specified from the sum L of the wiring lengths of the cells obtained above, and the internal delay time T
_{According to} the calculation formula of _d , the internal delay time _Td of the cell is specified from the specified load capacity C.

The formula for calculating the load capacitance C is as follows: from the netlist of the semiconductor integrated circuit described at the transistor level, the number of branches n of the wiring connected to the succeeding stage of each cell, and one or more cells connected to the succeeding stage. A circuit simulation for calculating the total wiring length L and the load capacitance C is executed, and the subsequent wiring length obtained for each value of the branch number n of the wiring connected to the subsequent stage of the cell based on the result of the circuit simulation From the relationship between the total L and the load capacity C, for example, using the least squares method.

The configuration of the timing simulator 350 according to the third embodiment is the same as that of the timing simulator 100 according to the first embodiment shown in FIGS. 2 and 3. In the following description, each component of the timing simulator 350 is referred to as the timing simulator 100.
It is represented using the same reference number as.

The hard disk 105 is used in a third timing simulation (FIG. 11, step S51) of a semiconductor integrated circuit netlist described at a transistor level used in a second mathematical expression creation process (FIG. 10, step S40) described later. A netlist of the semiconductor integrated circuit described at the gate level and data of a mathematical expression created by the second mathematical expression creation process are stored. ROM 107
Stores a program for the second mathematical expression creation process and a third timing simulation program to be executed using the mathematical expression created by the second mathematical expression creation process.
The CPU 106 reads the program written in the ROM 107 into the RAM 108 and executes the second mathematical expression creation processing and the third timing simulation.

(4-1) Second Formula Creation Process FIG. 10 is a flowchart of the second formula creation process (step S40) executed by the CPU 106. The process waits until a second mathematical expression creation process start button (not shown) displayed on the display 101 is selected by the keyboard 103 or the mouse 104 (NO in step S41).
When the second mathematical expression creation processing start button is selected by the keyboard 103 or the mouse 104 (YES in step S41), a netlist of the semiconductor integrated circuit described at the transistor level prepared for the expression creation is transferred from the hard disk 105 to the RAM 108. (Step S42). The execution program of the circuit simulator written in the ROM 107 is read out to the RAM 108,
From the netlist read in step S42, the number of branches n of the wiring connected to the subsequent stage of each cell, the total length L of the wiring to one or more cells connected to the subsequent stage, the load capacitance C,
Then, a circuit simulation for calculating the internal delay time _Td is executed (step S43).

The following steps S44 to S50
Then, based on the result of the circuit simulation executed in step S43, a plurality of calculation formulas for the load capacitance C and a calculation formula for the internal delay time _Td are created for each value of the number of branches n of the wiring connected to the subsequent stage of the cell. Then, the data of each created mathematical expression is written to the hard disk 105 and stored.

First, the value of a variable n representing the number of branch lines is set to 1
(Step S44). Step S43 above
According to the result of the circuit simulation in the above, when the number of wiring branches is n, the relational expression for specifying the load capacitance C from the total L of the subsequent wiring lengths, that is, the calculation expression of the load capacitance C is used, for example, using the least square method. (Step S
45). The data of the calculation formula of the load capacitance C created for each value of the wiring branch number n in step S45 is stored in the hard disk 105 (step S46). If the value of the variable n is not the maximum value N (where N ≧ 1) of the predetermined number of branches (NO in step S47), 1 is added to the variable n (step S48), and the process returns to step S45. Subsequently, a process of creating a calculation formula of the load capacitance C in the case of the number n of wiring branches is performed. If the value of the variable n has reached the maximum value N (YES in step S47),
A relational expression between the load capacitance C and the delay time _Td , that is, an expression for calculating the internal delay time _Td is created from the result of the circuit simulation (step S49). Created internal delay time T _d
Is stored in the hard disk 105 (step S50).

The above-described second mathematical expression creation processing (step S40)
May be automatically executed when the timing simulator 350 is started. In this case, once, a calculation formula of a plurality of load capacitances C for each value of the wiring branch number n, and
After the formula for calculating the internal delay time _Td is created, the second formula is used until the netlist of the semiconductor integrated circuit described at the transistor level stored in the hard disk 105 for formula creation is updated. A configuration that does not execute the creation processing may be adopted.

In addition, instead of a netlist of a semiconductor integrated circuit described at a transistor level, a circuit simulator for performing a circuit simulation for an actual circuit is prepared, and the circuit simulator is used to connect to a subsequent stage of each cell. Circuit simulation to calculate the number n of branches of the wiring to be performed, the total length L of wirings to one or more cells connected to the subsequent stage, the load capacitance C, and the internal delay time _Td ,
A configuration in which the result of the circuit simulation is output to the CPU 106 may be employed. In this case, the CPU 106
From the circuit simulation results output from the circuit simulator, a plurality of formulas for calculating the load capacitance C are created for each value of the number of branches n of the wiring connected to the subsequent stage of the cell, and a formula for calculating the internal delay time _Td is obtained. Is created, and the data of each created mathematical expression is written to the hard disk 105 and stored.

(4-2) Third Timing Simulation FIG. 11 is a flowchart of a third timing simulation (step S51) executed by the CPU 106. First, the process waits until a third timing simulation start button (not shown) displayed on the display 101 is selected by the keyboard 103 or the mouse 104 (NO in step S52). When the third timing simulation start button is selected by the keyboard 103 or the mouse 104 (YE in step S52)
S) The netlist of the semiconductor integrated circuit described at the gate level is read from the hard disk 105 into the RAM 108, and the number of branches n of the wiring connected to the subsequent stage of each cell from the read netlist and one or more connected to the subsequent stage The total L of the wiring lengths up to the cell is determined (step S5).
3). The second mathematical formula creation process (FIG. 10, step S4)
In step S54, the data of the calculation formulas of the plurality of load capacities C and the calculation formulas of the internal delay time _Td created for each value of the wiring branch number n in step 0) are read from the hard disk 105 to the RAM.

The following steps S55 to S59
Then, for each cell, the load capacitance C corresponding to the value of the number of branches n
After calculating the load capacitance C from the total wiring length L to one or more cells connected to the succeeding stage according to the calculation formula, the internal delay time T is calculated from the calculated load capacitance C according to the calculation formula of the internal delay time _{Td. Find d} .

First, the value of a variable S indicating the number of the cell from the cell having the external signal input terminal is initialized to 1 (step S55). According to the calculation formula of the load capacitance C corresponding to the number of branches n of the wiring connected to the subsequent stage of the S-th cell, the load capacitance C is specified from the total length L of the wiring connected to the subsequent stage (step S56). According calculation formula of the internal delay time Td, identifies the internal delay time T _d from the load capacitance C identified in Step S56 (Step S5
7). If the value of the variable S is not _{Smax indicating} the last number of the cell of the semiconductor integrated circuit described at the gate level (NO in step S58), after adding 1 to the value of the variable S (step S59), Returning to step S56, the branch number n of the wiring connected to the subsequent stage of the S-th cell is continued.
According to the calculation formula of the load capacitance C corresponding to the following, the load capacitance C is specified from the total length L of the wiring connected to the subsequent stage. If the value of the variable S has reached _Smax (YES in step S58),
The process ends.

As described above, the timing simulator 350 according to the third embodiment uses the load capacitance based on the total length L of the wiring connected to the subsequent stage of the cell for each value of the number of branches n of the wiring connected to the latter stage of the cell. Multiple load capacities C to find C
Together to create a calculation formula to create a calculation equation of one internal delay time to identify the internal delay time T _d from the load capacitance C T _d. Then, from the netlist of the semiconductor integrated circuit described at the gate level, the number of wiring branches n and the total wiring length L of each cell are obtained, and the load capacitance C corresponding to the value of the wiring branch number n is determined. According to the calculation formula, the load capacitance C is specified from the sum L of the wiring lengths of the cells determined above. Further, for each cell, the load capacitance C is determined from the specified load capacitance C according to the calculation formula of the internal delay time _Td . The internal delay time T _{d of the} cell
To identify. By employing this configuration, it is possible to specify the accurate internal delay time _Td of the cell according to the value of the number of branches n of the wiring connected to the subsequent stage, similarly to the timing simulator 100 according to the first embodiment. Becomes possible.

(5) Embodiment 4 A timing simulator 360 according to Embodiment 4
A plurality of relational expressions for calculating the load capacitance C from the total length L of the wiring connected to the subsequent stage of the cell for each value of the number n of branches of the wiring connected to the subsequent stage of the cell (hereinafter, also referred to as a calculation expression of the load capacitance C)
While creating, to create a single table from the load capacitance C and input slew T _in identifying the internal delay time T _d and output slew T _out. Then, from the netlist of the semiconductor integrated circuit described at the gate level, the total number L of the branch number n of the wiring connected to the subsequent stage of each cell and the wiring length to one or more cells connected to the subsequent stage is obtained. According to the calculation formula of the load capacitance C corresponding to the obtained number n of branches of the wiring among the calculated calculation formulas of the load capacitance C, the load capacitance C is specified from the total L of the obtained wiring lengths of the respective cells. , for each cell, in accordance with the above table, the load capacitance C and input through T _in the above calculation, to identify the internal delay time of the cell T _d and output through T _out.

The configuration of the timing simulator 360 according to the fourth embodiment is the same as that of the timing simulator 100 according to the first embodiment shown in FIGS. 2 and 3. In the following description, each component constituting the timing simulator 360 is referred to as the timing simulator 100.
It is represented using the same reference number as.

The hard disk 105 has a netlist of a semiconductor integrated circuit described at a transistor level used in a second table creation process (FIG. 12, step S60) described later, and a fourth timing simulation (FIG. 1).
3. The netlist of the semiconductor integrated circuit described at the gate level used in step S71), the calculation formulas of the plurality of load capacitors C created in the second table creation process, and the data of one table are stored. . ROM 107
Stores a program for a second table creation process, a calculation formula of a plurality of load capacities C created by the table creation process, and a fourth timing simulation program executed using one table. C
The PU 106 reads out the program written in the ROM 107 to the RAM 108 and executes the second table creation processing and the fourth timing simulation.

(5-1) Second Table Creation Processing FIG. 12 is a flowchart of the second table creation processing (step S60) executed by the CPU 106. The second table creation process start button (not shown) displayed on the display 101 is
4 to be selected (N in step S61).
O). When the second table creation processing start button is selected by the keyboard 103 or the mouse 104 (YES in step S61), a netlist of the semiconductor integrated circuit described at the transistor level prepared for table creation is transferred from the hard disk 105 to the RAM 108. (Step S62). The execution program of the circuit simulator written in the ROM 107 is stored in the RAM 108
From the netlist read in step S62, the number of branches n of the wiring connected to the subsequent stage of each cell, the total length L of the wiring to one or more cells connected to the subsequent stage, the load capacitance C, the input Through T _in , output through T _out ,
Then, a circuit simulation for calculating the internal delay time _Td is executed (step S).

The following steps S64 to S70
Then, based on the result of the circuit simulation executed in step S62, a plurality of calculation formulas for the load capacitance C are created for each value of the number of branches n of the wiring connected to the subsequent stage of the cell, and the load capacitance C and the input through T _in are calculated. One table for specifying the internal delay time _Td and the output slew _Tout of the cell is created, and the formula for calculating the plurality of created load capacities C;
Then, the data of one table is written and stored in the hard disk 105, respectively.

First, the value of a variable n representing the number of branch lines is set to 1
(Step S64). Step S62 above
According to the result of the circuit simulation executed in the above, when the number of branches of the wiring connected to the subsequent stage of the cell is n,
A calculation formula of the load capacitance C for specifying the load capacitance C is created from the total L of the subsequent wiring lengths (step S65). The data of the created calculation formula of the load capacity C is stored in the hard disk 105 (step S66). If the value of the variable n is not the maximum value N of the predetermined number of branches (where N ≧ 1) (NO in step S67), 1 is added to the variable n (step S68), and the process returns to step S65. Subsequently, when the number of branches of the wiring connected to the subsequent stage of the cell is n, a calculation formula of the load capacitance C for specifying the load capacitance C is created from the total L of the wiring lengths at the subsequent stage. If the value of the variable n becomes the maximum value N (YES at step S67), specific to the results of the circuit simulation, the internal delay time of the cell from the load capacitance C and input slew T _in T _d and output through T _out To create a table (step S6)
9). The table created in step S69 is stored in the hard disk 105 (step S70).

The second table creation processing (step S60) may be automatically executed when the timing simulator 360 is started. In this case,
Once the calculation formula of the load capacitance C for each value of the wiring branch number n and the internal delay time T from the load capacitance C and the input through T _in are calculated.
After the table for specifying the _d and the output through _Tout is created, the process is continued until the netlist of the semiconductor integrated circuit described at the transistor level stored in the hard disk 105 for the process is updated. A configuration that does not execute the two-table creation process may be adopted.

In addition, instead of a netlist of a semiconductor integrated circuit described at a transistor level, a circuit simulator for performing a circuit simulation for an actual circuit is prepared, and connected to the subsequent stage of each cell using the circuit simulator. The number n of wiring branches, the total length L of wiring connected to the subsequent stage, load capacitance C, input through T _in , output through T _out ,
And a circuit simulation for calculating the internal delay time _Td is executed, and the result of the circuit simulation is executed by the CPU.
A configuration for outputting to 106 may be adopted. In this case, C
The PU 106 creates a calculation formula of the load capacitance C for each value of the number of wiring branches n based on the circuit simulation result output from the circuit simulator, and generates the internal delay time T _d of the cell based on the load capacitance C and the input through T _in. Then, one table for specifying the output through _Tout is created, and the created calculation formula of each load capacity C and the data of the table are written to the hard disk 105 and stored.

(5-2) Fourth Timing Simulation FIG. 13 is a flowchart of a fourth timing simulation (step S71) executed by the CPU 106. First, the process waits until a fourth timing simulation start button (not shown) displayed on the display 101 is selected by the keyboard 103 or the mouse 104 (NO in step S72). When the fourth timing simulation start button is selected by the keyboard 103 or the mouse 104 (YE in step S72)
S), the netlist of the semiconductor integrated circuit described at the gate level is read from the hard disk 105 into the RAM 108, and the total number L of the wiring branches n and the wiring lengths connected to the subsequent stage of each cell is obtained from the read netlist (step S). S73). The second table creation process (FIG. 12,
The calculation formula of each load capacity C created in step S60) and the data of one table are read from the hard disk 105 to the RAM 108 (step S74).

The following steps S75 to S79
In the calculation formula of the plurality of load capacitances C read in step S74, for each cell, according to the calculation command corresponding to the value of the branch number n of the wiring, the sum of the wiring lengths L obtained in step S73 is calculated. While specifying the load capacity C,
Referring to the table read in step S74,
Identifying the internal delay time T _d and output slew T _out from the load capacitance C and input through T _in the above identified.

First, the value of a variable S indicating the number of the cell from the cell having the external signal input terminal is initialized to 1 (step S75). According to the calculation formula of the load capacitance C corresponding to the branch number n of the wiring at the subsequent stage of the S-th cell, the load capacitance C is specified from the total L of the wiring lengths (step S7).
6). Referring to the table, the delay time from the load capacitance C of the S-th cell specified in step S76 and the input through T _in (corresponding to the output through T _{out of the} signal output from the (S−1) -th cell) T _d and output slew T
_out (corresponding to the input through T _in the S + 1 th cell)
Is specified (step S77). In the step S77, the case of variable S = 1, i.e., the input slew T _in the first cell uses the input slew T _in the external signal input to the input terminal.

If the value of the variable S is not _{Smax indicating} the last number of the cell of the semiconductor integrated circuit described at the gate level (NO in step S78), 1 is added to the value of the variable S (step S78). S79) Returning to step S76, the process of specifying the load capacitance C from the total wiring length L according to the calculation formula of the load capacitance C corresponding to the branch number n of the wiring connected to the subsequent stage of the S-th cell is continued. Do. Variable S
Becomes equal to _Smax (YE in step S78).
S), the process ends.

The fourth timing simulation may be configured to be automatically executed following the second table creation processing (FIG. 12, step S60).

As described above, in the timing simulator 360, the load capacity C is obtained from the total length L of the wiring connected to the subsequent stage of the cell for each value of the number n of branches of the wiring connected to the latter stage of the cell. together to create a C calculation formula, the internal delay time from the load capacitance C and input to T _in T
Create one table that identifies _d and the output slew T _out . Then, from the netlist of the semiconductor integrated circuit described at the gate level, the total number L of the branch number n of the wiring connected to the subsequent stage of each cell and the wiring length to one or more cells connected to the subsequent stage is obtained. For each cell, the number n of branches of the wiring
The load capacitance C is specified from the total L of the determined wiring lengths in accordance with the calculation expression corresponding to the obtained number n of branches of the wiring among the plurality of calculation formulas of the load capacitance C created for each value of according table created from the load capacitance C and input through T _in the above calculation, to identify the internal delay time of the cell T _d and output through T _out. By employing this configuration, it is possible to specify the accurate internal delay time _Td of the cell according to the value of the number of branches n of the wiring connected to the subsequent stage, similarly to the timing simulator 100 according to the first embodiment. Becomes possible.

[0088]

According to the first timing simulator of the present invention, at least the number of branches n of the wiring connected to the subsequent stage of the cell
And delay parameters including at least the internal delay time _Td of the cell from the parameters including the load capacitance C. As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

The second timing simulator of the present invention specifies the internal delay time _Td of the cell from the number of branches n and the load capacitance C of the wiring connected to the subsequent stage of the cell. As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

The third timing simulator of the present invention uses a formula for specifying the internal delay time T _d from the load capacitance C for each value of the number of branches n of the wiring connected to the subsequent stage, which is stored in the storage device. Number n of branches connected to the subsequent stage
The internal delay time _Td of the cell is specified from the load capacitance C and the load capacitance C. As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

[0091] The fourth timing simulator of the present invention, by the value of the branch number n of wiring connected to the subsequent stage of the cell by a particular unit, the internal delay time T _d and the output of the cell from the load capacitance C and input through T _in The through _Tout is specified. As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

A fifth timing simulator according to the present invention uses a table stored in a storage device to specify, for each value of the number of branches n of the wiring connected to the subsequent stage of the cell by the specifying means.
Identifying the load capacitance C and the internal delay time of a cell from the input through T _in T _d and output through T _out. As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

According to the sixth timing simulator of the present invention, the load capacitance C is obtained from the total wiring length L for each value of the wiring branch number n, and at least the internal delay time T Identify the delay data including _d . As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

According to the first timing simulation method of the present invention, the delay data including at least the internal delay time _Td of the cell is specified from the parameters including the number of branches n and the load capacitance C of the wiring connected at the subsequent stage of the cell. I do. Thus, it is possible to accurately specify the output slew _Tout and the internal delay time _Td of the cell according to the wiring configuration of the cell.

In the second timing simulation method of the present invention, the internal delay time _Td of the cell is specified from the load capacitance C for each value of the number of branches n of the wiring connected to the subsequent stage of the cell. As a result, it is possible to accurately specify the internal delay time _Td of the cell according to the wiring configuration of the cell.

According to the third timing simulation method of the present invention, the internal delay time _Td and the output slew T of the cell are determined based on the load capacitance C and the input slew Tin _{in accordance with the} number of branches n of the wiring connected to the subsequent stage of the cell. _{Specify out} . As a result, an accurate cell output slew T according to the cell wiring form can be obtained.
_out and the internal delay time _Td can be specified.

In the fourth timing simulation method of the present invention, the total number of wiring lengths L to one or more cells connected to the subsequent stage of each cell is calculated for each value of the branch number n of the wiring connected to the subsequent stage of the cell. The load capacity C of each cell is specified, and the delay data including at least the internal delay time _Td of the cell is specified for each cell from the parameter including at least the specified load capacity C. Thus, it is possible to accurately specify the output slew _Tout and the internal delay time _Td of the cell according to the wiring configuration of the cell.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cell in a state in which three load capacitances C represented by a pie model are connected in parallel at a subsequent stage.

FIG. 2 is a diagram illustrating a configuration of a system according to an embodiment;

FIG. 3 is a diagram illustrating a configuration of a control unit.

FIG. 4 is a flowchart of a first mathematical formula creation process.

FIG. 5 is a flowchart of a first timing simulation.

FIG. 6 is a diagram showing an example of a cell to be processed.

FIG. 7 is a flowchart of a first table creation process.

FIG. 8 is a diagram showing a plurality of tables created according to the number of fan-outs.

FIG. 9 is a flowchart of a second timing simulation.

FIG. 10 is a flowchart of a second mathematical expression creation process.

FIG. 11 is a flowchart of a third timing simulation.

FIG. 12 is a flowchart of a second table creation process.

FIG. 13 is a flowchart of a fourth timing simulation.

FIG. 14 is a diagram showing signals input to and output from cells, and load capacitances connected to the cells.

FIG. 15 is a diagram showing a form of a wiring at a subsequent stage of a cell.

FIG. 16 is a diagram showing a form of a wiring at a subsequent stage of a cell.

[Description of Signs] 50, 201 to 205, 500 cells, 51, 501
Input node, 52, 502 Output node, 100, 30
0,350,360 Timing simulator, 101
Display, 102 control unit, 103 keyboard, 104 mouse, 105 hard disk, 106
CPU, 107 ROM, 108 RAM,

Claims (10)

[Claims] 1. A means for specifying delay data including at least an internal delay time _Td of a cell from at least a parameter including the number of branches n and a load capacitance C of a wiring connected to a subsequent stage of a cell, and a description at a gate level. Analyzing means for obtaining the number of branches n and load capacitance C of wiring connected to the subsequent stage of each cell from the obtained netlist of the semiconductor integrated circuit; and for each cell, the wiring determined by at least the analyzing means by the specifying means. And a timing simulation means for executing timing simulation for specifying delay data including at least the internal delay time _Td of the cell from parameters including the number of branches n and the load capacitance C. 2. The timing simulator according to claim 1, wherein, as the specifying means, the internal delay time T _{d of the} cell from the load capacitance C for each value of the number of branches n of the wiring connected to the subsequent stage of the cell.
Comprising a storage device for storing a plurality of mathematical formulas for specifying the following, the timing simulation means, for each cell,
The internal delay time _Td is specified as delay data from the load capacitance C in accordance with a mathematical expression corresponding to the number of wiring branches n obtained by the analysis means among a plurality of mathematical expressions stored in the storage device. Timing simulator. 3. The timing simulator according to claim 2, further comprising: a branch number n of a wiring connected to a subsequent stage of each cell; a load capacitance C; A circuit simulation means for executing a circuit simulation for calculating the internal delay time _Td; and a circuit simulation result obtained by the circuit simulation means. A timing simulator, comprising: a plurality of formulas for specifying the internal delay time _Td; and a formula preparing means for storing the prepared formulas in the storage device. 4. The timing simulator according to claim 1, wherein, as the specifying means, the internal delay time T of the cell from the load capacitance C and the input slew Tin _{in accordance with the} number of branches n of the wiring connected to the subsequent stage of the cell. _d and a storage device for storing a plurality of tables for specifying the output through T _out , wherein the timing simulation means comprises:
With reference to a table corresponding to the number of wiring branches n obtained by the analysis means among the plurality of tables stored in the storage device, the load capacitance C obtained by the analysis means and the input of a signal input to the cell are inputted. the timing simulator and identifies the internal delay time T _d and output slew T _out as delayed data from the through T _in. 5. The timing simulator according to claim 4, further comprising, from a netlist of the semiconductor integrated circuit described at the transistor level, the number of branches n of the wiring connected to the subsequent stage of each cell, the load capacitance C, and the input through. Circuit simulation means for executing a circuit simulation for calculating T _in , the internal delay time T _d of the cell, and the output slew T _out ; and, based on the result of the circuit simulation by the circuit simulation means, create multiple tables identifying the n value by the load capacitance C and input slew T _in internal delay time of the cells from the T _d and output through T _out, the table creation means for storing a plurality of tables created in the storage device A timing simulator comprising: 6. The number n of branches of a wiring connected to a subsequent stage of a cell
, A first specifying means for specifying the load capacitance C from the total wiring length L to one or more cells connected to the subsequent stage, and at least an internal delay time T _{d of the} cell from at least a parameter including the load capacitance C. Second specifying means for specifying delay data including: and analyzing means for obtaining, from the netlist of the semiconductor integrated circuit described at the gate level, a total L of wiring lengths to one or more cells connected to the subsequent stage of each cell The first specifying means specifies the load capacitance C of each cell from the total L of the wiring lengths to one or more cells connected to the subsequent stage of each cell obtained by the analyzing means,
And timing simulation means for executing timing simulation for specifying delay data including at least the internal delay time _Td of the cell from the parameter including the load capacitance C specified by the at least first specifying means. Characteristic timing simulator. 7. A first step of specifying a relationship between at least a parameter including a branch number n and a load capacitance C of a wiring connected to a subsequent stage of a cell and delay data including at least an internal delay time _Td of the cell. A second step of obtaining a branch number n and a load capacitance C of a wiring connected to a subsequent stage of each cell from a netlist of the semiconductor integrated circuit described at the gate level; and, for each cell, specified in the first step. In accordance with the relationship, the method comprises a third step of specifying delay data including at least the internal delay time _Td of the cell from at least the parameter including the number of wiring branches n and the load capacitance C obtained in the second step. Timing simulation method. 8. The timing simulation method according to claim 7, wherein, in the first step, the load capacitance C and the internal delay time _Td of the cell are determined for each value of the number of branches n of the wiring connected to the subsequent stage of the cell. In the third step, in accordance with the relation specified in the first step, the internal delay time T is determined based on the number n of branches of the wiring connected to the subsequent stage of each cell and the load capacitance C, which are examined in the second step. A timing simulation method characterized by specifying _d . 9. The timing simulation method according to claim 7, wherein, in the first step, the load capacitance C and the input through T _{in are} different for each value of the branch number n of the wiring connected to the subsequent stage of the cell.
And the relationship between the internal delay time _{Td of the} cell and the output slew _Tout is specified. In the third step, according to the relation specified in the first step, each cell is connected to the subsequent stage of the cell examined in the second step. branch number n of wires, the load capacitance C and timing simulation method characterized by identifying the internal delay time T _d and output slew T _out from the input through T _in the signal input to the cell. 10. A first method for specifying a relationship between a total wiring length L to one or more cells connected to a subsequent stage and a load capacitance C for each value of the number n of branches of a wiring connected to a subsequent stage of a cell. Step, a second step of specifying a relationship between at least a parameter including the load capacitance C, and delay data including at least the internal delay time _Td of the cell; and a netlist of the semiconductor integrated circuit described at the gate level. A third step of obtaining a total wiring length L of one or more cells connected to the subsequent stage of the cell; and a wiring length obtained in the third step according to the relationship specified in the first step for each cell. And the load capacity C of each cell is specified from the total L of the cells, and according to the relationship specified in the second step, at least from the parameter including the specified load capacity C, at least the cell Timing simulation method characterized by a fourth step of identifying the delay data including internal delay time T _d.