JP2000163119A - Network information processor for assembly and control monitor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute both the transmission and reception processing of a program or data and the interpretation processing of a program and the collection processing of state amounts without increasing the processing load of a processor. SOLUTION: A communication interface(I/F) part 10 of a network information processor 8 integrated into a control monitoring device 3 operates the transmission and reception processing of a program and data through a general communication network 5 with the outside part, and the interpretation and execution processing of the received program through a bus B1 is operated by a first arithmetic processing part 11, and the collection processing of state data related with an object 2 to be controlled and monitored through a bus B2 is operated by a second arithmetic processing part 12. Moreover, the network information processor 8 is provided with a shared operation processing part 17 to which access can commonly be performed by those first and second arithmetic processing parts for operating prescribed operation processing, and an arbitration processing part 18 for adjusting two independent accesses to those three processing parts according to the timing of access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a steel plant,
Used for multiple control and monitoring devices for controlling and monitoring various plants to be monitored and controlled, such as power systems and water and sewage plants, respectively, and can be processed by communicating information with each other via a network. The present invention relates to a network information processing device and a control monitoring system.

[0002]

2. Description of the Related Art Conventionally, at each control monitoring station (also referred to as a plant or control station) constituting a control monitoring system for controlling and monitoring various plants such as a steel plant, a power system, and a water supply and sewage system, the above control is performed. At least one control monitoring device that actually performs the monitoring process is provided. The control / monitoring devices installed at each control / monitoring station have a network connection processing unit incorporated therein in addition to the control / monitoring processor. The units are interconnected so that they can perform data communication with each other via a network dedicated to control and monitoring.

That is, a plurality of control and monitoring devices installed in a control and monitoring station communicate data related to control and monitoring with each other via respective network connection processing units and networks, for example, transmission and reception of state quantities related to control and monitoring targets. , Transmission and reception of set values (setting data) related to processing, transmission of control commands, and the like.

A network dedicated to control and monitoring is a network for communicating only data related to control and monitoring, and its transmission distance is usually several hundred meters to several hundred kilometers. For this reason, the control and monitoring dedicated network is used for control and monitoring data communication between a plurality of control devices installed in each control station, as described above, and for example, a plurality of remotely arranged at a distance exceeding ten and several kilometers. It was not used for control monitoring data communication between control monitoring devices installed at control stations.

[0005] In a system such as a power system control and monitoring system and a water and sewage control monitoring system, a plurality of control stations remotely located in a wide area are interconnected to control a power system, a water and sewage system and the like in a wide area. The plurality of control and monitoring devices are individually connected to other control and monitoring devices via dedicated communication lines (communication cables), and exchange and control of synchronization / control data with each other via the dedicated communication lines. It was transmitting commands.

On the other hand, in the recent OA environment, computer terminals such as personal computers (PCs) and workstations at a long distance are connected to each other via a general-purpose network represented by the Internet, an intranet, etc., to exchange data and electronic data. Frequent mail exchanges and the like are performed. Further, conventional programs all depend on the type of computer terminal such as a personal computer or a workstation, and the OS (operating system) installed in the computer terminal.
tems (registered trademark) language, etc., a programming language that does not depend at all on the model or OS appears, and various computer terminals such as personal computers and workstations execute common programs, and perform display processing, calculation processing, and other operations. Processing can be performed.

[0007]

Recently, a network information processing apparatus has been developed as a type (for example, an expansion board) of the above-mentioned control and monitoring apparatus incorporated in, for example, an empty slot. This network information processing apparatus has a processing processor inside and uses a program language of an interpreter type (hereinafter, also simply referred to as Java language), such as Java language, which does not depend on a device, a model, or an OS. Can be transmitted between the control monitoring device and an external device connected to the network.

However, since the same processor is in charge of the interpretation and processing of the Java language, the collection and setting of data such as state quantity data from the control and monitoring target of the control and monitoring device, and the input and output processing of data to and from the network, the processing of the processor There is a first problem that it is difficult to apply to a system / plant which has a high load and needs to constantly collect a large amount of state data such as power system monitoring.

Another reason for separately connecting a plurality of remotely located control and monitoring devices so that data communication can be performed using a dedicated line is that a plurality of remotely located control and monitoring devices are synchronized with each other. Therefore, it is necessary to perform processing such as control and exchange of state quantity data.

[0010] For example, a plurality of remotely arranged control / monitoring devices constituting a control / monitoring system for an electric power system constantly exchange state quantities (state quantity data) such as voltage and current of the electric power system among the plurality of control / monitoring devices. Since power system failures are determined by measuring and comparing the phase relationship among a plurality of control monitoring devices, it is very important for each control monitoring device to collect (measure) state quantities in synchronization with each other. Has become important.

However, when performing cooperative control such as synchronous control among a plurality of remotely arranged control and monitoring devices, a newly developed network information processing device and the Internet or the like can be used without using the above-mentioned dedicated line. When the general-purpose network is used, it is difficult to accurately synchronize the control and monitoring devices remotely arranged on the general-purpose network. That is, for example, in the case of power system control and monitoring, the synchronization between the control and monitoring devices requires an accuracy of about 100 microseconds, but the transmission delay and transmission time variation of data via a general-purpose network are from several hundred milliseconds. Due to the existence of several seconds, it is extremely difficult to achieve synchronization that satisfies the required accuracy among a plurality of control monitoring devices, and there has been a risk of deteriorating the reliability of the control monitoring system.

Further, in a conventional control / monitoring system composed of a plurality of control / monitoring devices, if the amount of computation of each control / monitoring device is large, the processing processors of each control / monitoring device are multiplexed, and the multiplexed plural processors are monitored. It is also adopted that parallel processing is performed by a processor.

However, when each control / monitoring device of the control / monitoring system performs parallel processing by a plurality of multiplexed processors, a specific processor performs data input / output processing and communication processing with the outside via a network. It was like. Therefore, when the specific processor fails, it is not possible to notify the failure of the specific processor to the outside via a network, and there is a risk that the reliability of the control and monitoring system is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and includes a process of transmitting and receiving a program and data to and from an external device via a network, a process of interpreting a program (instruction), and a process of collecting a state quantity from a control monitoring object. It is necessary to collect a large amount of state quantity data at all times, such as a power system monitoring system, by providing an embedded network information processing device that can execute processing without increasing the processing load on the processor. It is a first object of the present invention to improve the applicability of a built-in network information processing device to each control monitoring device that constitutes a control monitoring system having certain functions.

Further, the present invention has been made in view of the above-described circumstances, and even when a general-purpose network such as the Internet is used, a plurality of data can be transmitted regardless of a delay in data transmission and a variation in transmission time via the general-purpose network. Provided is an embedded network information processing apparatus capable of achieving synchronization that satisfies required accuracy between control and monitoring apparatuses, thereby improving the reliability of a control and monitoring system in which the embedded network information processing apparatus is incorporated. This is its second purpose.

Further, the present invention has been made in view of the above-mentioned circumstances, and has been made in consideration of the above circumstances. A third object of the present invention is to provide a network information processing apparatus to improve the reliability of a control and monitoring system in which the embedded network information processing apparatus is incorporated.

[0017]

According to an embedded network information processing apparatus according to the present invention, the embedded network information processing apparatus is incorporated in an apparatus for controlling and monitoring a control monitoring target based on state data representing a state quantity of the control monitoring target. A built-in network information processing apparatus that is used and that can collect external information via a general-purpose network. The embedded network information processing apparatus is connected to the general-purpose network and performs an interface process between the general-purpose network and the embedded network information processing apparatus. Interface means, first processing means for performing a process of transmitting and receiving programs and data between the general-purpose network and the interface means with the outside, and processing of interpreting and executing the received program; Second processing means for performing a process of collecting status data relating to the monitoring target; A hardware shared resource commonly accessible from the first and second processing means, and a shared operation processing unit for performing a predetermined operation process; and a shared operation processing unit for performing the predetermined operation processing, the first processing unit and the second processing unit. There is provided an access adjusting means for adjusting two independent accesses to the sharing operation processing unit in accordance with the timing of the access.

In a preferred aspect of the present invention, the sharing operation processing unit includes a time measuring unit for measuring an actual time, and an input / output unit for inputting / outputting data from / to the embedded network information processing device other than via the general-purpose network. An output unit, wherein the time measuring unit and the input / output unit are connected to a shared bus shared by the first processing unit and the second processing unit, and the first processing unit A function of interpreting a program transmitted from the outside via the general-purpose network and the interface means, a function of receiving state quantity data required based on the interpretation from the second processing means, and processing the same; Each having a function of transmitting a processing result to the general-purpose network via the interface means, wherein the second processing means A function of sequentially collecting the state quantity data of the control and monitoring target; accessing the time measuring unit via the access adjusting means to obtain the time measured by the time measuring means and adding the time to the collected state quantity data And the function of reading out the state quantity data corresponding to the request from the stored state quantity data with time in response to the request of the first processing means and delivering the data to the first processing means. Each has it.

According to a preferred aspect of the present invention, the first processing means includes a first processing unit for a shared bus of the shared operation processing unit.
And a first access request signal for requesting access to the shared operation processing unit to the access adjustment unit via the first bus. The second processing unit is connected to the shared bus of the shared operation processing unit by a second bus, and requests the access adjustment unit to access the shared operation processing unit via the second bus. And a second access request signal for transmitting and receiving the first bus, the second bus, and the shared bus. A second gate unit; a delay circuit that delays the first access signal and the second access signal by one clock to generate first and second delay signals; And performs a logical operation with the second access signal and said first and second delay signals,
A logic operation circuit for controlling the opening and closing of the first and second gates according to the result of the logic operation.

According to a preferred aspect of the present invention, a first program for storing the program and data which are connected to the first buffer and processed by the first processing unit.
A data storage unit; and a second program / data storage unit connected to the second buffer for storing the program and data processed by the second processing unit. A shared data storage area accessible by the first processing unit and the second processing unit is set in at least one of the storage areas of the program data storage means. The unit and the second processing unit are configured to access the shared data storage area to retrieve a program or data processed by another processing unit, while the access adjustment unit is configured to access the shared data storage area. Processing unit and the second
The processing unit also has a function of adjusting two independent accesses to the shared data storage area in accordance with the timing of those accesses.

As a preferred aspect of the present invention, a boot program storage means common to the first and second processing means and storing a boot program common to the first and second processing means, Starting signal supplying means for supplying a starting signal to the first processing means and the second processing means with a time difference, and wherein the first processing means and the second processing means supply the starting signal Means for starting with a time difference from each other in response to a start signal supplied with a time difference, and executing the common start-up programs stored in the start-up program storage means with a time difference from each other to perform an initialization process. I have.

As a preferred mode of the present invention, the interface means has shared interface means connected to the shared bus as hardware shared resources which can be commonly accessed from the first and second processing means. The first processing means, when an abnormality occurs in the second processing means, notifies the occurrence of the abnormality in the second processing means to the outside via the shared interface means and the general-purpose network. And the second
Is configured to notify the occurrence of an abnormality in the first processing unit to the outside via the shared interface unit and the general-purpose network when an abnormality occurs in the first processing unit. .

In a preferred aspect of the present invention, the apparatus further comprises a precise time acquiring means for acquiring a precise time, wherein the second processing means converts the precise time acquired by the precise time acquiring means into collected state quantity data. It is designed to be added and stored.

As a preferred aspect of the present invention, there are a plurality of the control and monitoring devices, and the embedded network information processing device described above is incorporated in each of the plurality of the control and monitoring devices to form a control and monitoring system. At least one information processing device in the embedded network information processing device is connected to another information processing device by a communication line different from the general-purpose network, and the other information processing device is connected to the precise time acquisition unit. Means for superimposing a signal representing each time timing constituting the precise time obtained by the above and time data representing the time of each time timing and transmitting the signal to the at least one information processing device via the communication line. Wherein the precise time acquisition means of the at least one information processing device communicates with the other information processing means via the communication line. A signal representative of the respective time timing decodes the superimposed signal transmitted Te, a means for obtaining the precise time separated into the time data representing the time of each time timing.

In a preferred aspect, the apparatus further comprises a sampling signal generating means for generating a data sampling signal synchronized with a time timing such as the precise time and transmitting the data sampling signal to the second processing section. The collection processing of the state quantity data is performed in synchronization with the data sampling signal.

In a preferred aspect, the apparatus further comprises a data sampling signal generating means for generating a data sampling signal synchronized with a time timing such as the precise time and transmitting the data sampling signal to the control monitoring device. The state quantity data collected from is output to the embedded network information processing device via the shared bus in synchronization with the transmitted data sampling signal, and is connected to the shared bus. Automatic storage means for automatically storing state quantity data output in synchronization with the data sampling signal via the shared bus.

[0027] As a preferred embodiment, there is provided display means capable of displaying the state quantity data and the like as hardware shared resources which can be commonly accessed from the first and second processing means, respectively, and the first processing means is provided. When an abnormality has occurred in the second processing means, the occurrence of an abnormality in the second processing means is displayed via the display means, and the second processing means is configured to display the first processing means. When an abnormality has occurred in the processing means, the occurrence of an abnormality in the first processing means is displayed via the display means.

As a preferred mode, the first program data storage means and the second program data storage means are constituted by removable storage media.

In a preferred embodiment, the first processing unit and the second processing unit are detachably mounted on the first program data storage unit and the second program storage unit.
The data storage means includes automatic discrimination means for automatically discriminating the type and capacity of a storage medium mounted on the embedded network information processing apparatus. Write data to the address, read data from the predetermined address, compare the write data with the read data,
The type and capacity of the storage medium are automatically determined according to the comparison result.

In a preferred embodiment, the boot program storage means is constituted by a writable and removable storage medium.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an embedded network information processing apparatus according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a first embodiment of the present invention is incorporated. FIG.

According to FIG. 1, the control and monitoring system 1 is installed in each of a plurality of control monitoring stations (control stations; only one control station is shown in this embodiment) Ca, A control and monitoring device 3 for monitoring and controlling the control and monitoring target 2 having the equipment, and a manned control station Cb provided, for example, at a distance from each control and monitoring device 3 to operate the control and monitoring device 3 An external display / operation device 4 for remotely monitoring and controlling the status is provided. Each control / monitoring device 3 and the display / operation device 4 can transmit and receive data via a general-purpose communication network 5 such as an intranet or the Internet. And the control and monitoring system 1 is constructed.

Each control and monitoring device 3 communicates with the control monitoring unit 7 that constantly (at regular intervals) obtains state quantity data representing the state quantity of the control monitoring target 2 from the control monitoring target 2, An embedded network information processing device 8 for performing a transmission / reception interface process of information (data program) related to the network 5 and a process of interpreting and executing a received program. The embedded network information processing device 8 is configured by mounting various circuit components (such as an LSI) such as a CPU, a memory, and an input / output interface on a board, and is mounted in, for example, an empty slot of the control monitoring device 3. Thereby, it is incorporated in the control monitoring device 3.

FIG. 1 also shows a functional block configuration of the embedded network information processing device 8. According to FIG. 1, the embedded network information processing device 8 is used for interfacing the data and the movable program module {the data for monitoring and control and the program in which the procedure for monitoring and control are integrated (module)} with the communication network 5. The communication interface unit 10 is connected to the communication interface unit 10 via a data transmission / reception bus B1.
0, a first arithmetic processing unit for performing transmission / reception processing of data and program modules with the outside (for example, the display operation device 4 or another control monitoring device) and interpretation / execution processing of the received program modules And a second arithmetic processing unit 12 for collecting state quantity data constantly acquired by the control monitoring unit 7.

The first arithmetic processing unit 11 has a first storage unit (memory) R1 for storing data and programs (including program modules and start-up programs) and a memory for accessing the first storage unit R1. The second arithmetic processing unit 12 is specifically configured by an arithmetic processing processor including an access circuit, and the second arithmetic processing unit 12 stores a program module (including a startup program) and state amount data and the like. Memory) R2 and second
Has an access memory access circuit, and is specifically configured by an arithmetic processing processor that is separate from the first arithmetic processing unit 11 in hardware.

That is, the first arithmetic processing section 11 receives data and program modules transmitted from outside activated by the activation program and processes the received data and program modules.
To memorize. Then, the first arithmetic processing unit 11 interprets various processing instructions included in the program module stored in the first storage unit R1.

Then, the first arithmetic processing unit 11 receives the state quantity data requested based on the instruction interpretation from the second arithmetic processing unit 12, processes the received state quantity data, and processes the processing result. A necessary command is transmitted to the second arithmetic processing unit 12 based on the data representing
For example, the data and the program module representing the processing result are integrated (integrated into the program module)
Then, the data is transmitted to the outside (the display operation device 4, another control monitoring device, etc.) via the communication interface unit 10 and the communication network 5.

The second arithmetic processing section 12 collects the state quantity data acquired by the control and monitoring unit 7 constantly (at a fixed period) and stores it in the second storage section R2. Based on the command transmitted from the unit 11, of the state quantity data stored in the second storage unit R <b> 2, the state quantity data requested by the first arithmetic processing unit 11 is replaced with the first arithmetic processing unit 11. Handover (supply). Further, based on the command transmitted from the first calculation processing unit 11, the second arithmetic processing unit 12 sends an operation command to the control monitoring unit 7 based on the command (for example, a predetermined command of the control monitoring target 2). An operation command for the equipment is transmitted, and the equipment corresponding to the control / monitoring target 2 operates according to the content of the operation command transmitted via the control / monitoring unit 7.

Further, the embedded network information processing device 8 includes, as hardware shared resources accessible from the first arithmetic processing unit 11 and the second arithmetic processing unit 12, the first and second A general-purpose clock unit 15 and a general input / output unit (input / output port) 16 are connected to a shared bus BC shared by the second arithmetic processing units 11 and 12.

The general-purpose clock section 15 always measures (counts) the actual time (real time), and outputs common time data in response to requests from the first arithmetic processing section 11 and the second arithmetic processing section 12, respectively. The general input / output unit 16 is a data input / output unit other than via the communication network 5, and performs other processing (display processing, etc.) necessary for the operation of the embedded network information processing device 8. It is used for software debugging of the first arithmetic processing unit 11 and the second arithmetic processing unit 12, and the like.

The first and second arithmetic processing units 1
General-purpose clock unit 15 commonly accessed by 1 and 12
The general input / output unit 16 is also referred to as a shared resource unit 17.

For example, the second arithmetic processing unit 12 accesses the general-purpose clock unit 15 in accordance with the collection of the state quantity data from the control monitoring unit 7 to sequentially acquire time data, and adds the time data to the collected state quantity data. The data is added and stored in the second storage unit R2 as state amount data with time.

As shown in FIG. 1, the embedded network information processing apparatus 8 according to the present embodiment includes a shared resource unit 17 from the first arithmetic processing unit 11 and the second arithmetic processing unit 12.
An arbitration processing unit 18 is provided for arbitrating (adjusting) the access timing to the (general-purpose clock unit 15 and the general input / output unit 16) and smoothly executing the access processing. The arbitration processing unit 18 communicates with the shared resource unit 17 (general clock unit 15 and general input / output unit 1) via the shared bus BC.
6) and the control / monitoring unit 7, and are also connected to the first arithmetic processing unit 11 via the bus B1 and to the second arithmetic processing unit 12 via the bus B2.

FIG. 2 is a circuit block diagram showing the internal configuration of the arbitration processing unit 18 in the form of hard-wired logic.
It should be noted that the circuit block configuration shown in hard wired logic in FIG. 2 can also be configured in an equivalent programmed logic.

As shown in FIG. 2, the arbitration processing unit 18 operates using a clock output unit 20 for outputting a clock signal and a clock signal output from the clock output unit 20 as common operation timing (hereinafter, referred to as the above-mentioned operation). The clock signal is referred to as a common clock signal CK), the first arithmetic processing unit 11
An access request signal REQ1 to the shared resource unit 17 transmitted from the second processing unit 12 and an access request signal REQ2 to the shared resource unit 17 transmitted from the
First and second latches 21 and 22 for delaying one clock each, and a bus B1 and a shared bus BC between the first arithmetic processing unit 11 and the shared resource unit 17 are opened and closed to perform a first arithmetic operation. A first gate buffer 23 for controlling the data transmission and reception between the processing unit 11 and the shared resource unit 17 to be enabled (→ open) and disabled (→ closed); a second arithmetic processing unit 12 and the shared resource unit 17 Between the second arithmetic processing unit 12 and the shared resource unit 17 by opening and closing the bus B2 and the shared bus BC between
(Closed).

The arbitration processing section 18 includes an arbitration logic circuit 25 that performs logical operation according to the common clock signal CK. The arbitration logic circuit 25 includes the first arithmetic processing unit 11
Request signal REQ1 and first latch 2
Whether the 1-clock delay signal DRQ1 of the access request signal REQ1 from 1 has been transmitted (if transmitted → true, not transmitted → false), and the second
And the access request signal REQ from the second latch 22.
2 1 clock delay signal DRQ2 has been transmitted (if transmitted → true, not transmitted →
False), that is, each signal (REQ1, DRQ1, REQ)
2) and an arbitration logical operation based on DRQ2), and the first gate buffer 2
3, a signal (access response signal ACK1; opening operation → true, closing operation → false) for opening or closing the gate buffer 23, and opening or closing the gate buffer 24 to the second gate buffer 24. A signal for performing the closing operation (access response signal ACK2; opening operation → true, closing operation → false) is transmitted.

The arbitration logic circuit 25 sends a processing completion signal END1 indicating completion of the access processing to the first arithmetic processing unit 11 after a certain period of time has elapsed since the transmission of the access response signal ACK1 of "true". After the transmission and transmission of the “true” access response signal ACK2, a processing completion signal END2 indicating completion of the access processing is transmitted to the second arithmetic processing unit 12 after a lapse of a predetermined time. , The first and second arithmetic processing units 11 and 12 end the access processing to the shared resource unit 17 in response to the processing completion signals END1 and END2.

Next, using the truth table T1 for representing the arbitration logic operation of the arbitration logic circuit 25 shown in FIG. The operation of the arbitration processing unit 18 will be mainly described.

In the embedded network information processing apparatus 8 of the present embodiment, the access request signals REQ1 and REQ2 to the shared resource unit 17 are transmitted from both the first processing unit 11 and the second processing unit 12 to the arbitration logic. Circuit 2
5 (both REQ1 • DRQ1 and REQ2 • DRQ2 are “false”), the arbitration logic circuit 25 uses the truth table shown in FIG. A false access response signal ACK1 and ACK2 are transmitted. As a result, all the gate buffers 23 and 24 are closed.

When the gate buffers 23 and 24 are closed, for example, the access request signal REQ2 from the second arithmetic processing unit 12 and the one-clock delay signal obtained by delaying the access request signal REQ2 from the second latch 22 by one clock. When DRQ2 is transmitted to the arbitration logic circuit 25, REQ2 · DRQ2 → “true”, ACK1 →
Since “false” and DRQ1 → “false”, the access response signal ACK2 becomes “true” according to the truth table shown in FIG. 3, and the second gate buffer 24 operates to open.

As a result, access of the second arithmetic processing unit 12 to the shared resource unit 17 is permitted, and the second arithmetic processing unit 12 accesses the shared resource unit 17 (for example, the general-purpose clock unit 15). (A process of acquiring time data from the server).

The second arithmetic processing unit 12 to which access is permitted
, After the access processing is completed {after a predetermined time has passed since access permission (ACK2 → “true”)}, the processing completion signal END2 is transmitted to the second arithmetic processing unit 12
Is terminated.

The same applies to the case where the first access request signal REQ1 is transmitted from the first arithmetic processing unit 11.

In the present embodiment, one of the arithmetic processing units (for example, the second arithmetic processing unit 12) sends the access request signal (for example, REQ2) to the shared resource unit 17 first (at least one clock ahead). ) Is transmitted, the access request signal (for example, R) from the other arithmetic processing unit (for example, the first arithmetic processing unit 11) at the next clock.
EQ1) is transmitted (that is, even if simultaneous access is performed), the access request signals REQ2 and REQ2 are not transmitted.
Since all of the clock delay signals DRQ2 become “true”, the shared resource unit 17 cannot be accessed as is apparent from the truth table shown in FIG. That is, in the present embodiment, each of the arithmetic processing units 11, 1
2, the arithmetic processing unit that has been requested to access earlier (one clock or more ahead) is given priority for access.

In this embodiment, when the access request signals are transmitted from the first and second processing units 11 and 12 to the shared resource unit 17 completely simultaneously, the truth shown in FIG. According to the value table, the access request from the first arithmetic processing unit 11 has priority.

As described above, according to the control / monitoring device 3 in which the embedded network information processing device 8 of the present embodiment is incorporated, an external device which requires a relatively long processing time (for example, another control device which is remotely located). A dedicated arithmetic processing unit (first arithmetic processing unit 11) for transmitting / receiving data / program modules to / from the display / operation device 4) at the location Cb and interpreting instructions.
Control monitoring target 2 that needs to be repeatedly executed at high speed (at least real time (real time) or more)
Can collect the state quantity data from each other, and can suppress the processing load on each of the arithmetic processing units 11 and 12. Therefore, the embedded network information processing device 8 of the present embodiment is sufficiently provided for each control and monitoring device of the control and monitoring system for a system or plant that needs to constantly collect a large amount of state quantity data such as power system monitoring. It can be applied, and its applicability and practicality can be improved.

Further, the embedded network information processing apparatus of the present embodiment is different from the first and second embodiments in that the above-described external data / program module transmission / reception processing and interpretation processing and the state quantity data collection processing are different. In the case where the processing is executed by the arithmetic processing units 11 and 12, the hardware resources accessed by the first and second arithmetic processing units 11 and 12 (in the present embodiment, the general-purpose clock unit 1)
5. If the general input / output unit 16) is provided for each of the first and second arithmetic processing units 11 and 12, a common hardware resource will be provided twice, and the embedded network information processing apparatus will be provided. This may increase the size and cost of the device, and may adversely affect the applicability and practicality.

However, according to the present embodiment, the first
Hardware resources (general-purpose clock unit 15 and general input / output unit 16) accessed by the first and second arithmetic processing units 11 and 12 are shared by a single unit. Arbitration processing unit 1 for arbitrating access timing to shared hardware resources
8, the simultaneous access to the shared hardware resources from the plurality of arithmetic processing units 11 and 12 can be avoided, and both accesses can be performed smoothly. And it can be realized without adversely affecting practicality.

In this embodiment, the arbitration processing unit 1
8, the arbitration logic circuit 25 performs the arbitration logic operation based on the truth table T1 shown in FIG. 3, but this is merely an example, and the arbitration logic circuit 25 changes the truth table and, for example, changes later (that is, the latest). It is also possible to perform a desired logical operation, such as a logical operation in which access is preferentially permitted.

(Second Embodiment) FIG. 4 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating an embedded network information processing device according to a second embodiment of the present invention. It is. In FIG. 4, the same components as those of the functional block configuration of the control monitoring system 1 and the embedded network information processing device 8 shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 4, the embedded network information processing device 8A of the control and monitoring system 1A of the present embodiment is connected to the bus B1 and is connected to a dedicated semiconductor memory or the like of the first arithmetic processing unit 11. A first program / data storage unit 31 is configured, and a second program / data storage unit 32 connected to the bus B2 and configured from a semiconductor memory or the like dedicated to the second arithmetic processing unit 12 is provided. ing.

The first program / data storage unit 31
Data and programs (including program modules and start-up programs) relating to the first arithmetic processing unit 11 are stored.
The data storage unit 32 stores state quantity data and programs (including a startup program) relating to the second arithmetic processing unit 12.
Etc. are stored.

Further, in the present embodiment, the data storage area of the second program / data storage section 32 has a shared data storage area RC (later accessible) by the first and second arithmetic processing sections 11 and 12, respectively. (Shown in FIG. 5) is preset.

In addition, the arbitration processing unit 18A of the present embodiment
The first arithmetic processing unit 11 and the second
Resource unit 17 (general clock unit 1)
5 and a process for arbitrating access to the general input / output unit 16), and a second program / data storage unit 3 from the first arithmetic processing unit 11 and the second arithmetic processing unit 12.
A process for arbitrating access to the second shared data storage area RC is performed.

FIG. 5 is a circuit block diagram showing the internal configuration of the arbitration processing unit 18A in the form of hard-wired logic. In FIG. 5, the arbitration processing unit 18 shown in FIG.
The same components as those of the circuit block configuration of A are denoted by the same reference numerals, and description thereof will be omitted.

As in the first embodiment, the arbitration logic circuit 25A of the arbitration processing unit 18A of the present embodiment includes the respective signals (REQ)
1, DRQ1, REQ2, and DRQ2) to execute an arbitration logical operation to control the opening and closing of the first gate buffer 23 and the second gate buffer 24 related to the access to the common resource unit 17. .

Further, the arbitration logic circuit 25A of this embodiment
Transmits a shared data storage area surrender request signal BREQ to the second arithmetic processing unit 12 in response to the access request signal REQC for the shared data storage area RC transmitted from the first arithmetic processing unit 11, When the shared data storage area delivery response signal BGN is returned from the second arithmetic processing unit 12, the shared data storage area delivery response signal BGN
An access response signal ACK1 and an access response signal ACK2 for opening the first and second gate buffers 23 and 24 according to T are transmitted to the first gate buffer 23 and the second gate buffer 24, respectively. I have.

When the intermediate gate buffers 23 and 24 open in response to the shared data storage area handover response signal BGNT, the arbitration logic circuit 25A sends the second program / data storage section 32 A signal (access signal MACC to the shared data storage area) required for accessing the shared data storage area RC is transmitted, and as a result, the first arithmetic processing unit 11 causes the second program / data storage unit 3
The second shared data storage area RC can be accessed.

Further, the arbitration logic circuit 25A sends the first true processing response unit ACK1 after transmitting the "true" access response signal ACK1 and transmitting the access signal MACC to the shared data storage area for a predetermined time. 11 and transmits a processing completion signal END1 indicating completion of the access processing, and "true".
After a certain period of time has passed since the transmission of the access response signal ACK2, the processing completion signal END2 indicating the completion of the access processing is transmitted to the second arithmetic processing unit 12, and the first and second processing units are transmitted. The arithmetic processing units 11 and 12
The access processing is terminated according to the processing completion signals END1 and END2.

Next, using the truth table T2 for expressing the arbitration logic operation of the arbitration logic circuit 25A shown in FIG. The description focuses on the operation processing of the arbitration processing unit 18A.

In the embedded network information processing apparatus 8 A of this embodiment, the shared data storage area access request signal REQC is sent from the first arithmetic processing unit 11 to the arbitration logic circuit 2.
5A (REQC → “true”), the arbitration logic circuit 25A transmits the shared data storage area delivery request signal BREQ to the second arithmetic processing unit 12 according to the truth table T2 shown in FIG. I do.

At this time, the second arithmetic processing unit 12 responds to the shared data storage area delivery request signal BREQ (BRE
Q → “true”), as soon as the current resource access {access to the second program / data storage unit 32 (shared data storage area RC)} is completed, the subsequent resource access is immediately stopped and the second program The right to use the data storage unit 32 is released, and the shared data storage area yield response signal BGNT is returned to the arbitration logic circuit 25A.

When the shared data storage area handover response signal BGNT is transmitted from the second processing unit 12 (REQC → “true”, BGNT →
"True"), the access response signal ACK1 and the access response signal ACK2 are respectively transmitted to the first gate buffer 23 and the second gate buffer 24 to open both gate buffers 23 and 24, and the truth shown in FIG. Based on the value table T2, an access signal MACC to the shared data storage area is transmitted to the second program / data storage unit 32.

As a result, the access of the first arithmetic processing unit 11 to the shared data storage area RC is permitted, and the first arithmetic processing unit 11
Access to C (for example, acquisition processing of state quantity data) is performed.

First operation processing unit 11 to which access is permitted
For the access permission (access (MACC →
After a lapse of a certain period of time since “true”, the processing completion signal EN
D1 is transmitted, and the access processing of the first arithmetic processing unit 11 to the shared data storage area RC ends.

When the access of the first arithmetic processing unit 11 to the shared data storage area RC ends, the arbitration logic circuit 2
5A transmits the access end to the second arithmetic processing unit 12. As a result, the second arithmetic processing unit 12 executes its own resource access ｛the second program / data storage unit 32
Access # to (shared data storage area RC) is resumed.

As described above, according to the present embodiment,
Dedicated program / data storage units 31 and 32 for the first arithmetic processing unit 11 and the second arithmetic processing unit 12 are provided;
Further, since a shared data storage area accessible from either of the arithmetic processing units 11 and 12 is provided for one program / data storage unit 32, the first arithmetic processing unit 11
And the processing of the second arithmetic processing unit 12 can be accelerated, and the data storage capacity of the program / data storage unit 31 having no shared data storage area can be significantly reduced.

Therefore, it is possible to minimize the capacity of a storage unit such as a semiconductor memory, which greatly affects the scale and price of hardware (embedded network information processing device hardware). The size can be reduced and the cost can be reduced.

In the present embodiment, the shared data storage area RC is set in a part of the second program / data storage unit 32 related to the second arithmetic processing unit 12, but the present invention is not limited to this. Instead, a shared data storage area may be set in a part of the first program / data storage unit 31 relating to the first arithmetic processing unit 11. It is also possible to set a shared data storage area in each of the program data storage units 31 and 32.

The above both program / data storage units 31
If a shared data storage area is set for each of the two processing units 11 and 12, for example, if the two processing units 11 and 12 simultaneously access the shared data storage region on the program data storage unit held by the other processing unit, The arithmetic processing unit cannot return an access response signal to the other arithmetic processing unit.
In some cases, a so-called deadlock occurs in which the access processing of Step 2 is stopped. Therefore, the above-mentioned deadlock measures are required.

As a deadlock countermeasure function, it is determined in advance when both arithmetic processing units 11 and 12 simultaneously request access to shared data storage areas RC1 and RC2 of the other party to arbitration logic circuit 25A. An error signal is transmitted to one of the arithmetic processing units (for example, the arithmetic processing unit 11), the access by the corresponding arithmetic processing unit 11 is forcibly stopped, and the other arithmetic processing unit (for example, the arithmetic processing unit 12) is It is desirable to include a function that allows access.

With this configuration, the first arithmetic processing unit 11 forcibly stops the access of the second arithmetic processing unit 12 to the shared data storage area RC2 by the transmitted error signal. The second arithmetic processing unit 12 can execute the first arithmetic processing unit 11 without causing a deadlock.
Access to the supply data storage area RC1.

At this time, the first access stopped
The arithmetic processing unit 11 is configured to access the shared data storage area RC2 again after an appropriate waiting time for stopping the access, so that the arithmetic processing unit 11 does not generate a deadlock. And 12 can access the other shared data storage area.

(Third Embodiment) FIG. 7 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating a built-in network information processing device according to a third embodiment of the present invention. It is. In FIG. 7, the same components as those of the functional block configuration of the control monitoring system 1 and the embedded network information processing device 8 shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

According to FIG. 7, the first arithmetic processing unit 11 and the second arithmetic processing unit 12 in the embedded network information processing device 8B of the control monitoring system 1B of the present embodiment.
Are composed of the same kind of arithmetic processing processors, respectively, and the initialization portions of the startup programs of the first arithmetic processing unit 11 and the second arithmetic processing unit 12 are exactly the same.

Therefore, the embedded network information processing device 8B of the present embodiment is connected to the shared bus BC as hardware shared resources accessible from the first arithmetic processing unit 11 and the second arithmetic processing unit 12, respectively. And a non-volatile start-up program storage unit 35 provided. The non-volatile start-up program storage unit 35 stores a start-up program Pc (hereinafter, also referred to as an initialization program) common to the first operation processing unit 11 and the second operation processing unit 12.
Is stored in a rewritable manner, and an initialization program unique to each of the first arithmetic processing unit 11 and the second arithmetic processing unit 12 is deleted.

The nonvolatile boot program storage unit 35
Is a processing program P1 unique to each arithmetic processing unit after initialization.
(For the arithmetic processing unit 11) and P2 (for the arithmetic processing unit 12) are stored at predetermined addresses.

The embedded network information processing apparatus 8
B is the first arithmetic processing unit 11 and the second arithmetic processing unit 1
Start signal generating unit 36 capable of generating and transmitting initialization start signals S1 and S2 at a predetermined timing for each of them.
It has.

Further, the embedded network information processing device 8B determines whether the initialized arithmetic processing unit is the first arithmetic processing unit 11 or the second arithmetic processing unit 12. The units 37 and 38 are provided for each arithmetic processing unit.

According to the present embodiment, the non-volatile start-up program storage is performed by sharing the initialization programs possessed by the first arithmetic processing unit 11 and the second arithmetic processing unit 12 each composed of the same type of processor. By storing in the unit 35, the initialization processing of each of the first arithmetic processing unit 11 and the second arithmetic processing unit 12 can be unified,
In addition, the storage capacity of the program storage unit (the first storage unit R1 and the second storage unit R2) can be saved.

In this embodiment, when the first arithmetic processing unit 11 and the second arithmetic processing unit 12 simultaneously start initialization using the common nonvolatile boot program storage unit 35, an access error may occur depending on the processor. May occur. In general, inconvenience in timing often occurs.

Therefore, in the present embodiment, the activation signal generation unit 36 supplies the activation signal S1 to the first arithmetic processing unit 11 and the activation signal S2 to the second arithmetic processing unit 12 with a time difference. Simultaneous initialization access is avoided to prevent the occurrence of access abnormality and timing inconvenience.

That is, according to the present embodiment, as shown in the time chart of FIG. 8, when power is supplied to the embedded network information processing device 8B, the activation signal The start signal S1 is transmitted to one of the arithmetic processing units (for example, the first arithmetic processing unit 11).

At this time, the arithmetic processing unit 11 stores the nonvolatile startup program storage unit 35 in response to the transmitted startup signal S1.
The initialization program Pc is read from the CPU, and an initialization process is performed based on the initialization program Pc. The arithmetic processing unit 11 that has completed the initialization processing enters a standby state.

On the other hand, the activation signal generator 36 supplies the activation signal S
After a time sufficient for completing the initialization processing has elapsed after transmitting 1, the activation signal S2 is transmitted to the other arithmetic processing unit (for example, the second arithmetic processing unit 12).

The arithmetic processing unit 12 transmits the start signal S
2, the initialization program Pc is read from the nonvolatile startup program storage unit 35, and the initialization program Pc is read.
Is performed on the basis of. The arithmetic processing unit 12 that has completed the initialization process enters a standby state.

The arithmetic processing units 11 and 12 which have been in the standby state after the initialization process have been completed,
Access is made to 38 to determine whether or not it is the first arithmetic processing unit or the second arithmetic processing unit. Then, the first and second arithmetic processing units 11 and 12 respectively read out the corresponding unique processing programs P1 and P2 stored at predetermined addresses of the nonvolatile startup program storage unit 35, respectively, and read their own program storage units. The first
To the storage unit R1 and the second storage unit R2. The first and second arithmetic processing units 11 and 12 execute the specific processing by executing the unique processing programs P1 and P2 copied to the first storage unit R1 and the second storage unit R2, respectively. With this, all the starting processes are completed.

That is, according to the present embodiment, the simplification of the initialization processing based on the unification and the saving of the storage capacity based on the common start-up program are realized without causing an access abnormality or an inconvenience of timing. be able to.

(Fourth Embodiment) FIG. 9 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating an embedded network information processing device according to a fourth embodiment of the present invention. It is. In FIG. 9, the same components as those of the functional block configuration of the control monitoring system 1 and the embedded network information processing device 8 shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, the communication interface unit 10 is not connected to the bus B1 but to the shared bus BC, and is connected to the first arithmetic processing unit 11 and the second arithmetic processing unit 12. Are configured as hardware shared resources that can be accessed from each other.

In the present embodiment, normally, the first arithmetic processing unit 11 exclusively uses the communication interface unit 10 to exchange data with the outside (the display operation device 4 and the like) via the communication network 5. And program module transmission / reception processing.

According to the present embodiment, for example, if the second arithmetic processing unit fails for some reason, the first arithmetic processing unit 11 can use the appropriate method to determine whether the second arithmetic processing unit 12 has failed. To get to know. For example, as described in the second embodiment, the second storage unit R of the second arithmetic processing unit 12
2, a shared data storage area is set, and the second arithmetic processing unit 1 is periodically set in a part of the shared data storage area.
2 defines the part where the value is rewritten. Then, the first arithmetic processing unit 11 determines that the second arithmetic processing unit 12 has failed if the portion in which the value of the shared data storage area is rewritten has not been updated for a certain period of time.

At this time, the first arithmetic processing unit 11 transmits the second operation data from the communication interface unit 10 to the outside (the display operation device 4 or the like) via the communication network 5 from the communication interface unit 10 by a predetermined method (communication procedure, communication program). Of the arithmetic processing unit 12 is notified.

Further, in the present embodiment, a communication program at the time of abnormality (for example, at the time of failure of the first arithmetic processing unit 11) is stored in advance in the second storage unit R2 of the second arithmetic processing unit 12. When the first arithmetic processing unit 11 fails, the second arithmetic processing unit 12
1, the failure of the first arithmetic processing unit 11 is recognized, the communication program is executed, and the communication interface unit 1 is executed.
0 and a failure of the first arithmetic processing unit 11 is notified to the outside via the communication network 5.

That is, according to the present embodiment, the first arithmetic processing which is a specific processor which exclusively performs the transmission / reception processing of the data / program module with the outside (the display / operation device 4 etc.) via the communication network 5 Even when the unit 11 fails, the first arithmetic processing unit 1
Since the access right to the communication interface unit 10 possessed by the first processing unit 1 is extinguished, the second arithmetic processing unit 12 accesses the communication interface unit 10 and
Can be notified to the external display / operation device 4. Note that, even when the second arithmetic processing unit 12 fails, the failure can be notified to the external display operation device 4 by the processing of the first arithmetic processing unit 11.

Therefore, it is possible to promptly take an appropriate action for the failed arithmetic processing unit (processor),
The reliability of the embedded network information processing device 8C, the control monitoring device 3 incorporating the embedded network information processing device 8C, and the control monitoring system 1C can be improved.

Further, in the present embodiment, when the first arithmetic processing unit 11 fails, the second arithmetic processing unit 12 performs the functions of the first arithmetic processing unit 11 (data and data exchange with the outside).
Back up program transmission / reception processing and program module interpretation processing, etc.
In the event that 2 fails, the first arithmetic processing unit 11 performs the function of the second arithmetic processing unit 12 (state quantity data collection processing, etc.).
May be configured to be backed up. In this case, even if one of the arithmetic processing units fails, the operation processing of the control monitoring device 3 can be continued, so that the control monitoring efficiency and the reliability thereof can be further improved. .

(Fifth Embodiment) FIG. 10 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating an embedded network information processing device according to a fifth embodiment of the present invention. It is. In FIG. 10, the same components as those of the functional block configuration of the control monitoring system 1 and the embedded network information processing device 8 shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The embedded network information processing device 8D of the control monitoring system 1D according to the present embodiment has a predetermined accuracy {accuracy according to the control monitoring target, such as high accuracy of about 1 μs and accuracy of about 1 second, for example}. (Hereinafter, a time having a predetermined precision is defined as a precision time) as a precision time detecting means for detecting and acquiring
A precise time receiving unit 40 and a precise time receiving antenna 41 for detecting a time having a high precision of about 1 μs (hereinafter referred to as an absolute time) are provided. The precise time receiving unit 40 is connected to the shared bus BC. They are connected and configured as hardware shared resources that can be accessed from the first arithmetic processing unit 11 and the second arithmetic processing unit 12, respectively.

The precision time receiving unit 40 is a navigation system which is transmitted from a plurality (for example, four or more) of GPS (Global Positioning System) satellites (artificial satellites) equipped with an atomic clock having a constant vibration period of molecular vibration. Signal (navigation data,
(Hereinafter referred to as a GPS signal) via a GPS receiving antenna 41, which decodes the signal, obtains a three-dimensional position of the GPS antenna 41, and corrects a time lag based on the obtained three-dimensional position to obtain an accurate absolute signal. Time {a periodic signal (having an accuracy corresponding to the absolute time) having a constant period (usually 1 second period) representing each time timing and time data representing the time at each time timing; for example, the above-mentioned 1 μs accuracy} It has become.

For example, when the control and monitoring target is an electric power system, it is desirable that the precision required for the precise time be, for example, about 1 μs or more.

When collecting the state quantity data of the control / monitoring target from the control / monitoring target 2 via the control / monitoring unit 7, the second arithmetic processing unit 12 stores the status at a predetermined position in the second storage unit R 2. The precise time measured by the precise time receiving unit 40 is recorded together with the amount data.

That is, according to the present embodiment, even if a plurality of remotely located control and monitoring devices are connected via the general-purpose communication network 5 such as the Internet, the built-in Exchange and collation of state quantity data at the same timing can be performed between the network information processing apparatuses.

In the field of monitoring and control of electric power systems and the like, the phase matching of state data at a plurality of locations remotely located may be performed. It is possible to perform accurate phase matching. Therefore, it is possible to improve the reliability of the control monitoring system in which the embedded network information processing device of the present embodiment is incorporated.

In the present embodiment, the precise time is measured by receiving a GPS signal from a GPS satellite equipped with a plurality of atomic clocks. However, the present invention is not limited to this. JG2AS from Tsukuba
, Etc., and the precise time may be measured.

As a modification of the present embodiment, the second arithmetic processing unit 12 uses the precise time measured by the precise time receiving unit 40 when the precise time receiving unit 40 is operating normally. At the same time as collecting state data
The time calibration process of the general-purpose clock unit 15, that is, the real-time time measured by the general-purpose clock unit 15 and the precise time reception unit 4
By performing the process of calibrating the deviation from the precise time measured by 0 at an appropriate interval, the accuracy of the real-time time measured by the general-purpose clock unit 15 is corrected to an accurate time having the accuracy of the precise time. Has become.

In other words, according to the present embodiment, when the precise time receiving unit 40 cannot measure the precise time because the GPS signal or the terrestrial wave cannot be received due to, for example, deterioration of the radio wave condition, the second calculation is performed. The processing unit 12 can collect the state quantity data based on the accurate time having the precision of the precise time measured by the general-purpose clock unit 15 and corrected based on the precision time. Then, when the precise time measuring operation of the precise time receiving unit 40 is restored due to the improvement of the radio wave condition or the like, the second arithmetic processing unit 12 returns to the precise time receiving unit 40.
The use of the precise time measured by the above is resumed to perform the state quantity data collection processing.

Therefore, even when the precise time cannot be measured, the second arithmetic processing unit 12 can continue the state quantity data collection processing using the very accurate time having the precision of the precise time. Further, it is possible to provide a more reliable embedded network information processing apparatus, control monitoring apparatus, and control monitoring system.

(Sixth Embodiment) The precise time receiving unit described in the fifth embodiment is relatively expensive.
In addition, since peripheral devices such as an antenna for receiving GPS signals and terrestrial waves are required, a plurality of control and monitoring devices (embedded network information processing devices) are installed in the same building (control center). In such a case, providing peripheral devices such as a precision time receiving unit and an antenna in each of the embedded network information processing apparatuses has a problem in terms of cost.

Therefore, in the present embodiment, when a plurality of control monitoring apparatuses (embedded network information processing apparatuses) are installed in the same control station, each of the embedded network information processing apparatuses has a precise time receiving unit. In addition, the present invention proposes a configuration in which each embedded network information processing device can acquire a precise time without providing peripheral devices such as an antenna and the like.

That is, FIG. 11 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating an embedded network information processing device according to the sixth embodiment of the present invention having the above-described configuration. is there.

In the present embodiment, in the same building (control center) Ca, a plurality (two in FIG.
Control and monitoring devices 3E1 and 3E2. That is, the control monitoring devices 3E1 and 3E2 are disposed at positions close to each other. Note that FIG.
Here, only the embedded network information processing apparatuses 8E1 and 8E2 in the control monitoring apparatuses 3E1 and 3E are shown, and the control monitoring unit 7 is omitted.

One control monitoring device 3 in the same control station Ca
Embedded network information processing device 8 incorporated in E1
E1 includes, in addition to the functional block configurations of the embedded network information processing apparatus 8D shown in FIG.
A periodic signal (time timing signal; having precision corresponding to the precise time) representing each time timing constituting the precise time measured by 0 and time data representing the time of each time timing are superimposed, and the superimposed signal is obtained. A time timing superimposing unit 45 for transmitting the (time timing superimposed signal) to the embedded network information processing device 8E2 incorporated in the other control monitoring device 3E2 in the same control station Ca is provided.

The embedded network information processing device 8E2 incorporated in the other control monitoring device 3E2 does not have the above-described precise time receiving unit and antenna, and
Each functional block configuration of the embedded network information processing apparatus 8 shown in FIG.
In addition, only the time timing signal and the time data are combined from the time timing superimposed signal transmitted from the embedded network information processing device 8E1 to the second
Time decoding unit 46 to be supplied to the arithmetic processing unit 12
The time-timing superimposing unit 45 and the time-timing decoding unit 26 are connected by a communication line such as an optical fiber.

FIG. 12 is a diagram for explaining the operation of the time and timing superimposing unit 45 and the time and timing decoding unit 46.
The time data in the time-timing superimposing section 45, the time-timing signal, the time-timing superimposed signal transmitted from the time-timing superimposing section 45 to the time-timing decoding section 46 and the time-timing superimposed signal received by the time-timing decoding section 46 are decoded. FIG. 3 is a waveform diagram (time chart) showing time data and a time timing signal, respectively. The time data is serial data of an appropriate transfer speed, and the time corresponding to one byte of the serial data is td.

That is, according to the present embodiment, as shown in FIG. 12, the time-timing superimposing section 45 superimposes the time-timing signal on the time signal serial signal for a time-timing time Tt sufficiently longer than td. The time timing decoding unit 46 checks the superimposed signal for a decoding detection time Tr that satisfies td <Tr <Tt, and detects the time timing signal when it is "true" or more than Tr.

That is, according to the present embodiment, for example, the embedded network information processing apparatus installed in a plurality of control monitoring apparatuses relatively close to each other, such as a control monitoring apparatus installed in the same control station. The precision time receiving means (precision time receiving antenna, precision time reception) is superimposed on the precision time (time data, time timing signal) measured by at least one precision time receiving means (precision time receiving antenna, precision time receiving unit). Section) is transmitted to another embedded network information processing apparatus that is not mounted thereon, whereby the other embedded network information processing apparatus decodes the transmitted superimposed signal and acquires the precise time. The state quantity data collection processing can be performed using the precise time.

Therefore, the number of precision time receiving means (precision time receiving antenna, precision time receiving unit) mounted on a plurality of embedded network information processing apparatuses can be reduced, and the cost of the control and monitoring system can be reduced. be able to.

(Seventh Embodiment) FIG. 13 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating an embedded network information processing apparatus according to a seventh embodiment of the present invention. It is. In FIG. 13, the same components as those of the functional block configuration of the control monitoring system 1D and the embedded network information processing device 8D shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 13, the embedded network information processing apparatus 8F includes, as hardware shared resources that can be accessed by the first and second arithmetic processing units 11 and 12, respectively, the sampling network connected to the shared bus BC. The signal generator 45 is provided. This sampling signal generator 4
5 generates and generates a sampling signal at a finer interval than the time timing signal (usually every one second) of the precise time receiving unit 40 based on the time timing signal at the precise time measured by the precise time receiving unit 40. The obtained sampling signal is transmitted to the second arithmetic processing unit 12. As a result, the second arithmetic processing unit 12 collects state quantity data according to the transmitted sampling signal.

The details of the sampling signal generator 45 will be described below.

The sampling signal generating section 45 generates a signal (clock signal) having a very stable frequency by a quartz oscillator.
And a clock timing signal of the precise time received by the precise time receiving unit 40,
A change point detection section 45b for detecting a change point (rising point or falling point) of the time timing signal, and a signal oscillated and output from the crystal oscillator 45a is frequency-divided, and the second arithmetic processing section 12 is used as a sampling signal. And a frequency dividing counter 45c for outputting the data to the counter.

That is, the period of the time timing signal is set to H
t, the period of the sampling signal finally output from the frequency division counter 45c to the second arithmetic processing unit 12 is s · Ht
(S is an integer), N is an appropriate large integer, and the crystal oscillator 45
It is assumed that the oscillation frequency of “a” is N · s · Ht, and the number of divisions of the division counter 45c is N.

At this time, the frequency dividing counter 45c divides the frequency of the clock signal of frequency N · s · Ht output from the crystal oscillator 45a by N, so that the output of the frequency dividing counter 45c becomes a signal of frequency s · Ht. The signal of this frequency s · Ht is used as a sampling signal.

The frequency division counter 45c receives the change point signal supplied from the time timing change point detection section 45b as a clear signal, and clears the counter at each time timing. Thus, the sampling signal output from the frequency division counter 45c is synchronized with the time timing signal.

According to this configuration, for example, the sampling of the state quantity data, which has been conventionally performed at a period of about one second (Ht = 1 s), is performed at a high-speed period s times the one-second period and at the time of the precise time. It can be performed in synchronization with the timing.

Therefore, for example, the period (frequency) of the time timing signal of the precise time measured by the precise time receiving means 40 of the embedded network information processing device 8F is determined by the state quantity data acquisition (sampling) of the control monitoring unit 7.
Even when the period is lower than the timing period (frequency), the sampling signal generation unit 45 sets the period of the sampling signal to be higher than the period of the time timing signal of the precise time, so that the collection of state quantity data synchronized with the precise time can be performed. This can be performed in accordance with the state quantity data sampling cycle of the control monitoring unit 7.

(Eighth Embodiment) FIG.
In FIG. 14, the same components as those of the functional block configuration of the control monitoring system 1F and the embedded network information processing device 8F shown in FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted.

According to FIG. 14, the control monitoring unit 7A of the control monitoring device 3F transfers the state quantity data to the embedded network information processing device 8G in synchronization with the sampling signal transmitted from the sampling signal generating unit 45. The embedded network information processing device 8G includes a data transfer unit 50, and the first and second arithmetic processing units 11 and 1
2 includes an automatic state quantity storage unit 51 connected to the shared bus BC as a hardware shared resource that can be accessed. The data transfer unit 50 of the control monitoring unit 7A is connected to the automatic state quantity storage unit 51 via a signal line L separate from the shared bus BC so that data can be transmitted and received.

The automatic state quantity storage section 51 has a data storage (storage) area having a smaller data storage capacity than the storage capacity of the second storage section R2, and is transmitted from the control monitoring unit 7A. The state quantity data can be automatically stored in the data storage area.

According to the present embodiment, the control monitoring unit 7
The state quantity acquired from the control monitoring target 2 by A is output to the embedded network information processing apparatus 8G by the data transfer section 50 in synchronization with the sampling signal from the sampling signal generating section 45 as state quantity data. You.
At this time, the state quantity data is output to the automatic state quantity storage unit 51 via the signal line L instead of the shared bus BC.

The automatic state quantity storage section 51 automatically takes in the state quantity data output via the signal line L in synchronization with the sampling signal from the sampling signal generation section 45 and stores the data in the data storage area. To memorize. As a result,
The second arithmetic processing unit 12 reads the state quantity data from the automatic state quantity storage unit 51 at appropriate intervals according to the storage capacity of the data storage area of the automatic state quantity storage unit 51 and collects the state quantity data. It has become.

That is, in this embodiment, acquisition and collection of state quantity data from the control monitoring target 2 via the control monitoring unit 7 is performed at a high frequency, and the state quantity data is a large amount of data. Also, without passing through the shared bus BC, the embedded network information collecting device 8G
Can be stored in the data storage area of the automatic state quantity storage unit 51.

Therefore, even if the high-frequency and large amount of state data is collected, the high-frequency and large amount of state data does not occupy the shared bus BC.
The processing of the arithmetic processing unit 11 and the second arithmetic processing unit 12 can be performed smoothly irrespective of the high frequency and large amount of state data collection, and the state data collection processing of the embedded network information processing apparatus 8G can be performed. Can be efficiently performed.

Further, since the automatic state quantity storage unit 51 is provided for storing the state quantity data, the rate at which the state quantity data is stored in the storage area of the data storage unit R2 of the second arithmetic processing unit 12 is reduced. The storage capacity of the storage unit R2 can be saved.

(Ninth Embodiment) FIG. 15 is a diagram showing a schematic configuration of a control monitoring system including a control monitoring device incorporating a built-in network information processing device according to a ninth embodiment of the present invention. It is. In FIG. 15, the same components as those of the functional block configuration of the control monitoring system 1 and the embedded network information processing device 8 shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

According to FIG. 15, the embedded network information processing device 8H includes a display connected to the shared bus BC as a hardware shared resource that can be accessed by the first and second arithmetic processing units 11 and 12, respectively. An apparatus 55 is provided.

In the present embodiment, in normal times, the first arithmetic processing section 11 exclusively uses the display device 55, and displays a predetermined display on the display device 55 based on the display program included in the program module. Processing is performed.

At this time, similarly to the fourth embodiment, when the second arithmetic processing unit 12 fails, the first arithmetic processing unit 11
Detects the failure and displays a predetermined form indicating the failure of the second arithmetic processing unit 12 via the display device 55 based on the display program.

If the first arithmetic processing unit 11 that exclusively performs the display processing via the display device 55 breaks down, the first arithmetic processing unit 11 releases the exclusive use of the display device 55. I do. As a result, the second arithmetic processing unit 12
Detects a failure in the first arithmetic processing unit 11 and detects an abnormality (first arithmetic processing unit 11) stored in advance in the second storage unit R2.
The display device 55 displays a predetermined form indicating the failure of the first arithmetic processing unit 11 on the display device 55 based on the display program at the time of failure.

That is, according to the present embodiment, even if a failure occurs in one of the arithmetic processing units, the occurrence of a failure in the corresponding arithmetic processing unit can be displayed by the other arithmetic processing unit. As a result, an operator who visually recognizes the display device can take appropriate and prompt measures based on the occurrence of the failure.

The above-described fourth embodiment (see FIG. 4)
The first program data storage unit 31 and the second program data storage unit 32 in the above may be configured to be attachable / detachable to / from a mounting unit (not shown) of the embedded network information processing apparatus 8A. Then, a storage medium (memory device) of an appropriate type and capacity can be used as each of the program / data storage units 31 and 32.

When various storage capacities and types of storage media are used as in this modification, the first arithmetic processing unit 1
The first and second arithmetic processing units 12 must automatically determine the type and capacity of the storage medium actually used.

Therefore, in this modification, the type and the type of storage medium used as the program / data storage units 31 and 32 by the first and second arithmetic processing units 11 and 12 are described.
We propose a method for automatically determining the capacity and a method for more easily realizing automatic attachment and detachment of storage media.

Hereinafter, the process of automatically determining the type and capacity of the storage medium will be described. Note that, as types of usable storage media, ROM, static RAM (SRA
M), dynamic RAM (DRAM), and the usable capacity (size) of each is large capacity, medium capacity,
Small capacity. Further, for ease of explanation, a process in which the first arithmetic processing unit 11 automatically determines the type and capacity of the storage medium used as the first program / data storage unit 31 will be described.

FIG. 16 is a flowchart showing the outline of the automatic discrimination processing of the type and capacity of the storage medium of the first arithmetic processing section 11.

According to FIG. 16, the first arithmetic processing unit 11
Initializes the storage medium mounted as the first program / data storage unit 31 as a large-capacity SRAM (step S1). Next, the first arithmetic processing unit 11
Performs a process of writing data D1 to the first address A1 of the memory area of the storage medium (step S2).
Note that, for example, when the storage medium is a ROM, the address A1 is an area in which valid data is stored, and the write data D1 is a value other than the corresponding ROM data and the default value of the bus.

Subsequently, the first arithmetic processing unit 11 reads the data at the address A1, and stores the read data in X
(Step S3). The processing of steps S2 to S3 is repeated one or more predetermined times (for example, two times).

The first arithmetic processing unit 11 determines that the data X read out in the process of step S3 is twice the data D
It is determined whether or not they match 1 (step S4), and 2
If they match each other (step S4 → YES; Y is simplified in the figure), the first arithmetic processing unit 11 determines that the storage medium is an SRAM, and determines the size (capacity) of the SRAM. (S5; see FIG. 17) and the subroutine processing is performed.

That is, as shown in FIG. 17, the first arithmetic processing unit 11 sets the storage medium (SRAM) to have a large capacity and initializes the memory access circuit of the first arithmetic processing unit 11 ( Step S5a) Then, the arbitrary data D is stored in the maximum address A2 of the storage area which is assumed to have a large capacity.
2 is written (step S5b). Then, the first arithmetic processing unit 11 writes arbitrary data D3 to the medium capacity maximum address A3 (step S5c), reads data at the address A2, and sets the read data to X (step S5d).

Then, the first arithmetic processing unit 11 determines whether or not the data X read in the processing of step S5d matches the data D2 (step S5e), and if they match (step S5e → YES), storage medium SRA
It is determined that the capacity of M is large (step S5f), the process returns to the main process (FIG. 16), and proceeds to the process of step S14 described later.

On the other hand, in the process of step S5e, if the data D2 subjected to the writing process does not match the data X (step S5e → NO), the storage medium (S5e)
RAM) is set to a medium capacity, and the memory access circuit of the first arithmetic processing unit 11 is initialized (step S5).
g) Then, write any data D3 to the maximum address A3 of the storage area assumed to be medium capacity (step S5)
h). Then, the first arithmetic processing unit 11 writes arbitrary data D4 to the small-capacity maximum address A4 (step S5i), reads data at the address A3, and sets the read data to X (step S5j).

Then, the first arithmetic processing unit 11 determines whether or not the data X read in the processing of step S5j matches the data D3 (step S5k). If the data X matches (step S5k → YES), storage medium SRA
It is determined that the capacity of M is the medium capacity (step S51), the process returns to the main process (FIG. 16), and the process proceeds to step S14 described later.

On the other hand, in the process of step S5j, if the data D3 subjected to the write process does not match the data X (step S5j → NO), the storage medium (S5j
RAM) is set to a small capacity, and the memory access circuit of the first arithmetic processing unit 11 is initialized (step S5).
m), the capacity of the storage medium SRAM is determined to be small (step S5n), the process returns to the main process (FIG. 16), and proceeds to the process of step S14 described later.

In the process of step S3, if the written data D1 and the data X do not match at least once (step S4 → N
O; simplified in the figure as N), the first arithmetic processing unit 1
1 judges whether the read data X has the same value (the default value of the bus, etc.) both times (step S).
6).

If it is determined in step S6 that the read data X has the same value (the default value of the bus, etc.) both times (step S6 → YES), the first arithmetic processing unit 11 sets the storage medium in the ROM. And determines the size (capacity) of the ROM (S7; see FIG. 18).
Then, the subroutine process is performed.

That is, as shown in FIG. 18, the first arithmetic processing section 11 sets the storage medium (ROM) to have a large capacity and initializes the memory access circuit of the first arithmetic processing section 11 ( Step S7a), and then read the data at the maximum address A2 of the storage area assumed to have a large capacity,
This read data is set to Y (step S7b). Then, the first arithmetic processing unit 11 outputs the maximum address A of the medium capacity.
3 is read, and the read data is set as X (step S7c).

Then, the first arithmetic processing unit 11 determines whether or not the data X and Y read in the processing of steps S7b and S7c do not match, and whether the data Y and the default value do not match (step S7d). ), Data X,
If Y does not match and data Y does not match the default value (step S7d → YES), the storage medium ROM
Is determined to be a large capacity (step S7e), the process returns to the main process (FIG. 16), and shifts to the process of step S14 described later.

On the other hand, in the process of step S7d, when it is determined that the data X and Y match or the data Y and the default value match (step S7).
7d → NO), the first arithmetic processing unit 11 stores the storage medium (R
OM) as the medium capacity and the first arithmetic processing unit 11
Of the memory access circuit at step S7 (step S7).
f) Then, the data at the maximum address A3 of the storage area assumed to have a medium capacity is read, and the read data is set to Y (step S7g). Then, the first arithmetic processing unit 11
Reads the data of the small-capacity maximum address A4, and sets the read data as X (step S7h).

Then, the first arithmetic processing section 11 determines whether or not the data X and Y read in the processing of steps S7g and S7h do not match, and whether the data Y and the default value do not match (step S7i). ), Data X,
If Y does not match and data Y does not match the default value (step S7i → YES), the storage medium ROM
Is determined to be a medium capacity (step S7j), the process returns to the main process (FIG. 16), and the process proceeds to step S14 described later.

If the first arithmetic processing unit 11 determines that the data X and Y match or the data Y and the default value match (step S7).
i → NO), the storage medium (ROM) is set as a small capacity, the memory access circuit of the first arithmetic processing unit 11 is initialized (step S7k), and the capacity of the storage medium ROM is determined to be a small capacity. (Step S71) Returning to the main processing (FIG. 16), the processing shifts to the processing of step S14 described later.

In the process of step S6, if the data D1 and the data X for which the writing process has been performed are not the same value such as the default value of the bus both times (step S6 → NO), the first arithmetic processing is performed. The unit 11 initializes the storage medium as a DRAM having a large capacity (step S
8) Then, a process of writing data D1 to address A1 in the memory area of the storage medium is performed (step S9).

Next, the first arithmetic processing unit 11 reads out the data at the address A1, and
(Step S10).

Then, the first arithmetic processing section 11 determines whether or not the data X read in the processing of step S10 matches the data D1 (step S11). YES), the first arithmetic processing unit 11 determines that the storage medium is a DRAM, and
Size (capacity) determination subroutine processing (S12; FIG. 1)
9).

The DRAM size determination subroutine shown in FIG. 19 (steps S19a to S19)
Each process of n) is equivalent to the process in which the target storage medium is replaced with the DRAM in the SRAM size determination subroutine processing steps S5a to S5n shown in FIG. 17, and the description thereof is omitted.

On the other hand, if the result of determination in step S11 is that they do not match (step S11 → NO), the first arithmetic processing unit 11 sets the embedded network information processing apparatus 8A
It is determined that no storage medium is mounted as the first storage unit R1 (step S13).

Thus, the first arithmetic processing unit 11
After automatically determining the type and capacity of the storage medium used and mounted as the first program / data storage unit 31, the first arithmetic processing unit 11 sets the first program / data storage unit 31 (memory ) Is reported (step S14), and the process ends.

Hereinafter, the first arithmetic processing section 11 accesses the first program / data storage section 31 constituted by a storage medium of the determined type and capacity.

As described above, according to this modification, a storage medium suitable for the characteristics of the control / monitoring device in which the embedded network information processing device is incorporated, and the type and amount of state quantity data to be collected. And can be removably mounted as storage means for the first and second arithmetic processing units. Further, the type and capacity of the mounted storage medium can be automatically determined.

Therefore, it is possible to provide an embedded network information processing apparatus equipped with a storage means (storage medium) which is optimal for any of the three points of performance, price and scale.

The seventh embodiment described above (see FIG. 7)
May be configured to be writable and detachable. With such a configuration, in a state where the nonvolatile boot program storage unit 35 is attached to the embedded network information processing apparatus, the nonvolatile boot program storage unit 3 is used by using an appropriate writing program.
It is possible to erase, write, change, etc. the storage contents (storage program) of No. 5.

According to the present modification, by further preparing an appropriate writing device, the nonvolatile boot program storage unit 35 can be stored in a state in which the nonvolatile boot program storage unit 35 is detached from the embedded network information processing apparatus. It is possible to erase, write, change, etc. the stored contents.

That is, in the present modification, the management and updating of the boot program stored in the nonvolatile boot program storage section 35 can be facilitated, and the maintainability of the boot program can be improved.

[0185]

As described above, according to the present invention, it is necessary to repeatedly execute a program / data transmission / reception process with an external device and a program command interpretation process which require a relatively long processing time in real time. A process of collecting state quantity data from a control monitoring object can be compatible.

Therefore, the present invention can be incorporated in each control and monitoring device constituting a control and monitoring system which needs to collect a large amount of state quantity data at all times, such as a power system monitoring system. The applicability of the device can be improved.

Further, according to the present invention, the processing of each processing means having the highest frequency is accelerated, and the scale of the hardware is reduced.
It is possible to minimize the capacity of storage means (semiconductor memory or the like) that greatly affects the price, and to reduce the size of the embedded network information processing apparatus.

Further, according to the present invention, highly accurate and accurate time can be obtained at a relatively low cost and given to the embedded network information processing apparatus. Time synchronization can be realized between them. That is, the control and monitoring processing that conventionally required a dense synchronization mechanism such as the phase comparison of the state quantity data can be easily realized by the embedded network information processing apparatus using the general-purpose network.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a first embodiment of the present invention is incorporated.

FIG. 2 is a circuit block diagram showing an internal configuration of an arbitration processing unit in FIG. 1 in the form of hard-wired logic.

FIG. 3 is a diagram showing a truth table for representing arbitration logic operation of the arbitration logic circuit shown in FIG. 2;

FIG. 4 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a second embodiment of the present invention is incorporated.

FIG. 5 is a circuit block diagram showing an internal configuration of an arbitration processing unit shown in FIG. 4 in the form of hard-wired logic.

FIG. 6 is a diagram showing a truth table for representing the arbitration logic operation of the arbitration logic circuit shown in FIG. 5;

FIG. 7 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a third embodiment of the present invention is incorporated.

FIG. 8 is a time chart illustrating timings of start signals of first and second arithmetic processing units and operation timings of first and second arithmetic processing units according to the third embodiment.

FIG. 9 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a fourth embodiment of the present invention is incorporated.

FIG. 10 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a fifth embodiment of the present invention is incorporated.

FIG. 11 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a sixth embodiment of the present invention is incorporated.

FIG. 12 is a diagram illustrating a time data, a time timing signal, a time timing superimposition signal transmitted from the time timing superimposition unit to the time timing decoding unit, and a time received by the time timing decoding unit according to the sixth embodiment. FIG. 4 is a waveform diagram (time chart) showing a timing superimposition signal, decoded time data, and a time timing signal, respectively.

FIG. 13 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a seventh embodiment of the present invention is incorporated.

FIG. 14 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to an eighth embodiment of the present invention is incorporated.

FIG. 15 is a block diagram showing a schematic configuration of a control monitoring system including a control monitoring device in which an embedded network information processing device according to a ninth embodiment of the present invention is incorporated.

FIG. 16 is a flowchart showing an outline of a process for automatically determining the type and capacity of a storage medium according to a modification of the present invention.

FIG. 17 is a flowchart showing an outline of the SRAM size (capacity) determination subroutine processing in FIG. 16;

FIG. 18 is a flowchart showing an outline of a ROM size (capacity) determination subroutine process in FIG. 16;

19 is a flowchart showing an outline of a DRAM size (capacity) determination subroutine process in FIG. 16;

[Explanation of symbols]

1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H
Control monitoring system 2 Control monitoring target 3, 3E1, 3E2 Control monitoring device 4 Display / operation device 5 Communication network 7 Control monitoring unit 8, 8A, 8B, 8C, 8D, 8E1, 8E2, 8F,
8G, 8H Embedded network information processing device 10 Communication interface unit 11 First arithmetic processing unit 12 Second arithmetic processing unit 15 General-purpose clock unit 16 General input / output unit 17 Shared resource unit 18, 18A Arbitration processing unit 20 Clock output Unit 21, 22 Latch 23, 24 Gate buffer 25, 25A Arbitration logic circuit 26 Start signal generation unit 31 First program / data storage unit 32 Second program / data storage unit 35 Non-volatile start program storage unit 36 Start signal generation unit 37, 38 discriminating unit 40 precision time receiving unit 41 antenna 45 time timing superimposing unit 45a crystal oscillator 45b change point detecting unit 45c frequency dividing counter 50 data transfer unit 51 automatic state quantity storage unit 55 display device B1, B2 bus BC shared bus RC Shared data storage area REQ1 First operation processing REQ2 Access request signal to general-purpose clock unit or general input / output unit REQ2 Access request signal from second operation processing unit to general-purpose clock unit or general input / output unit REQC Shared data storage area access request from first operation processing unit Signal DRQ1 One clock delay signal of REQ1 DRQ2 One clock delay signal of REQ2 ACK1 Access response signal to first processing unit ACK2 Access response signal to second processing unit MACC Access signal to shared data storage area BREQ No. Storage area delivery request signal to the second processing unit BGNT Storage area delivery response signal returned from the second processing unit END1 Processing completion signal to the first processing unit END2 Processing to the second processing unit Completion signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 12/28 G05B 15/02 M H04Q 9/00 301 H04L 11/00 310Z

Claims (15)

[Claims] An embedded network that is incorporated in an apparatus that controls and monitors a control monitoring target based on state data representing a state quantity of the control monitoring target and that can collect external information through a general-purpose network. In the information processing apparatus, an interface unit connected to the general-purpose network and performing an interface process between the general-purpose network and the embedded network information processing apparatus, and the external general-purpose network and the interface unit via the interface unit First processing means for performing processing for transmitting and receiving a program and data, and processing for interpreting and executing a program subjected to reception processing; second processing means for performing processing for collecting state data relating to the control monitoring target; Hardware commonly accessible from the first and second processing means, respectively A shared resource, a shared operation processing unit for performing a predetermined operation process, and two independent accesses to the shared operation processing unit of the first processing unit and the second processing unit. And an access adjusting means for adjusting according to the timing of the embedded network information processing apparatus. 2. The sharing operation processing unit includes: a time measuring unit that measures an actual time; and an input / output unit for inputting and outputting data to and from the embedded network information processing device other than via the general-purpose network. The time measuring unit and the input / output unit are connected to a shared bus shared by the first processing unit and the second processing unit, respectively. A function of interpreting a program transmitted via the interface means, a function of receiving state quantity data required based on the interpretation from the second processing means, and processing the processing result, and transmitting the processing result to the interface Means for transmitting to the general-purpose network via the means, and the second processing means includes a state quantity data of the control / monitoring target. A function of sequentially collecting data, a function of accessing the time measuring unit via the access adjusting means, acquiring a time measured by the time measuring means, adding the time to the collected state quantity data, and storing the acquired time. A function of reading out the state quantity data corresponding to the request from the stored state quantity data with time in response to the request of the first processing means and transferring the data to the first processing means. 2. The embedded network information processing apparatus according to claim 1, wherein: 3. The first processing unit is connected to a shared bus of the shared operation processing unit by a first bus, and the shared operation is performed to the access adjusting unit via the first bus. A first access request signal for requesting access to a processing unit is transmitted, and the second processing unit is connected to a shared bus of the shared operation processing unit by a second bus. And transmitting a second access request signal for requesting access to the shared operation processing unit to the access adjustment unit via the second bus, wherein the access adjustment unit A first and a second gate unit for opening and closing the first bus, the second bus, and the shared bus, respectively; and a first access signal and a second access signal, respectively. Performing a logical operation using a delay circuit that delays by one clock to generate first and second delay signals, and the first and second access signals and the first and second delay signals; 3. The embedded network information processing device according to claim 2, further comprising: a logical operation circuit that controls opening and closing of the first and second gate units according to the result of the logical operation. 4. The first buffer connected to the first buffer.
A first program / data storage unit for storing the program and data processed by the processing unit, and a program and data connected to the second buffer and processed by the second processing unit And a second program / data storage means for performing the first processing unit and the second processing in at least one storage area of the first and second program / data storage means. A shared data storage area accessible by each unit is set, and the first processing unit and the second processing unit are processed by another processing unit by accessing the shared data storage area. While the program and the data are taken out, the access adjusting means is provided for the shared data storage area of the first processing unit and the second processing unit. 4. The embedded network information processing apparatus according to claim 3, further comprising a function of adjusting two independent accesses according to the timing of the accesses. 5. A boot program storage unit that is common to the first and second processing units and stores a boot program common to the first and second processing units.
And a start signal supply means for supplying a start signal to the second processing means with a time difference, and the first processing means and the second processing means are provided with the start signal supply means. Are activated with a time difference from each other in response to a start signal supplied with a time difference, and the initialization process is performed by executing the common start programs stored in the start program storage means with a time difference from each other. The embedded network information processing apparatus according to any one of claims 1 to 4, wherein: 6. The interface means has shared interface means connected to the shared bus as hardware shared resources which can be commonly accessed from the first and second processing means, respectively. Is configured to notify the occurrence of an abnormality in the second processing unit to the outside via the shared interface unit and the general-purpose network when an abnormality occurs in the second processing unit, The second processing means is configured to, when an abnormality occurs in the first processing means, notify the occurrence of the abnormality in the first processing means to the outside via the shared interface means and the general-purpose network. The embedded network information processing apparatus according to any one of claims 1 to 4, wherein: 7. An apparatus according to claim 1, further comprising: a precise time acquiring means for acquiring a precise time, wherein said second processing means stores the precise time acquired by said precise time acquiring means in addition to the collected state quantity data. The embedded network information processing apparatus according to any one of claims 1 to 4, wherein: 8. The second processing means is adapted to calibrate the time measured by the time measuring unit in accordance with the precise time obtained by the precise time obtaining means, and 8. The time data adding process for the state quantity data is performed using the time measured and calibrated by the time measuring unit when the precise time acquired in step (a) cannot be used. Embedded network information processing device. 9. The control and monitoring apparatus according to claim 7, wherein said embedded network information processing apparatus is incorporated in each of said plurality of control and monitoring apparatuses to form a control and monitoring system. At least one information processing device in the embedded network information processing device is connected to another information processing device by a communication line different from the general-purpose network, and the other information processing device is connected to the precise time acquisition unit. Means for superimposing a signal representing each time timing constituting the precise time obtained by the above and time data representing the time of each time timing and transmitting the signal to the at least one information processing device via the communication line. Wherein the precise time obtaining means of the at least one information processing device transmits the precise time from the other information processing means via the communication line. Control monitoring system, characterized in that the means for obtaining a signal representative of the respective time timing decodes the superimposed signal has been, the precise time separated into the time data representing the time of each time timing. 10. A sampling signal generating means for generating a data sampling signal synchronized with a time timing such as the precise time and transmitting the data sampling signal to the second processing unit, wherein the second processing unit The embedded network information processing apparatus according to any one of claims 1 to 4, wherein a collection process of the state quantity data is performed in synchronization with a sampling signal. 11. A data sampling signal generating means for generating a data sampling signal synchronized with time timing such as the precise time and transmitting the data sampling signal to the control monitoring device, wherein the control monitoring device is collected from the control monitoring target. The shared state data is output to the embedded network information processing device via the shared bus in synchronization with the transmitted data sampling signal, and is connected to the shared bus. 11. The embedded network information processing apparatus according to claim 10, further comprising an automatic storage unit for automatically storing state quantity data output in synchronization with the data sampling signal via a bus. 12. A display unit capable of displaying the state quantity data and the like as hardware shared resources commonly accessible from the first and second processing units, wherein the first processing unit includes When an abnormality has occurred in the second processing means, the occurrence of the abnormality in the second processing means is displayed via the display means, and the second processing means is provided with the first processing means. 5. The apparatus according to claim 1, wherein when an abnormality occurs, the occurrence of an abnormality in the first processing unit is displayed via the display unit. 6.
13. The embedded network information processing apparatus according to claim 1. 13. The embedded network information processing apparatus according to claim 4, wherein said first program data storage means and said second program data storage means are constituted by removable storage media. . 14. The embedded network information as the detachable first program data storage means and the second program data storage means, wherein the first processing section and the second processing section are detachable. An automatic discriminating means for automatically discriminating the type and capacity of the storage medium mounted on the processing device is provided. The automatic discrimination means writes data to a predetermined address of a storage area of the storage medium, 14. The method according to claim 13, wherein data is read from a predetermined address, the write data is compared with the read data, and the type and capacity of the storage medium are automatically determined according to the comparison result. Embedded network information processing device. 15. The embedded network information processing apparatus according to claim 5, wherein said boot program storage means is constituted by a writable and removable storage medium.