JP2000163108A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken a time required for transmitting interruption request and release from an I/O unit through an interrupting signal line to a CPU unit. SOLUTION: Interrupting signals from plural I/O units 4 on a basic base 1 and extension bases 2 are transmitted through one interrupting signal line which is made common among system buses to a CPU unit 3 on the basic base 1 in this PC. In this case, the basic base 1 is provided with an AND gate 6a for electrically dividing the interrupting signals from the I/O units 4 on the basic base 1 and the interrupting signals from extension connector sides for connecting the extension bases, and for applying any signal to the CPU unit 3, and the extension base 2 is provided with an AND gate 8a for electrically dividing the interrupting signals from the I/O units 4 on its own extension base and the interrupting signals from the extension connector side for connecting the other extension base, and applying any signal to the extension connector at the CPU unit side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller and, more particularly, to an interrupt request / release from a plurality of I / O units mounted on a basic base or an extension base to a CPU unit mounted on the basic base. The present invention relates to a programmable controller that performs an interrupt process for performing

[0002]

2. Description of the Related Art FIG.
1 shows a configuration example of a controller (hereinafter abbreviated as PC). This PC has one basic base 1 for electrically connecting the units and a plurality of (two for convenience) extension bases 2.

A basic base 1 is equipped with a CPU unit 3 for controlling the entire PC system. The CPU unit 3 includes a microprocessor 3a and a memory 3b storing a program to be executed by the microprocessor 3a.
And a system bus control circuit 3c for controlling the I / O unit 4, and an interrupt input circuit 3d.

A power supply unit 11 and a plurality of I / O units 4 for exchanging data with an external input / output device (not shown) are mounted on the basic base 1 and the extension base 2, respectively. The I / O unit 4 includes an interrupt request circuit 4a and an open collector output inverter gate 4.
b, and an interrupt signal state notification circuit 4c for the CPU unit 3 to determine the presence or absence of an interrupt request.

The basic base 1 is provided with a system bus 5. The system bus 5 is provided with an interrupt signal line 5 a for transmitting an interrupt request / release to the CPU unit 3.
And a signal line group 5e other than the interrupt signal line. A pull-up resistor 5f is connected to the interrupt signal line 5a.
This pull-up resistor 5f is necessary for realizing wired OR connection by an open collector, and is mounted so that an interrupt signal does not malfunction when no I / O unit is mounted on the basic base. Is what you are doing. The extension base 2 is also provided with a system bus 7. The system bus 7 includes an interrupt signal line 7 a for transmitting an interrupt request / release to the CPU unit 3 and a signal line group 7 e other than the interrupt signal line. Contains.

An extension connector 10 is provided on each of the basic base 1 and the extension base 2, and a system bus 5 including an interrupt signal line 5a is connected to each extension connector 10. Extension connector 10 of basic base 1 and extension base 2 and extension connector 10 of extension base 2
Is connected to an extension cable 9, and the extension cable 9 is directly connected to the system buses 5 and 7 of each base.

In the PC, many input / output lines are connected to each device via the I / O unit 4 of the PC in order to control a plurality of devices in a factory or the like. If the number of I / O lines is not enough with only the number of I / O units, a plurality of extension cables 9 are connected to extension connectors 10 on the basic base 1 and the extension base 2 as shown in the figure. 1 and the system buses 7 on the plurality of extension bases 2 are electrically the same system bus, so that the basic base 1
CPU unit 3 can control the I / O unit 4 on the extension base 2, thereby increasing the number of input / output lines. In addition, when controlling a device located at a place distant from the basic base 1, the extension base 2 is connected to the basic base 1 via an extension cable 9 to extend the distance.

[0008] Since a plurality of I / O units are connected to the PC, if an interrupt signal is individually input to the CPU unit 3 by one interrupt signal line for each I / O unit, an interrupt input The number of signal lines increases,
Since there are many disadvantages in terms of cost and space such as an increase in the number of system buses, the number of pins of the extension connector, and the number of cores in the extension cable, the interrupt signal lines 5a and 7a are provided with a plurality of I / Os.
Units share one interrupt signal line.

For convenience, before the CPU unit 3 activates the interrupt processing program, the CPU unit 3 positions the extension bases (1), (2) to (j) in order from the extension base close to the basic base. And the presence or absence of the I / O unit 4 and the mounting position of each I / O unit 4 for each base, and the I / O units (1),
It is assumed that they are positioned as I / O unit (2) to I / O unit (i).

Since the interrupt signal lines 5a from the plurality of I / O units 4 are shared by one and the interrupt signal is input to the system bus control unit 3c in the CPU unit 3, each of the I / O units 4 A wired OR connection is implemented by mounting an inverter gate 4b having an open collector output, and an interrupt signal line 5a is connected to an interrupt input circuit 3d in the CPU unit 3 so that the interrupt signal outputs do not collide electrically. , An interrupt request to the microprocessor 3a.

[0011] Therefore, the CPU unit 3 is
Alternatively, means is required to determine which of the plurality of I / O units 4 attached to the extension base 2 has issued the interrupt request. When the microprocessor 3a receives the interrupt request via the interrupt input circuit 3d in the CPU unit 3 when the interrupt signal state notification circuit 4c is mounted,
Activate the interrupt processing program stored in the memory 3b.

FIGS. 5 and 6 show the processing flow of the interrupt processing program. First, the unit number i is set to 1 (step S101), and the interrupt signal state notification circuit 4c in the I / O unit (i) mounted on the basic base 1 is controlled by the signal line group 5e other than the interrupt signal line. An access is made (S102), and information for determining the presence or absence of an interrupt request from the I / O unit (i) is obtained. Based on the information, the presence or absence of an interrupt request from the I / O unit (i) is determined (step S103), and a corresponding interrupt process is performed on the I / O unit having the interrupt request (S103).
104).

Hereinafter, the I / O mounted on the basic base 1
The process is repeated for the number of O units 4 (step S105, step S106, steps S102 to S105).

When processing for the number of I / O units 4 mounted on the basic base 1 is completed, it is determined whether or not the extension base 2 is mounted (step S107), and the extension base 2 is mounted. If so, the extension base number j and the unit number i are set to 1 (step S10).
8, step S109), the interrupt signal state notification circuit 4c in the I / O unit (i) mounted on the extension base (j) is accessed by the signal line group 7e other than the interrupt signal line (S110), and the I Information for determining the presence / absence of an interrupt request from the / O unit (i) is obtained. The presence or absence of an interrupt request from the I / O unit (i) is determined based on the information (step S111), and a corresponding interrupt process is performed on the I / O unit having the interrupt request (S111).
112) After that, the I / O attached to the extension base (j)
The process is repeated for the number of O units 4 (step S113, step S114, steps S109 to S113).

When the processing of one extension base (j) is completed, it is checked whether or not the extension base (j + 1) exists (step S115). If the extension base (j + 1) is mounted, the extension base (j + 1) is installed. ) Of the I / O unit 4 (step S116, step S109)
-Step S115).

As described above, in the conventional interrupt processing program, all of the I / O units 4
The interrupt signal status notifying circuit 4c is accessed via the signal line groups 5e and 7e other than the interrupt signal line and the extension cable 9 to determine from which I / O unit the interrupt request is issued. A method of executing a corresponding interrupt processing program for the / O unit has been adopted.

[0017]

In the above-described conventional connection method of the interrupt signal, the total extension of the system bus becomes longer as the extension base, the extension cable and the I / O unit are increased. The total length of the interrupt signal lines in the bus also increases, the inductance and capacitance of the interrupt signal lines increase, and interrupt requests from all I / O units mounted on the PC to the CPU unit
The propagation delay time for release was uniformly increased.

In particular, the extension cable is several tens cm to several meters.
Or because it has a length of several tens of meters, and also has a length of several tens of cm in the interrupt signal line on the extension base,
This greatly affected the propagation delay of the interrupt signal.

In order to share one interrupt signal line, an open-collector output inverter gate is used as an interrupt signal output of each I / O unit. When the / O unit releases the interrupt request, the shared interrupt signal is driven to a high level by the pull-up resistor.
As the wiring length of the interrupt signal line is longer, the transition time from the low level to the high level becomes longer due to inductance and capacitance.

In general, even if several tens of I / O units are mounted, the probability of simultaneous occurrence of interrupt requests is low, and even if they occur simultaneously, the number of interrupt requests is at most several. After the CPU unit receives the interrupt request from the I / O unit, all the attached I / O
The interrupt signal status notification circuit of the unit is accessed to determine from which I / O unit the interrupt request is issued. The time required for the CPU unit to access the I / O unit is determined by the CPU in the CPU unit. Several times to several times longer than the time required to access the memory
Since it is required to be 0 times, it takes time to determine the presence or absence of an interrupt request, and it takes a long time to execute the interrupt processing program.

The present invention has been made to solve the above-mentioned problems, and has as its object to speed up the time required to transmit an interrupt request / release from an I / O unit to a CPU unit via an interrupt signal line. And especially, CPU
The interrupt signal for requesting / releasing an interrupt from an I / O unit mounted on a base close to the unit can be sped up, and by shortening the execution time of the interrupt processing program executed by the CPU unit, the overall PC It is an object of the present invention to obtain a programmable controller capable of reducing processing time.

[0022]

To achieve the above object, a programmable controller according to the present invention comprises:
In a programmable controller that transmits interrupt signals from a plurality of I / O units on a basic base and an extension base to a CPU unit on the basic base via one shared interrupt signal line in a system bus, the basic base is An interrupt signal line that can electrically separate an interrupt signal from an I / O unit on the basic base and an interrupt signal from an expansion connector for connecting an expansion base, and can provide any signal to the CPU unit Means.

A programmable controller according to the next invention has a plurality of I / Os on a basic base and an extension base.
The interrupt signal from the unit is sent to the CPU on the basic base via one shared interrupt signal line in the system bus.
In the programmable controller for transmitting to the unit, the extension base electrically separates an interrupt signal from an I / O unit on the self extension base from an interrupt signal from an extension connector for connecting another extension base. Is also provided with an interrupt signal line disconnecting means which can be applied to the additional connector on the CPU unit side.

In the programmable controller according to the next invention, the basic base or the extension base interrupt signal line disconnecting means is constituted by an AND gate.

In the programmable controller according to the next invention, the interrupt request is obtained from the state of the interrupt signal line from the I / O unit on the basic base and the state of the interrupt signal line from the extension connector for connecting the extension base. Has an interrupt signal status notifying means for discriminating whether the signal is from an I / O unit on the basic base or an I / O unit on the extension base and notifies the CPU unit of the discrimination result. , I on the base
Only when there is an interrupt request from the I / O unit, the I / O unit on the basic base is searched for the interrupt request source I / O unit and the interrupt processing is executed. When there is no I / O unit on the basic base, the I / O unit of the interrupt request source is not searched for.

In the programmable controller according to the next invention, the state of the interrupt signal line from the I / O unit on the self extension base and the interruption signal line from the extension connector side for connecting another extension base is provided by the interruption signal line dividing means. An interrupt signal for discriminating whether the interrupt request is from an I / O unit on its own extension base or an I / O unit on another extension base and notifying the CPU unit on the basic base of the discrimination result. A status notification unit is provided in the extension base, and only when there is an interrupt request from the I / O unit on the extension base, the I / O unit of the interrupt request source is searched for the I / O unit on the extension base. Executes interrupt processing, and if there is no interrupt request from the I / O unit on the self extension base, interrupts the I / O unit on the self extension base It is not conducted search of the requesting I / O unit.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a programmable controller according to the present invention will be described below in detail with reference to the accompanying drawings. Note that, in the embodiment of the present invention described below, portions having the same configuration as the above-described conventional example are as follows.
The same reference numerals as those of the above-described conventional example are given the same reference numerals, and description thereof will be omitted.

FIG. 1 shows an embodiment of a programmable controller according to the present invention. In the programmable controller according to the present invention, a basic base interrupt control circuit 6 is incorporated in the basic base 1 and an extension base interrupt control circuit 8 is incorporated in the extension base 2.

The basic base interrupt control circuit 6 is mounted near the place where the CPU unit 3 is mounted on the basic base 1 and electrically converts an interrupt signal on the basic base 1 and an interrupt signal from a plurality of extension bases. It includes a circuit for the CPU unit 3 to monitor the state of the interrupt signal on the separated bases 1 and the plurality of extension bases 2 separated from each other.

More specifically, the basic base interrupt control circuit 6
Is an AND gate 6a serving as an interrupt signal line disconnecting means whose output terminal is connected to an interrupt input circuit 3d of the CPU unit 3 by an interrupt signal line 5c, and an interrupt signal line 5b and 5d An interrupt signal status notifying circuit 6b for the CPU unit 3 to determine the presence / absence of an interrupt request on the basic base 1 and the presence / absence of an interrupt request from the extension base 2;
And a pull-up resistor 6c for securely fixing the interrupt signal line 5d of the extension connector 10 to a high level so that an interrupt request does not malfunction when the device is not mounted. The interrupt signal line 5b of the I / O unit 4 is connected to one input terminal of the AND gate 6a, and the interrupt signal line 5d from the extension connector 10 is connected to the AND terminal.
It is connected to the other input terminal of the gate 6a.

The extension base interrupt control circuit 8 is mounted in the vicinity of the extension connector 10 on the extension base 2 and electrically separates the interruption signals of each extension base 2 and checks the state of each of the separated interruption signals. The CPU unit 3 includes a circuit for monitoring.

More specifically, the extension-based interrupt control circuit 8
Is an AND gate 8a as an interrupt signal line disconnecting means whose output terminal is connected to an extension connector (previous stage extension connector) 10 on the basic unit 1 side by an interrupt signal line 7c.
And a signal is input from the interrupt signal lines 7b and 7d via a bus in the basic unit 1 to determine the presence or absence of an interrupt request on the self-expanding base and an interrupt from another extension base that is additionally added to the self-expanding base. An interrupt signal state notifying circuit 8b for the CPU unit 3 to determine whether or not there is a request;
A pull-up resistor 8 for securely fixing the interrupt signal line 7d to a high level so that an interrupt request does not malfunction when another extension base is not added to the self extension base.
c, and a pull-up resistor 8d mounted to prevent a malfunction of the interrupt signal when no I / O unit is mounted on the self-expanding base and for realizing wired OR connection. The interrupt signal line 7b of the I / O unit 4 on the self-
a, and an interrupt signal line 7d from another extension base side extension connector (later stage extension connector) 10 is connected to the other input terminal of the AND gate 6a.

Next, the operation of the programmable controller having the above configuration will be described below. When an I / O unit 4 mounted on the basic base 1, for example, the I / O unit (1) on the basic base 1 generates an interrupt request to the CPU unit 3 by a command from an external input / output device, the basic The interrupt signal line 5b on the base 1 is driven to low level, and then the basic base interrupt control circuit 6
AND gate 6a drives the interrupt signal line 5c to low level, and the interrupt input circuit 3d in the CPU unit 3
To notify that an interrupt request has occurred.

Therefore, when an interrupt request is generated from the I / O unit 4 on the basic base 1, the inverter gate 4b connects the interrupt signal line 5d on the basic base 1, the extension cable 9, and the interrupt signal on the extension base 2 to each other. Lines 7b, 7
Since there is no need to drive c and 7d, I on the basic base 1
The delay time from when the / O unit (1) issues an interrupt request to when the interrupt request reaches the interrupt input circuit 3d in the CPU unit 3 is reduced.

When the I / O unit 4 mounted on the first-stage extension base (1) issues an interrupt request, the interrupt signal line 7b on the extension base (1) is driven to a low level. Then, the AND gate 8a in the extension base interrupt control circuit 8 on the extension base (1) is connected to the interruption signal line 7c on the extension base (1), the interruption signal line in the extension cable (1) and the basic base 1. 5d interrupt signal line
To a low level, the AND gate 6a in the basic base interrupt control circuit 6 drives the interrupt signal line 5c to a low level, and notifies the interrupt input circuit 3d in the CPU unit 3 that an interrupt request has occurred. .

Therefore, when an interrupt request is generated from the I / O unit 4 on the extension base (1), an extra delay time of several nsec for driving two AND gates is required. An interrupt signal line 7b on the extension base other than the base (1), which typically extends over several tens of cm, an interrupt signal line 5b on the basic base 1, and an extension cable (2)
There is no delay time due to the inductance or capacitance of the interrupt signal line in the CPU unit 3 after the I / O unit 4 on the extension base (1) issues an interrupt request as compared with the conventional interrupt signal wiring method. Interrupt input circuit 3d
, The delay time until the interrupt request arrives becomes shorter.

When the I / O unit 4 mounted on the second-stage extension base (2) issues an interrupt request, the interruption signal line 7b on the extension base (2) is driven to a low level, and subsequently. The AND gate 8a in the extension base interrupt control circuit 8 on the extension base (2) includes the interruption signal line 7c on the extension base (2), the interruption signal line in the extension cable (2), and the first-stage extension base (1). ) Interrupt signal line 7 on
Drive d to low level.

As a result, the AND gate 8a in the extension base interrupt control circuit 8 on the extension base (1) is connected to the interruption signal line 7c on the extension base (1), the interruption signal line in the extension cable (1) and the basic base 1. Upper interrupt signal line 5d
To a low level, the AND gate 6a in the basic base interrupt control circuit 6 drives the interrupt signal line 5c to a low level, and notifies the interrupt input circuit 3d in the CPU unit 3 that an interrupt request has occurred.

Therefore, in the example of FIG. 1, the I / O on the second-stage extension base (2) located farthest from the basic base.
When an interrupt request is issued from the unit 4, AND
Although an extra delay time of several nsec for driving three gates is required, an interrupt signal line 7b normally extending to several tens of cm on an extension base other than the extension base (2) and an interrupt signal line on the basic base 1 Since the delay time due to the inductance and the capacitance of 5b disappears, the delay time due to the AND gate drive is canceled, and the C / C is output after the I / O unit 4 on the second-stage expansion base (2) issues an interrupt request.
The delay time until the interrupt request reaches the interrupt input circuit 3d in the PU unit 3 is equal to the delay time in the conventional interrupt signal wiring system.

As described above, an I / O unit mounted on a base closer to the CPU unit 3 on the basic base 1 can transmit an interrupt request to the CPU unit faster.

Further, since the basic base interrupt control circuit 6 and the extension base interrupt control circuit 8 are mounted,
Since the wiring length of the interrupt signal line connecting the OR gate output of the open collector output in the I / O unit with the wired OR connection was shortened, the inductance and the capacitance were reduced, and the I / O unit released the interrupt request. Sometimes, the interrupt signal line 5 that is wired OR-connected
The time required for b and 7b to transition from a low level to a high level due to the pull-up resistor is reduced.

As described above, the programmable controller according to the present invention reduces the number of interrupt signal lines in the system bus and the extension cable by adding several electric components to the conventional base and providing the interrupt control circuit. The time required to transmit an interrupt request / release to the CPU unit can be shortened without increasing the number of interrupts and without changing the interrupt circuit of the CPU unit or the I / O unit.

As described above, the occurrence of an interrupt request is notified to the interrupt input circuit 3d in the CPU unit 3, and when the microprocessor 3a receives the interrupt request via the interrupt input circuit 3d, it is stored in the memory 3b. Start the interrupt processing program.

Also in this case, for convenience, before the CPU unit 3 activates the interrupt processing program, the CPU unit 3 sequentially starts with the extension bases (1),
The extension bases (2) to (j) are positioned, and the presence / absence and mounting position of the I / O unit 4 are known for each base, and the I / O units (1), I It is assumed that they are positioned as / O unit (2) to I / O unit (i).

FIGS. 2 and 3 show a processing flow of an interrupt processing program in the programmable controller according to the present invention. When the interrupt processing program is started, the CPU unit 3 first accesses the interrupt signal status notification circuit 6b in the basic base interrupt control circuit 6 mounted on the basic base 1 (step S1). The state (high level or low level) of the interrupt signal line 5b from the I / O unit 4 and the interrupt signal line 5d from the extension base is monitored, and an interrupt request from the I / O unit 4 mounted on the basic base 1 is monitored. Information for determining the presence / absence and information for determining the presence / absence of an interrupt request from the I / O unit 4 mounted on the extension base 3 are obtained.

Next, it is determined whether or not there is an interrupt request from the I / O unit 4 mounted on the basic base 1 from the state of the interrupt signal line 5b (step S2). If there is an interrupt request, the unit number i to be checked is set to 1 as in the case of the conventional interrupt processing (step S).
3) Access to the interrupt signal status notifying circuits 4c of all the I / O units 4 mounted on the basic base 1 to determine the presence or absence of an interrupt request (step S4, step S4).
5) A predetermined interrupt process is performed for the I / O unit having the interrupt request (step S6).

Thereafter, the I / O mounted on the basic base 1
The process is repeated for the number of O units 4 (step S7, step S8, step S4 to step S7).

If there is no interrupt request from the I / O unit 4 mounted on the basic base 1 in step S2, the I / O unit 4 on the extension base 2 is used instead of the basic base 1. Can be determined to be an interrupt request from step S2, and the process can jump from step S2 to step S10.
All I / O units 4 mounted on the basic base 1
Need not access the interrupt signal status notifying circuit 4c.

As described above, the information is obtained by accessing the interrupt signal status notifying circuit 6b in the basic base interrupt control circuit 6 mounted on the basic base 1, and is mounted on all the additional bases 2. It is possible to determine whether or not there is an interrupt request from the I / O unit 4 (step S9). If there is no interrupt request in this determination, the interrupt processing program ends immediately.

On the other hand, when it is determined that there is an interrupt request from the I / O unit 4 mounted on the extension base 2, the extension base number j to be checked is set to 1
(Step S10), and sequentially accesses the interrupt signal state notification circuit 8b in the interrupt control circuit 8 on the extension base from the extension base (j) close to the basic base 1 (S1).
1), an interrupt signal line 7b from the I / O unit 4 on the self extension base and another extension base (extension base at a later stage)
Monitors the state (high level or low level) of the interrupt signal line 7d from the I / O module,
Information for determining the presence / absence of an interrupt request from the I / O unit 4 and information for determining the presence / absence of an interrupt request from the I / O unit 4 mounted on the subsequent extension base are obtained.

Next, it is determined from the state of the interrupt signal line 7b whether or not there is an interrupt request from the I / O unit 4 mounted on the own extension base (step S12). If there is an interrupt request, the unit number i to be checked is set to 1 as in the conventional interrupt processing (step S1).
3) Access to the interrupt signal status notifying circuits 4c of all the I / O units 4 mounted on the self extension base to determine whether or not there is an interrupt request (step S14, step S14).
15) For the I / O unit having the interrupt request, a predetermined interrupt process is performed (step S16).

Thereafter, the I / O mounted on the self-
The process is repeated for the number of O units 4 (step S17, step S18, step S14 to step S18).
17).

In step S12, if there is no interrupt request from the I / O unit 4 mounted on the self-extension base, it is not on the self-extension base but on the extension base located downstream of the self-extension base. It can be determined that the request is an interrupt request from the I / O unit 4.
19, so that it is not necessary to access the interrupt signal state notification circuits 4c of all the I / O units 4 mounted on the self-expanding base.

As described above, the determination as to which I / O unit issues an interrupt request is made in advance in base units. In particular, the larger the number of I / O units and extension bases mounted, the greater the determination. The time required to execute the interrupt processing program is shorter than before, and the execution time of the entire interrupt processing program can be shortened.

[0055]

As can be understood from the above description, according to the programmable controller of the present invention, the interrupt signal from the I / O unit on the basic base and the interrupt signal from the additional connector for connecting the additional base are provided. Since the interrupt signal line is electrically separated by the interrupt signal line separating means, the path of the interrupt signal line from one interrupt request / release to the CPU unit can be shortened from one I / O unit to the I / O unit. Interrupt request to CPU unit
Propagation delay of an interrupt signal for notifying release can be reduced. As a result, the time required for transmitting an interrupt request / release from the I / O unit to the CPU unit via the interrupt signal line can be shortened. In particular, an interrupt from the I / O unit mounted on the base close to the CPU unit can be achieved. The speed of an interrupt signal for request / release can be increased.

According to the programmable controller of the next invention, the interrupt signal from the I / O unit on the self-extensible base and the interrupt signal from the extra connector for connecting another extensible base are electrically connected by the interrupt signal line disconnecting means. , The path of the interrupt signal line from the transmission of the interrupt request / release to the CPU unit from a certain I / O unit can be shortened.
The propagation delay of the interrupt signal for notifying the PU unit of the interrupt request / release can be reduced. As a result, the time required for transmitting an interrupt request / release from the I / O unit to the CPU unit via the interrupt signal line can be shortened. In particular, an interrupt from the I / O unit mounted on the base close to the CPU unit can be achieved. The speed of an interrupt signal for request / release can be increased.

According to the programmable controller of the next invention, since the basic-base or extension-base interrupt signal line disconnecting means is constituted by an AND gate,
Electrical disconnection of the interrupt signal line can be easily performed by a general circuit element.

According to the programmable controller of the next invention, when there is no interrupt request from the I / O unit on the basic base, the I / O unit of the interrupt request source is searched for the I / O unit on the basic base. Therefore, the execution time of the interrupt processing program executed by the CPU unit can be shortened, whereby the processing time of the entire PC can be shortened.

According to the programmable controller of the next invention, when there is no interrupt request from the I / O unit on the self-extensible base, the I / O unit on the self-extensible base is searched for the I / O unit that has issued the interrupt request. Is not performed, the execution time of the interrupt processing program executed by the CPU unit can be shortened, whereby the processing time of the entire PC can be shortened.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing one embodiment of a programmable controller according to the present invention.

FIG. 2 is a flowchart showing the first half of an interrupt processing flow in the programmable controller according to the present invention.

FIG. 3 is a flowchart showing the latter half of the interrupt processing flow in the programmable controller according to the present invention.

FIG. 4 is a system configuration diagram showing one embodiment of a conventional programmable controller.

FIG. 5 is a flowchart showing a first half of an interrupt processing flow in a conventional programmable controller.

FIG. 6 is a flowchart showing a latter half of an interrupt processing flow in a conventional programmable controller.

[Explanation of symbols]

1 basic base, 2 extension base, 3 CPU unit, 3a microprocessor, 3b memory, 3c
System bus control circuit, 3d interrupt input circuit, 4 I
/ O unit, 4a interrupt request circuit, 4b inverter gate, 4c interrupt signal status notification circuit, 5 system bus on basic base, 5a, 5b, 5c, 5d
Interrupt signal line on basic base, 5e Signal line other than interrupt signal on basic base, 6 basic base interrupt control circuit, 6a AND gate, 6b interrupt signal status notification circuit, 6c pull-up resistor, 7 system bus on extension base 7a, 7b, 7c, 7d Interrupt signal line on extension base, 7e Signal line other than interrupt signal on extension base, 8 Extension base interrupt control circuit, 8a AND gate, 8b Interrupt signal status notification circuit, 8c, 8d pull Up resistor, 9 extension cable, 10 extension connector,
11 Power supply unit.

Claims (5)

[Claims] 1. A programmable controller for transmitting interrupt signals from a plurality of I / O units on a basic base and an extension base to a CPU unit on the basic base via one shared interrupt signal line in a system bus. In the basic base, the interrupt signal from the I / O unit on the basic base and the interrupt signal from the extension connector for connecting the extension base are electrically separated, and any of the signals
A programmable controller comprising interrupt signal line disconnecting means that can be given to a U unit. 2. A programmable controller for transmitting interrupt signals from a plurality of I / O units on a basic base and an extension base to a CPU unit on the basic base via one shared interrupt signal line in a system bus. In the extension base, the interruption signal from the I / O unit on the extension base itself and the interruption signal from the extension connector for connecting another extension base are electrically separated, and any of the signals is connected to the CPU unit. A programmable controller comprising interrupt signal line disconnecting means that can be given to the additional connector. 3. The programmable controller according to claim 1, wherein the interrupt signal line disconnecting means of the basic base or the extension base is an AND gate. 4. An interrupt request from the I / O unit on the basic base and an interrupt signal line from the extension connector side for connecting the extension base by the interruption signal line dividing means, the interruption request being sent from the I / O unit on the basic base. An interrupt signal state notifying means for judging whether the signal is from the I / O unit or the I / O unit on the extension base and notifying the CPU unit of the judgment result; I / O unit on the basic base only when there is an interrupt request from the I / O unit
The I / O unit on the basic base is searched to execute an interrupt process. If there is no interrupt request from the I / O unit on the basic base, the I / O unit on the basic base
2. The programmable controller according to claim 1, wherein a search for an / O unit is not performed. 5. An interrupt request is self-expanded by the interrupt signal line disconnecting means based on the status of an interrupt signal line from an I / O unit on the self-expansion base and an interrupt signal line from an extension connector for connecting another expansion base. It is determined whether it is from an I / O unit on the base or from an I / O unit on another extension base, and the determination result is used as the CP on the basic base.
An interrupt signal status notifying means for notifying the U unit is provided in the extension base, and the I / O unit on the self extension base receives the I / O unit of the interrupt request source only when there is an interrupt request from the I / O unit on the self extension base. The I / O unit is searched to execute the interrupt processing. If there is no interrupt request from the I / O unit on the self extension base, the I / O unit on the self extension base is
3. The programmable controller according to claim 2, wherein the I / O unit of the interrupt request source is not searched for the O unit.