JP2000156519A - Infrared-ray detecting device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form contact holes for positive-side and negative-side electrodes by a single etching process while preventing formation of an overetching zone to the reverse conducting zone. SOLUTION: A surface control layer 2 made of a semiconductor layer having a wide forbidden band width is provided on a conducting semiconductor layer 1 having a narrow forbidden band width. Etching stopper electrodes 4 are provided on the surface control layer 2 on the reverse conducting zone 3 forming a diode passed through the control layer 2 and reaching the semiconductor layer 1. Contact holes 7 corresponding to the stopper electrodes 4 are made in an insulating film 5 covering the stopper electrodes 4. A contact hole 6 passed through the control layer 2 is made in the semiconductor layer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an infrared detector and a method of manufacturing the same, and more particularly, to an infrared detector (IRPPA: InfraRed Focal Pla).
The present invention relates to a method for forming a contact hole for an HgCdTe photodiode array used in a Ne Array, an infrared detecting device having an electrode structure therefor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an infrared detector for detecting infrared rays in the vicinity of the 10 μm band has a Cd composition ratio of about 0.2,
For example, a pn junction diode formed on a HgCdTe layer having a Cd composition ratio of 0.22 is used as a photodiode, and the photodiode is arranged in a one-dimensional array or a two-dimensional array, and the electrical connection between the photodiode and a read circuit is made. In order to make an intimate contact, a structure is adopted in which an infrared photodiode array substrate and a Si signal processing circuit substrate are bonded together with a metal bump such as In formed on both.

Here, the manufacturing process of a conventional infrared detector will be described with reference to FIGS. 4 (a) and 4 (b). Referring to FIG. 4A, first, the Hg vacancy concentration is set to 1 on a CdZnTe substrate (not shown) in a Te-rich melt by using a closed tube chipping method.
Non-doped p-type HgCdTe layer 3 of about 0 ¹⁷ cm ^-3
1 was subjected to liquid phase epitaxial growth, and then heat-treated at a temperature of 200 to 400 ° C. in Hg vapor to obtain Hg.
By filling the vacancies with Hg atoms, p-type HgCdT
The hole concentration of the e-layer 31 is controlled to the order of 10 ¹⁶ cm ⁻³ .

[0004] Then, in order to flatten the surface and make the thickness uniform, alumina polishing is performed to obtain p-type HgCdTe.
After controlling the thickness of the layer 31 to 15 to 25 μm, B ions are selectively implanted using a resist pattern (not shown) as a mask to form an n-type region 32 to form a photodiode.

Then, after removing the resist pattern, the entire surface of Cg, which is a broad bandgap semiconductor, is made of HgCdTe.
After the dTe layer 33 is provided as a surface control layer for stably controlling the surface of the p-type HgCdTe layer 31, a ZnS film 34 is formed thereon as a protective insulating film.

Referring to FIG. 4B, a resist pattern (not shown) is used as a mask.
And sulfuric acid + water (H_TwoSO _Four: H_TwoO = 1: 1)
Selectively etch ZnS film 34 using etchant
And then add 1wt% Br to methanol
CdTe layer 33 using 1 wt% Br methanol
Is selectively etched to form p-type HgCdT
Contact hole 35 and n-type region 3 for e layer 31
A contact hole 36 for 2 is formed.

Next, although not shown, after removing the resist pattern, an In electrode serving as an n-side electrode, and
An Au electrode serving as a p-side electrode was formed, and then an In bump was formed by a lift-off method.

In the step of forming the contact holes 35 and 36, ZnS is performed by dry etching using plasma using a mixed gas of hydrogen and argon instead of wet etching.
By selectively etching the film 34 and the CdTe layer 33,
Contact hole 35 for p-type HgCdTe layer 31
Also, a contact hole 36 for the n-type region 32 is formed.

[0009]

However, when a contact hole is formed by wet etching, since the ZnS film 34 and the CdTe layer 33 have different etchants, it is necessary to perform an etching process for each of them. There is a problem of increasing.

Referring to FIG. 4C, there are few etchants having selectivity for CdTe and HgCdTe. As shown in the figure, over-etching regions 37 and 38 are formed at the bottoms of the contact holes 35 and 36 by over-etching. Side electrode is p-type Hg
There is a possibility that the CdTe layer 31 may be short-circuited, and there is a problem of lack of reliability.

[0011] Further, while the CdTe layer 33 is adhered, B
When the pn junction is formed by selectively transmitting and implanting ions, the resistance of the CdTe layer 33 on the n-type region 32 is reduced. Therefore, when the contact hole 36 for the n-type region 32 is formed, the ZnS film is formed. Only the etching of 34 is sufficient, but in this case, a dedicated mask and an etching step for forming the contact hole 35 for the p-type HgCdTe layer 31 are required, and there is a problem that the number of steps increases.

On the other hand, when dry etching is used to form the contact holes 35 and 36, the ZnS film 34 and the CdTe layer 33 can be etched simultaneously, which reduces the number of steps. Since the dry etching has poor selective etching property with respect to the p-type HgCdTe layer 31, there is a problem that the over-etched regions 37 and 38 are formed as in the case shown in FIG.

Accordingly, it is an object of the present invention to form a contact hole for an n-side electrode and a p-side electrode by a single etching step without generating an over-etching region for a reverse conductivity type region.

[0014]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1. (1) The present invention provides a surface control layer 2 made of a wide band gap semiconductor layer on a one conductivity type narrow band gap semiconductor layer 1, and penetrates the surface control layer 2 to form a one conductivity type narrow band gap. In the infrared detecting device in which the diode is constituted by the reverse conductivity type region 3 reaching the band width semiconductor layer 1, the etching stopper electrode 4 is provided on the surface control layer 2 on the reverse conductivity type region 3 and the etching stopper electrode 4 is covered. Forming a contact hole for the etching stopper electrode in the insulating film;
A surface control layer 2 for one conductivity type narrow bandgap semiconductor layer 1
The contact hole 6 penetrating through is provided.

As described above, by providing the etching stopper electrode 4 on the surface control layer 2 on the reverse conductivity type region 3, the contact hole 7 is formed without generating an over-etching region with respect to the reverse conductivity type region 3. Therefore, the signal extraction electrode 9 for the opposite conductivity type region 3 does not short-circuit with the one conductivity type narrow bandgap semiconductor layer 1. In the present invention, the “one conductivity type narrow bandgap semiconductor layer” refers to a Hg-based II-
It means a one-conductivity narrow bandgap semiconductor layer or a one-conductivity narrow bandgap semiconductor substrate such as a group VI compound semiconductor or lead chalcogenite.

(2) In the present invention, in the above (1), the one-conductivity type narrow bandgap semiconductor layer 1 is formed of Hg _1-x Cd _x T
e (0 <x <1), and the surface control layer 2 is made of Cd _1-y Z
n _y Te (0 ≦ y ≦ 1), and the insulating film 5 is made of Z
nS.

As described above, the one conductivity type narrow bandgap semiconductor layer 1
Is Hg_1-xCd_xIf Te (0 <x <1), the table
As the surface control layer 2 for stabilizing the surface, Cd_1-y
Zn _yTe (0 ≦ y ≦ 1), typically CdTe is preferred
It is preferable that the insulating film 5 is made of ZnS.

(3) According to the present invention, a surface control layer 2 made of a wide bandgap semiconductor layer is provided on a narrow band gap semiconductor layer 1 of one conductivity type. In a method for manufacturing an infrared detecting device in which a diode is formed by the reverse conductivity type region 3 reaching the narrow bandgap semiconductor layer 1, an etching stopper electrode 4 is formed on the surface control layer 2 on the reverse conductivity type region 3 and then the entire surface is formed. When the contact holes 6 and 7 are formed, the contact hole 7 for the reverse conductivity type region 3 is etched until it reaches the etching stopper electrode 4, and the contact hole 7 for the one conductivity type narrow bandgap semiconductor layer 1 is formed. The contact hole 6 is characterized in that etching is performed until the contact hole 6 reaches the one conductivity type narrow bandgap semiconductor layer 1 through the surface control layer 2.

As described above, even in the case of an infrared detector in which a diode is formed by the reverse conductivity type region 3 penetrating the surface control layer 2 and reaching the one conductivity type narrow bandgap semiconductor layer 1, the reverse conductivity type region 3 By providing the etching stopper electrode 4, the contact hole 7 for the etching stopper and the contact hole 6 for the one-conductivity type narrow bandgap semiconductor layer 1 can be formed by either wet etching or dry etching. At the same time, since it can be formed without generating an over-etched region with respect to the reverse conductivity type region 3, it is possible to prevent a short circuit without increasing the number of steps.

(4) Further, according to the present invention, in the above (3), the etching stopper electrode 4 is formed on the opposite conductivity type region 3 by using the mask used for forming the opposite conductivity type region 3 as it is. It is characterized by being formed in a self-aligned manner.

As described above, the etching stopper electrode 4
Is formed in a self-aligned (self-aligned) manner by the lift-off method using the mask used for forming the reverse conductivity type region 3 as it is, thereby simplifying the electrode forming process and increasing the size. The etching stopper electrode 4 having a large area can be formed, thereby reducing the alignment accuracy when forming the contact hole 7.

(5) In the present invention, in the above (3) or (4), the reverse conductivity type region 3 is formed by selectively introducing a conductivity type determining impurity into the one conductivity type narrow bandgap semiconductor layer 1. It is characterized by forming by doing.

As described above, the region 3 of the opposite conductivity type is not only made to have the opposite conductivity type by a crystal defect accompanying implantation of B ions or the like, but also has
It may be formed by selectively introducing conductivity type determining impurities such as s and Sb into the one conductivity type narrow bandgap semiconductor layer 1 by an ion implantation method or a diffusion method.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a manufacturing process according to an embodiment of the present invention will be described with reference to FIGS. In order to simplify the description, a description will be given as a process of forming two photodiodes. Referring to FIG. 2 (a), first, as in the conventional case, Te is used by using
H on a CdZnTe substrate (not shown) in a rich melt
Non-doped p-type H having a vacancy concentration of about 10 ¹⁷ cm ^-3
After the liquid phase epitaxial growth of the gCdTe layer 11 (Cd ratio 0.22), 200 to 40 g
By filling the Hg vacancies with Hg atoms by heat treatment at a temperature of 0 ° C., the hole concentration of the p-type HgCdTe layer 11 is controlled to the order of 10 ¹⁶ cm ⁻³ .

Next, in order to flatten the surface and make the thickness uniform, alumina polishing is performed to obtain p-type HgCdTe.
After controlling the thickness of the layer 11 to 15 to 25 μm, the CdTe layer 1 having a thickness of 10 to 500 nm, for example, 100 nm is formed on the p-type HgCdTe layer 11 by using an electron beam evaporation method.
2 is deposited as a surface control layer for surface stabilization.
The CdTe layer 12 in this case is considered to be polycrystalline.

Next, for example, 20 μm square and an interval of 10
Using the resist pattern 13 having an opening having a thickness of μm as a mask, the B ions 14 are supplied at an acceleration energy of 130 to 180 keV, for example, 150 keV, and 1.0 × 10 ¹³
~ 1.0 × 10 ¹⁵ cm ⁻² , for example, 1.0 × 10 ¹⁴ cm
^An n-type region 15 to be a photodiode is formed by selectively ion-implanting ⁻² . In this ion implantation step, a crystal defect is generated in the region of the CdTe layer 12 into which the B ions 14 have been implanted, so that the resistance is reduced.

Next, referring to FIG. 2B, using the resist pattern 13 as a mask as it is, using an electron beam evaporation method,
5 nm of Cr, 10 nm of Au, and 5 nm of Pt are sequentially deposited to form Cr / Cr serving as an etching stopper electrode.
An Au / Pt electrode 16 is formed.

Next, as shown in FIG. 2C, the Cr / Au / Pt electrode 16 deposited on the resist pattern 13 is lifted off by removing the resist pattern 13 so that C is self-aligned with the n-type region 15.
After the r / Au / Pt electrode 16 is left as an etching stopper electrode and an ohmic electrode, a thickness of 100 to 2000 nm, for example, 300
A ZnS film 17 of nm is deposited as a protective insulating film. In this case, the resistance of the CdTe layer 12 existing on the n-type region 15 is reduced, so that the n-type region 15 and the Cr / Au / Pt
The conduction with the electrode 16 is established.

Next, a photoresist is applied to a portion where a contact hole for the n-type region 15 is to be formed, for example, 5 μm.
□ opening is formed, and the p-type HgCdTe layer 11 is formed.
For example, in a portion where a contact hole for
The resist pattern 18 is formed by exposing and developing so as to form an opening of 15 μm square.

Then, using the resist pattern 18 as a mask, hydrogen is supplied at a flow rate of 1 sccm and argon at a flow rate of 6 sccm, the degree of vacuum is set at about 0.13 Pa (1 × 10 ³ Torr), and at room temperature, about 40 W of high-frequency power of 40 MHz is applied to the substrate holder. Then, hydrogen and argon are turned into plasma, and the ZnS film 17 is etched by dry etching using the plasma to form a contact hole 19 for the n-type region 15.

Subsequently, the plasma drying was performed under the same conditions.
By performing etching, the p-type HgCdTe layer 1 is formed.
Cd exposed in the portion provided with the opening for
The contact hole 20 is formed by etching the Te layer 12.

In this case, the etching rate of the ZnS film 17 under the plasma dry etching condition is 1
5 nm / min, and the ratio of the etching rate to each layer was HgCdTe: CdTe: ZnS = 8: 4:
1 so that the lower layer is more easily etched,
In the contact hole 20, the p-type HgCdTe layer 1
1 is also easily etched to form an over-etched region. However, in the contact hole 19, since the Cr / Au / Pt electrode 16 serving as an etching stopper is provided, the etching is automatically stopped on the surface of Pt, and No etched area is formed.

Next, after removing the resist pattern 18, a Cr film is deposited on the entire surface by sputtering, and then etched into a predetermined shape to form the signal extraction electrode 2.
1 and 22 are formed and then connected to the signal extraction electrodes 21 and 22 by a lift-off method (not shown).
By forming n bumps, the basic configuration of the infrared photodiode array is completed.

As described above, in the embodiment of the present invention, the p-type HgCdTe
Since the contact hole 20 for the layer 11 and the contact hole 19 for the n-type region 15 are formed at the same time, only one type of mask is required for etching, so that the process is greatly simplified.

In this case, since the Cr / Au / Pt electrode 16 serving as an etching stopper in the contact hole forming step is provided on the n-type region 15 via the low-resistance CdTe layer 12, the n-type region 15 is formed. Contact hole 19 stops at Cr / Au / Pt electrode 16, so that no over-etched region is formed in n-type region 15, and therefore the n-side electrode and p-type Hg
Since there is no short circuit with the CdTe layer 11, the device characteristics do not deteriorate.

In the embodiment of the present invention, n
Since the CdTe layer 12 always exists on the n-type region 15, the Cr / Au / Pt electrode 16 is not in contact with the surface of the n-type region 15 made of a narrow band gap semiconductor, so that the surface is stably controlled. As a result, the deterioration of the device characteristics can be suppressed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made. For example, in the description of the above embodiment, the contact hole 1
In the plasma dry etching process for forming the layers 9 and 20, a gas composed of hydrogen and argon is used, but a gas composed of nitrogen and argon, a gas composed of hydrogen and nitrogen, or a gas composed of hydrogen and nitrogen and argon Even when a gas is used, favorable etching can be performed. When a gas containing nitrogen is used, flat etching can be performed and no etching residue is generated.

The dry etching step is not limited to the plasma dry etching step, but may be a sputter dry etching step using an inert gas such as argon, helium, neon, or xenon.

Further, in the above description of the embodiment, when the contact holes 19 and 20 are formed, dry etching is used. However, wet etching may be used. Is a ZnS film 1
In the etching step 7, sulfuric acid: water is, for example,
A 1: 1 etchant may be used, and 1 wt% Br methanol may be used in the step of etching the CdTe layer 12.

Further, in the etching step of the ZnS film 17, sulfuric acid + acetic acid or sulfuric acid + perchloric acid may be used instead of sulfuric acid + water. Since it is small, the controllability of etching is enhanced.

In the description of the above embodiment, the n-type region 15 is formed by ion-implanting the B ions 14. However, the n-type impurity such as As or Sb is diffused or ion-implanted. It may be formed by:

In the above embodiment, the Cr / Au / Pt electrode 16 serving as an etching stopper is provided by using a lift-off method in order to simplify the process and eliminate the need for positioning accuracy. However, the present invention is not necessarily limited to the lift-off method.
After depositing the three-layered conductive film, the film may be etched into a predetermined shape to form an etching stopper electrode.

In the above embodiment, the CdTe layer 12 serving as a surface control layer and the ZnS film 17 serving as a protective insulating film are deposited using an electron beam evaporation method. It is not limited to
An epitaxial growth method, another evaporation method, or a sputtering method may be used.Moreover, instead of using the same film forming method for both, the epitaxial growth method, the evaporation method, and the sputtering method are combined. It may be used.

In the above embodiment, Hg is used as a semiconductor for forming a photodiode array.
_Although explained using _0.78 Cd _0.22 Te, Hg _0.78 C
It is not limited to d _{0. 22} Te, other compositional ratio Hg
CdTe may be used, or HgTe, HgZn
A semiconductor whose conductivity type is inverted due to physical damage such as Te or HgCdZnTe may be used. Further, the present invention is also applied to a lead chalcogenide having a narrow band gap such as PbSSe or PbSnTe.

Further, a discrete element may be used instead of the photodiode array. For example, Cg of HgCdTe may be used.
An APD (avalanche photodiode) may be formed by setting the d ratio to about 0.60.

[0046]

According to the present invention, when a contact hole for the one conductivity type narrow bandgap semiconductor layer and a contact hole for the opposite conductivity type region forming the photodiode are formed, the contact hole is formed on the opposite conductivity type region. Since the etching stopper electrode is provided via the forbidden band width semiconductor layer, both contact holes can be formed at the same time without generating an over-etching region in the opposite conductivity type region, thereby simplifying the manufacturing process. In addition, since the degree of integration can be improved without impairing reliability due to a short circuit through the over-etched region, a highly reliable infrared photodiode array can be formed with good reproducibility, and as a result, high integration can be achieved. It greatly contributes to the practical use of high-resolution infrared sensors.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through an embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory view of a manufacturing process and a problem of a conventional infrared detection device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 one conductivity type narrow bandgap semiconductor layer 2 surface control layer 3 reverse conductivity type region 4 etching stopper electrode 5 insulating film 6 contact hole 7 contact hole 8 signal extraction electrode 9 signal extraction electrode 11 p-type HgCdTe layer 12 CdTe layer 13 resist Pattern 14 B ion 15 n-type region 16 Cr / Au / Pt electrode 17 ZnS film 18 resist pattern 19 contact hole 20 contact hole 21 signal extraction electrode 22 signal extraction electrode 31 p-type HgCdTe layer 32 n-type region 33 CdTe layer 34 ZnS film 35 contact hole 36 contact hole 37 over-etched area 38 over-etched area

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Koji Fujiwara 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tetsuya Miyatake 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Limited F term (reference) 5F049 MA02 MA07 MB01 NA08 PA10 PA11 PA14 PA18 RA02 SE05 SS02 WA01

Claims (5)

[Claims] A surface control layer comprising a wide bandgap semiconductor layer is provided on a one-conductivity narrow bandgap semiconductor layer, and penetrates the surface control layer to reach the one-conductivity narrow bandgap semiconductor layer. In the infrared detection device in which a diode is formed by a reverse conductivity type region, an etching stopper electrode is provided on the surface control layer on the reverse conductivity type region, and a contact with the etching stopper electrode is provided on an insulating film covering the etching stopper electrode. An infrared detector, wherein a hole is provided, and a contact hole penetrating the surface control layer is provided for the one conductivity type narrow bandgap semiconductor layer. 2. The semiconductor device according to claim 1, wherein said one conductivity type narrow bandgap semiconductor layer is Hg.
_1-x Cd _x Te (0 <x <1), the surface control layer is made of Cd _1-y Zn _y Te (0 ≦ y ≦ 1), and the insulating film is made of ZnS. The infrared detecting device according to claim 1, wherein 3. A one-conductivity-type narrow bandgap semiconductor layer is provided on a one-conductivity-type narrow bandgap semiconductor layer, and reaches the one-conductivity-type narrow bandgap semiconductor layer through the surface control layer. In the method of manufacturing an infrared detection device that forms a diode by the reverse conductivity type region, after forming an etching stopper electrode on the surface control layer on the reverse conductivity type region,
When the entire surface is covered with an insulating film and a contact hole is formed, the contact hole for the opposite conductivity type region is etched until it reaches the etching stopper electrode, and the contact hole for the one conductivity type narrow bandgap semiconductor layer is A method of manufacturing an infrared detector, wherein etching is performed until the semiconductor layer reaches the one-conductivity narrow bandgap semiconductor layer through a surface control layer. 4. The method according to claim 1, wherein the etching stopper electrode is formed in a self-aligned manner with respect to the opposite conductivity type region, using a mask used for forming the opposite conductivity type region as it is. 3. The method for manufacturing an infrared detection device according to item 3. 5. The semiconductor device according to claim 3, wherein the reverse conductivity type region is formed by selectively introducing a conductivity type determining impurity into the one conductivity type narrow bandgap semiconductor layer. Manufacturing method of the infrared detecting device.