JP2000155691A - Control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control system which performs needed interrupt processing without needing an interrupt processing circuit dedicated for a CPU. SOLUTION: This system has a main CPU 1, a one chip microcomputer 10 which receives and processes an interrupt from external peripheral equipment 8 and 9, outputs the processed results and also generates an interrupt signal to the main CPU 1 in prescribed timing and a RAM 7 for communication which receives and stores the output of the processed results from the microcomputer 10 and is for transferring it to the main CPU, and the CPU 1 fetches the processed results stored in the RAM 7 for communication and performs interrupt processing based on receiving an interrupt signal from the microcomputer 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system for efficiently controlling an interruption to a main control device executing a main program.

[0002]

2. Description of the Related Art In general, in an arcade game device specialized to execute only a specific game, there are many peripheral devices such as a display device, a sound device, and an input / output device such as a joystick. Various interrupts occur at various timings for the (CPU).

However, high-speed CPUs used in such game machines often do not include an interrupt controller, and it is impossible for the CPU alone to efficiently control interrupts from peripheral devices. For this reason, in a conventional game machine, it was necessary to equip a CPU support chipset supplied by each CPU manufacturer.

[0004] This chipset uses interrupt processing logic dedicated to the CPU, and is capable of realizing high-level interrupts.

[0005]

By the way, in a game device, a high-speed CPU is required, while an OS dedicated to a game is used and an interrupt from a specific peripheral device only needs to be processed. In many cases, a simple interrupt processing circuit is not required. On the other hand, a chip set supplied by a CPU manufacturer has a very high level of interrupt processing logic in order to support a general-purpose system, and may be very expensive. For this reason, there was a case where the disadvantage in terms of cost was large.

The present invention has been made in view of such circumstances, and has as its object to provide a control system capable of performing necessary interrupt processing without requiring an interrupt processing circuit dedicated to a CPU. It is.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention receives and processes an interrupt from a main control device and an external peripheral device, outputs a processing result, and outputs the processing result. A sub-controller that generates an interrupt signal at a predetermined timing for the device, and receives and stores an output of a processing result from the sub-controller,
A communication memory for transferring to the main control device, wherein the main control unit extracts a processing result stored in the communication memory based on receiving an interrupt signal from the sub control device. Provided is a control system that performs interrupt processing.

In the above-mentioned system, when an interrupt from an external device to the main control unit occurs, the sub-control device stores data specifying the device in which the interrupt occurred in the communication RAM, and stores the data in the communication RAM. The unit is configured to process an interrupt from the external device by receiving, from the communication RAM, data specifying an interrupted device based on receiving an interrupt signal from the sub-control device. Is preferred.

According to such a configuration, all interrupts can be centrally managed programmatically by the sub-controller, so that there is no need to provide a dedicated interrupt controller in the main CPU.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a control device according to the present invention will be described with reference to an example in which the control device is applied to a control circuit of a game device.

FIG. 1 is a functional block diagram showing a control circuit according to the present invention. The bus A to which the main CPU 1 is connected includes, in addition to a first ROM 2 and a first RAM 3 for the bus A, a communication IC 4 directly controlled by the main CPU 1.
And an ASIC 5 as an image processor. The ASIC 5 is connected to a CRT (display device) (not shown), functions as a display controller, and has a function of generating a synchronization signal for synchronizing with a display.

The communication IC 4 operates when communicating with the outside, and generates an interrupt according to the operation. The first ROM 2 stores a microprogram (OS for the main CPU) that stores the operation procedure of the main CPU 1 for the interrupt operation.

The bus A has a communication RAM 7
Is connected to the bus B via A relatively low-speed peripheral device, that is, a sound controller 8 and an I / O 9 are connected to the bus B. The bus B is connected to a one-chip microcomputer 10 for controlling these peripheral devices and a second ROM 11 and a second RAM 12 for the bus B. That is, all the devices connected to the bus B are controlled by the one-chip microcomputer 10 in principle. In the second ROM 11,
A microprogram (OS for one-chip microcomputer) for controlling the one-chip microcomputer 10 is stored.

The control circuit according to the present invention is characterized in that interrupts to the main CPU 1 are centrally managed by the one-chip microcomputer 10, and the procedure for the first and second microcomputers is as follows.
It is included in the microprogram stored in the second ROMs 2 and 11.

That is, a device that generates an interrupt in the control circuit is an ASIC connected to the bus A.
5, a communication IC 4, a sound circuit 8, an I / O, and the like 9 connected to the bus B. Here, an interrupt from a device (sound circuit 8, I / O, or the like 9) connected to the bus B is processed by the one-chip microcomputer 10, and the one-chip microcomputer 10 transmits only the processing result to the main CP.
Communication RAM in preparation for interruption to U1
7 is executed. On the other hand, when a device (ASIC 5, communication IC 4) connected to the bus A generates an interrupt, the one-chip microcomputer 10 performs an operation of writing data of the device that generated the interrupt into the communication RAM 7. Do.

The one-chip microcomputer 10 interrupts the main CPU 1 at a certain timing based on, for example, a synchronization signal from the ASIC 5 (indicated by a dashed line in the figure). Based on this, the main CPU 1 accesses the communication RAM 7 and
An interrupt task is performed for each data stored in M7.
That is, while receiving and processing the processing result of the device connected to the bus A, the interrupt of the device connected to the bus B is permitted. The execution order (priority order) of the interrupt task is determined by, for example, a program stored in the second ROM 11.

FIG. 2 is a flowchart showing this procedure. In this flowchart, the processing flow of the one-chip microcomputer 10 is displayed on the left, and the processing flow of the main CPU 1 is displayed on the right.

First, the one-chip microcomputer 10 monitors an interrupt from the devices (8, 9) connected to the bus B in step S1. When an interrupt from a device connected to the bus B is detected, the interrupt is processed (step S2), and the processing result is stored in the communication RAM 7.
(Step S3).

On the other hand, as shown in the flow on the right side, if the main CPU 1 detects an interrupt from the device (4, 5) connected to the bus A (step S4), it interrupts the one-chip microcomputer 10 and Is notified (step S5).

The one-chip microcomputer 10 executes step S6
When an interrupt from the CPU 1 is detected in step S7, data on what device the interrupt occurred on the bus A is written into the communication RAM 7 (step S7).

The one-chip microcomputer 10 repeats steps S1 to S7 until a predetermined interrupt timing for the main CPU 1 arrives (step S8). By these steps S1 to S7, all the information necessary for the interrupt processing has been written into the communication RAM 7 by the one-chip microcomputer 10.

Next, in step S8, it is detected that an interrupt timing to the main CPU 1 has arrived (for example, A
If the detection is performed based on the signal generated in the SIC 5), an interrupt to the main CPU 1 is issued in a step S9. Upon receiving this, the main CPU 1 determines in step S10 whether or not there has been an interrupt signal from the one-chip microcomputer 10, and if there has been an interrupt, based on that,
Execute a predetermined interrupt task (steps S11 and S11).
12).

That is, first, in step S11, the processing result of the device connected to the bus B written in the communication RAM 7 is extracted and processed. The processing result is transferred to the one-chip microcomputer 10 via the communication RAM 7.

Next, in step S12, an interrupt of a device connected to the bus A is permitted based on the data written in the communication RAM 7, and an interrupt process is performed.

The order of the interrupt processing performed by the main CPU 1 may be determined by the one-chip microcomputer 10 and written in the communication RAM 7, or may be determined by the main CPU 1 independently.

According to such a configuration, it is possible to provide a control circuit capable of performing necessary interrupt processing without requiring an interrupt processing circuit dedicated to the CPU. In particular, a high-speed CPU (main CPU 1) and a low-speed CPU
In the case of a general arcade game device constituted by the (one-chip microcomputer 10), there is no need to incorporate a dedicated support chip set, so that there is a great cost advantage.

Further, since the interrupt generation signal of the entire system is processed in software by the one-chip microcomputer 10, the interrupt processing can be performed dynamically and intelligently with a high degree of freedom. For example, it is also possible to change the interrupt priority order according to the processing only by replacing the microprogram.

The present invention is not limited to the above-described embodiment, but can be variously modified without changing the gist of the invention.

For example, in the above embodiment, a control system for a game has been described as an example, but the present invention is not limited to a game.

The microprogram is stored in the ROM, but may be stored in the RAM. In this case, there is an effect that the program can be easily changed. Further, the program may not be incorporated in the OS, but may be included in an application program.

[0031]

According to the configuration of the present invention described above,
Without the need for a CPU dedicated interrupt processing circuit,
There is an effect that necessary interrupt processing can be performed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram for explaining an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main CPU (Main control device) 2 ... 1st ROM 3 ... 1st RAM 4 ... Communication IC (external peripheral device) 5 ... ASIC (external peripheral device) 7 ... Communication RAM (communication memory) 8 ... Sound controller (external peripheral device) 9 ... I / O etc. (external peripheral device) 10 ... One-chip microcomputer (sub-controller) 11 ... Second ROM 12 ... Second RAM

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G05B 15/02 W

Claims (3)

[Claims] A sub-control unit for receiving and processing an interrupt from an external peripheral device, outputting a processing result, and generating an interrupt signal at a predetermined timing with respect to the main control device. And a communication memory for receiving and storing the output of the processing result from the sub-control device, and for passing the output to the main control device. The main control unit transmits an interrupt signal from the sub-control device. A control system, wherein a processing result stored in the communication memory is taken out based on the acceptance and interrupt processing is performed. 2. The control system according to claim 1, wherein, when an interrupt from an external device to the main control unit occurs, the sub-control device stores data specifying the device in which the interrupt has occurred in the communication RAM. The main control unit may receive an interrupt signal from the auxiliary control device, receive data specifying the interrupted device from the communication RAM, and process the interrupt from the external device. A control system characterized by the following. 3. The control system according to claim 1, wherein the external device includes a display controller, and the sub control device generates an interrupt notification signal to the main control device based on a synchronization signal from the display controller. A control system characterized by: