JP2000155342A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability and life of a display element by forming thin-film transistors(TFTs) having a resin film for planarization which extends to diodes constituting protective circuits. SOLUTION: Semiconductor regions are formed on a substrate and a gate insulating film is formed on the semiconductor regions and gate electrodes are formed thereon. Impurity regions of a P type are formed in part of the semiconductor regions and the impurity regions of an N type are formed in another part. After an insulating film is formed to cover the gate electrodes, the film is bored with holes for electrode formation and electrodes are formed. The circuits where the diodes constituting the protective circuits disposed on a periphery and the P channel type TFTs and N channel type TFTs coexist are obtained. The regions including the protective circuits on the periphery and the surfaces of the display element regions are coated and formed with the organic resin 1501 for planarization, for example, a translucent polyimide resin, by which the pixel electrodes 1503 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device in which a thin film transistor exists in a portion where a pixel exists, and the thin film transistor functions as a driving device of the pixel, and various devices using the display device of such a form. That is, the present invention provides a liquid crystal display using a nematic, cholesteric, smectic, etc. method, a projection type device (such as a liquid crystal projector) having a display device similar to the liquid crystal display, or an optical signal other than the liquid crystal. The present invention relates to a device for displaying a static or dynamic image or signal using a material whose characteristics can be controlled.

[0002]

2. Description of the Related Art The display devices listed above employ a so-called active matrix system in which a driving device such as a thin film transistor exists for each pixel and the pixels are controlled. The number of thin film transistors assigned to each pixel is one in FIG. 1, and two or more thin film transistors are used in FIGS. 2 to 4 if necessary. Further, depending on the method, one or more thin film transistors may be used for a plurality of pixels. In each case, each pixel has a plurality of signal lines arranged in the vertical and horizontal directions, an electro-optical element such as a liquid crystal element is arranged at the intersection of these, and the data transmitted by the vertical and horizontal signal lines by the thin film transistor. It controls the electro-optical element based on it.

FIG. 1 shows a circuit of one pixel in order to explain such an active matrix type circuit. A plurality of signal lines 103a to 103d extend from the data driving circuit 101 in the vertical direction. Similarly, a plurality of signal lines 104a to 104a to
d is extended. FIG. 1 illustrates a circuit for driving an electro-optical element at a portion where the signal lines 103a and 104a intersect. That is, a thin film transistor is provided in the vicinity of the intersection of both signal lines, the signal line 103a is connected to the gate electrode 105 of the thin film transistor, and the signal line 104a is connected to the drain electrode 106 of the thin film transistor.
It is connected to the. The source electrode 107 of the thin film transistor is connected to an electro-optical element 108 such as a liquid crystal. Although an N-channel thin film transistor is used in FIG. 1, a P-channel thin film transistor may be used.

FIG. 2 shows a CMOS inverter type active matrix system. Like the active matrix system of FIG. 1, a plurality of signal lines 203a to 203d extend from a vertical data drive circuit 201. Similarly, from the horizontal data drive circuit 202, a plurality of signal lines 2
04a-d extend. Unlike the case of FIG. 1, a wiring 204 ′ runs parallel to the signal line 204. Then, as in FIG. 1, two thin film transistors are used to drive the electro-optical element at the intersection of both signal lines. As shown in the figure, the thin film transistors are a P-channel transistor and an N-channel transistor, and the signal line 203a is connected to the gate electrodes 2 of both transistors.
05p and 205n. The drain electrode 206p of the P-channel thin film transistor is connected to the signal line 204a, and the drain electrode 206n of the N-channel thin film transistor is connected to the wiring 204 '.
Further, the source electrodes 207p and n of the P and N channel type thin film transistors are both connected to an electro-optical element 208 such as a liquid crystal.

FIG. 2 shows a CMOS buffer type active matrix system. Like the active matrix system of FIG. 2, a plurality of signal lines 303a to 303d extend from a vertical data drive circuit 301. Similarly, a plurality of signal lines 3 are output from the horizontal data drive circuit 302.
04a-d and wires 204'a-d are running. Then, as in FIG. 2, a P-channel transistor and an N-channel transistor
A channel type transistor is used, and a signal line 303a is used.
Are the gate electrodes 305p and 305 of both transistors.
n. Further, the drain electrode 306n of the N-channel thin film transistor is connected to the signal line 304a,
p is connected to the wiring 304 '. Further, the source electrodes 307 p and n of the P and N channel type thin film transistors are both connected to an electro-optical element 308 such as a liquid crystal.

FIG. 4 shows a CMOS transfer gate type active matrix system, similar to the active matrix system of FIG.
, A plurality of signal lines 403a to 403d extend. Similarly, a plurality of signal lines 404a to 404d extend from the horizontal data drive circuit 402. As in FIGS. 2 and 3, a P-channel transistor and an N-channel transistor are provided to drive the electro-optical element at the intersection of both signal lines.
It is connected to the source electrodes 406p and 406n of both transistors. The gate electrodes 405p and 405n of both thin film transistors are connected to a signal line 404a, and the drain electrodes 407p and n of both thin film transistors are connected to an electro-optical element 408 such as a liquid crystal.

A problem common to these circuits is that a circuit for protecting the thin film transistor when a surge (static) voltage is generated between each drive circuit and the thin film transistor is not provided. In particular, when a high voltage is applied to the gate electrode of the thin film transistor, the gate insulating film is broken and does not function as an element.

Also, when an excessive voltage is applied between the source and the drain of the thin film transistor, the voltage between the gate electrode and the channel forming region increases,
Since the gate insulating film is indirectly damaged, the thin film transistor is seriously damaged, and in some cases, is damaged. The source of such an excessive voltage is mainly due to static electricity generated for some reason.In most cases, the amount of current itself is not large.If an excessive voltage is generated, it can be quickly removed. desired.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for protecting a thin film transistor at an appropriate position by an appropriate manufacturing method, to protect the thin film transistor, and to enhance the reliability and life of the display element. I do.

[0010]

It is desirable that a protection circuit for a thin film transistor is provided around a display portion of the device, and it is also desirable that the protection circuit be manufactured at the same time when the thin film transistor of the display portion is manufactured. Further, although a normal drive voltage is passed, an excessive voltage is not passed, and it is necessary to appropriately bypass the drive voltage. The excessive voltage in a thin film transistor is generally about 10 times the threshold voltage of the gate voltage and indicates 50 V or more, but this value greatly changes depending on the structure of the thin film transistor. On the other hand, the normal driving voltage is at most several times the threshold voltage of the gate voltage, and in most cases is 10 to 40 V, but this value also varies greatly depending on the structure of the thin film transistor.

In order to satisfy the above conditions, according to the present invention, as shown in FIG. 5, a protection circuit is provided in the display element section and a driving circuit section around the display element section. As the protection circuit, for example, a circuit can be used utilizing the Zener characteristics of the diodes shown in FIGS. As a diode, besides a PN junction, which is a P-type and N-type junction,
PI, which is the junction of I-type (intrinsic) and P-type (or N-type)
A junction (NI junction) or a PIN junction that is a P-type, I-type, or N-type junction, and a PIPI junction or NINI junction or PI obtained by combining a plurality of these.
NIPIN: bonding or the like can be used. Also,
It is also possible to use a diode utilizing a Schottky junction between a semiconductor and a metal.

FIG. 8A shows an example of a protection circuit using a diode. In this example, V _DD is positive;
The voltage is 50V. Generally, a diode has a current-voltage characteristic as shown in FIG. 8B, and a current flows rapidly when a reverse voltage of a certain level or more is applied. The characteristics at this time are called Zener characteristics. The value of the threshold voltage V _th at which the current rapidly flows is, for example, 5 to 20 V. In addition, by connecting a plurality of diodes in series, it is possible to further increase the value of _Vth .

When the potential at point A in the figure is an appropriate positive value, of the diodes, D1 and D3 function as resistors close to ordinary conductors, while D2 and D4 function as extremely high resistors. . Therefore, the potential at point B is substantially the same as V _DD . Similarly, when the potential at the point A is an appropriate negative value, the potential at the point B becomes the same potential as the ground potential.

However, when an excessively large positive voltage exceeding V _th is applied, each diode functions as a low resistor. If the resistances of D1 and D2 are substantially the same and are much smaller than R1, most of the current flows in the direction of D2. The same applies when an excessive negative voltage is applied. Most of the current passes through D1, and the potential at point B is kept low. By connecting a plurality of such circuits in series, an excessive current can be more effectively prevented.

FIG. 9A shows another example using a diode. The diode shown in the figure is called a Zener diode, and has a structure in which two opposite diodes are connected. For example, a PNP (NPN)
Joining, NIN (PIP) joining, PINIP (NIPI
N) It is made by bonding or a combination of these. As shown in FIG. 9B, the characteristics of the Zener diode function as an extremely large resistance at a voltage between −V _{th and} + V _th , but when an excessive voltage exceeding the voltage is applied, the resistance value becomes Is to go down.

If the potential at point A is positive or negative below V _th , this zener diode D1 functions as a very large resistor, and the potential at point B is almost the same as the potential at point A. However, if the potential at point A is an excessively positive or negative value exceeding _Vth , D1 functions as a large resistance. If the resistance is sufficiently large compared to R1, most of the current flows through D1. And the potential at point B is kept low. By connecting a plurality of such circuits in series, an excessive voltage can be more effectively prevented.

A protection circuit having the same effect can be manufactured by using a thin film transistor. An example is shown in FIGS. FIG. 6A shows a circuit that operates only when a positive overvoltage is applied and bypasses the overvoltage. By selecting the resistors R1 and R2, the gate voltage of the N-channel thin film transistor and the voltage between the source and the drain are designed to have appropriate values. For example, assuming that R1 / R2 = 10, the potential at point A in the figure will be (based on the potential at point B).
When the voltage is +50 V, the potential of the gate can be set to +5 V. If the threshold voltage of the thin film transistor is +5 V, the thin film transistor operates,
Current flows between the source and drain. When the potential at the point A is +50 V or more, the potential of the gate electrode is +5 V or more, so that the thin film transistor operates to exhibit an effect of removing an excessive voltage. Here, if a P-channel transistor is used as the thin film transistor, it operates only when a negative excessive voltage is applied. On the other hand, when the potential at the point A is +50 V or less, the thin film transistor functions as a high resistance, and the voltage does not decrease much. Therefore, the normal signal voltage is not bypassed.

The circuit shown in FIG. 6A operates only when a positive overvoltage is applied, and does not operate when a negative overvoltage is applied. However, in practice, a positive overvoltage may be applied, or a negative overvoltage may be applied. FIG. 6 (B)
Shows a circuit for that, and eight resistors R1, R2, R
By selecting the values of 3 and R4, the source-drain voltage of the two N-channel transistors and the voltage of the gate electrode can be appropriately controlled. For example, R1 /
Assuming that R2 = 10 and R4 / R3 = 10, if the potential at point A is + 50V, the potential of the gate electrode of the thin film transistor T1 is + 5V, and the potential of T2 is + 45V.
At this time, the source / drain current flows in T1 as described above, but in T2, the potential of the channel formation region is lower than the potential of the gate electrode across the gate insulating film. , No bypass current flows.

Conversely, if the potential at point A is -50 V, T
Since the potential of the gate electrode 1 is -5 V, which is lower than the potential (0 V) of the channel formation region, no bypass current flows. However, the potential of the gate electrode of T2 is -45.
V, which is higher than the potential of the channel formation region (−50 V), so that a bypass current flows. If the potential at the point A is between −50 V and +50 V, no current flows through either of the thin film transistors, so that a normal signal current is hardly affected.

FIG. 6 (C) shows a composite of the above circuits. After the excessive voltage attenuated in the first protection circuit (upper part of the figure) passes through the resistor R5, the second protection circuit (FIG. (Bottom of the figure).

FIG. 6 relates to a protection circuit constituted by using either an N-channel type thin film transistor or a P-channel type thin film transistor. P
By using both the channel thin film transistor and the N channel thin film transistor, a protection circuit can be formed as shown in FIG. The basic operation of the protection circuit according to this method will be described with reference to FIG.

As shown in FIG. 6, an appropriate resistor R
By selecting 1, R2, the voltage between the source and the drain and the potential of the gate electrode can be set to appropriate values. For example, by setting R1 / R2 = 10, A
Assuming that the potential at the point is +50 with respect to the point B, the voltage of the gate electrode of the thin film transistor is + 5V. Then, among the thin film transistors, only T1, which is an N-channel thin film transistor, functions as a bypass.

Conversely, when the potential at point A is -50 V, the potentials of the gate electrodes of both thin film transistors are -5 V
However, at this time, only the T-channel thin film transistor T2 functions as a bypass. FIG. 7 (B)
Is a combination of the above circuits.

When such a method is adopted, the withstand voltage of the thin film transistor used in the protection circuit determines the withstand voltage of the protection circuit. In a thin film transistor, if the allowable value of the voltage between the gate electrode and the source electrode is 50 V, the above circuit can withstand a voltage up to ± 500 V and functions as a protection circuit. Of course, this value can be easily changed by selecting the value of the resistor.

Although there is no description of the resistance between the source and the drain in FIGS. 6 and 7, it is important to consider this value in determining the voltage between the source and the drain. As a value in a general thin film transistor,
For example, the channel length is 10 μm and the channel width is 10 μm
10 ⁸ to 10 ¹¹ Ω is obtained with the N-channel type thin film transistor described above. This value seems pretty large,
Using a high-resistance polycrystalline silicon having a resistivity of 10 ⁶ Ω · cm or amorphous (semi-amorphous) silicon, a linear body having a length of 10 μm, a width of 1 μm, and a thickness of 0.1 μm has a resistance of 10 ¹² Ω. The resistance of the thin film transistor is almost negligible.

As a resistor used in these protection circuits, a material mainly containing silicon may be used,
A metal material, an alloy of metal and silicon, and various compound semiconductors (for example, tin oxide, indium oxide, indium tin oxide, and the like) may be used.

Next, a method for manufacturing a protection circuit of a display device driving circuit according to the present invention will be described. A feature of the protection circuit of the present invention is that the circuit can be manufactured in parallel with the manufacture of the drive circuit (the circuit including the thin film transistor shown in FIGS. 1 to 4). .

FIG. 10 shows an example of a method for manufacturing a thin film transistor used for a driving circuit and a zener diode provided around the thin film transistor. First, a semiconductor film having a thickness of 10 nm to 10 μm, preferably 50 nm to 1 μm is provided on an appropriate substrate for mounting a display element, and this is selectively etched to form semiconductor regions 1001 and 1002. I do. The size of the semiconductor region is determined by the size of an element to be formed later. In the case of a normal thin film transistor, the length of one side is 100 nm to 100 μm.
m is used. At this time, a glass material such as quartz glass or AN glass is selected as a material of the substrate, and if necessary, a material in which another coating is formed on the substrate is used. Further, as a method of forming a semiconductor film, a low pressure CVD (LPCVD) method, a plasma CVD method, a light CV
The D method or the like is used. Further, immediately after the completion of the film formation or after another process, the semiconductor film is 400 to
At 800 ° C., preferably 500-650 ° C.
Crystallinity may be increased by heat treatment or irradiation with intense light such as a laser beam to improve characteristics as a semiconductor.

Next, films 1003 and 10 functioning as a gate insulating film are formed on the semiconductor region thus formed.
04 has a thickness of 10 nm to 1 μm, preferably 10 nm
To 200 nm. Silicon oxide,
Silicon nitride or the like is used, and its manufacturing method is LPCVD.
Method, plasma CVD method, photo CVD method, thermal oxidation (nitridation)
A method such as a light irradiation oxidation (nitriding) method and a plasma oxidation (nitridation) method is selected according to the thickness and characteristics of a target film. Finally, a thickness of 50 nm to 10 as a material of the gate electrode
A coating 1005 of μm, preferably 100 nm to 2 μm, is formed over them. Examples of the material of the gate electrode include semiconductor materials such as amorphous silicon (germanium), semi-amorphous silicon (germanium), and polycrystalline silicon (germanium); silicides such as tungsten silicide, aluminum silicide, and molybdenum silicide; and tungsten, molybdenum, and aluminum. A single layer of a metal or an alloy, or a multilayer of these materials is used. For example, thickness 1
A structure in which a tungsten layer having a thickness of 100 nm to 2 μm is provided over an amorphous silicon layer doped with phosphorus having a thickness of 0 to 100 nm is also possible. Thus, FIG. 10A is obtained.

Next, the film 1005 is selectively left on the insulating film, and regions 1006 and 1007 are formed. This region may later become a gate electrode. Further, a known impurity introduction method, for example, an ion implantation method,
Semiconductor regions 1001 and 1002 by thermal diffusion
The region selectively contains a large amount of impurities to form regions with high conductivity, so-called impurity regions 1008 to 1011. At this time, the photoresist or the like existing on or in the regions 1006 and 1007 functions as a mask for introducing impurities, so that impurities do not enter much below the regions. This is a step usually called a self-alignment step. Further, when impurities are introduced by an ion implantation method, the crystallinity of the semiconductor region is significantly impaired. Therefore, heat treatment is performed at 400 to 800 ° C., preferably 500 to 650 ° C., or
It is necessary to improve crystallinity by irradiating strong light such as laser light from the front surface or the back surface to improve characteristics as a semiconductor. Thus, FIG. 10B is obtained.

Finally, after forming an insulating film covering the regions 1006 and 1007, holes for forming electrodes are formed in the region 1007 and the impurity regions 1008 to 1011, and the electrode 1 is formed.
012 to 1016 are formed. Thus, a zener diode 1017 and an N-channel thin film transistor 1018 are manufactured. Thus, FIG.
(C) is obtained. Such a device in which a Zener diode and a thin film transistor are mixed is, for example, a device having a protection circuit shown in FIG.

Now, in FIG. 10C, the area 10
06 is not provided with an electrode.
Since the conductivity of the semiconductor region 1002 is not controlled, the element 1017 does not function as a thin film transistor; however, if an electrode is provided in a final step, the element becomes a thin film transistor. Therefore, as shown in FIG.
A large number of elements can be fabricated on a substrate, and electrodes can be provided later on these elements in the display region or peripheral region as needed, and some can be designed to function as thin film transistors and some as diodes. There is a degree.

FIG. 11 shows an example of a thin film transistor used for a driver circuit and a method of manufacturing a thin film transistor provided around the thin film transistor. First, on a substrate, a thickness of 10 nm
A semiconductor film having a thickness of 10 μm, preferably 50 nm to 1 μm is provided, and this is selectively etched to form a semiconductor region 11.
01 to 1104 are formed.

Next, a film 1105 functioning as a gate insulating film is formed on the semiconductor region thus formed. Finally, a coating 1006 serving as a material for the gate electrode is formed to cover these. Thus, FIG.
(A) is obtained.

Next, the gate electrode 1107 to 1110 is formed by selectively leaving the coating 1106 on the insulating film. Thus, FIG. 11B is obtained.

Further, semiconductor regions 1101 and 110
4 is masked by a photoresistor or the like to expose only the semiconductor regions 1102 and 1103, and form P-type impurity regions 1111 to 1114 in the semiconductor regions 1102 and 1103 in a self-aligned manner by a known impurity introduction method (FIG. 11). (C)). Further, similarly, the semiconductor regions 1102 and 1103 are similarly masked, and the semiconductor regions 1102 and 1103 are masked.
By exposing 101 and 1104 and introducing impurities, N-type impurity regions 1115 to 1118 are formed.
Thus, FIG. 11D is obtained.

Finally, after forming an insulating film covering the gate electrodes 1107 to 1110, holes for forming electrodes are formed in each of the gate electrodes and the impurity regions, and the electrodes 1119 to 1112 are formed.
8 are formed. Thus, a circuit in which a P-channel thin film transistor and an N-channel thin film transistor are mixed is manufactured. Thus, FIG. 11E is obtained. Such a circuit in which a P-channel thin film transistor and an N-channel thin film transistor are mixed is used, for example, in a device having a protection circuit shown in FIG.

FIG. 13 shows an example of a protection circuit manufactured by the above-described manufacturing method. In this manufacturing method, first, semiconductor regions 1301 and 1302 are formed, a film functioning as a gate insulating film (not shown) is formed, and then a gate electrode 1303 extending over both semiconductor regions is formed. After a P-type impurity region is formed in the semiconductor region 1301 and an N-type impurity is formed in the semiconductor region 1302, an interlayer insulating film (not shown) is further formed.
To form Then, the metal electrode 1 extending over both semiconductor regions is made of a metal material such as aluminum which is a good conductor.
304 and 1305 and the signal line 1306 are formed at the same time. After that, wirings 1307 and 1308 functioning as resistors are formed using a resistive material such as tin oxide or indium, or a high-resistance amorphous silicon or the like.
A protection circuit is formed.

FIG. 12 shows an example of a method for manufacturing a thin film transistor used for a driving circuit and a diode provided around the thin film transistor. First, a semiconductor film is provided on a substrate and selectively etched to form semiconductor regions 1201 to 12
04 is formed.

Next, a film 1205 functioning as a gate insulating film is formed on the semiconductor region thus formed. Finally, a coating 1206 serving as a material for the gate electrode is formed to cover these. Thus, FIG.
(A) is obtained.

Next, the gate electrode 1207 and 1208 are formed by selectively leaving the coating 1206 on the insulating film. Thus, FIG. 12B is obtained.

Further, semiconductor regions 1201 and 120
A portion of the semiconductor regions 1201 and 1202 are masked with a photoresist or the like, and only the other portions of the semiconductor regions 1201 and 1202 and 1203 are exposed. P-type impurity regions 1209 and 1210 are formed in the semiconductor region 1203 and P-type impurity regions 1211 and 1212 are formed in the semiconductor region 1203 in a self-aligned manner (FIG. 12).
(C)). Similarly, this time, the regions including the impurity regions of the semiconductor regions 1201 and 1202 and the entire region 1203 are masked, the other portions of the semiconductor regions 1201 and 1202 and the entire region 1204 are exposed, and impurities are introduced.
Type impurity regions 1213 to 1216 are formed. Thus, FIG. 12D is obtained.

Finally, after an insulating film is formed to cover the gate electrodes 1207 and 1208, holes for forming electrodes are formed in each of the gate electrodes and impurity regions, and the electrodes 1217 to 1124 are formed.
To form Thus, the PIN diode 122
5 and 1226, P-channel type thin film transistor 122
7. A circuit in which N-channel thin film transistors 1228 are mixed is manufactured. Thus, FIG. 12E is obtained. Such a circuit in which a diode, a P-channel thin film transistor, and an N-channel thin film transistor are mixed is used, for example, in an apparatus having a protection circuit shown in FIG. In particular, the electrode 1218 can be used as a wiring including a resistor shown in FIG. 8 by extending it.

FIG. 14 shows a method of manufacturing a device having stacked P-channel thin film transistors and N-channel thin film transistors. Using the method shown in FIGS. 10 to 12, first, semiconductor regions 1405 and 1406 each having an N-type impurity region on a substrate, and further, a gate electrode 140 provided thereon via a gate insulating film.
3 and 1404, and N-channel thin film transistors 1401 and 1402 are obtained. As described above, these elements function as diodes when the gate electrode of the thin film transistor is not electrically connected to the outside. Thus, FIG. 14A is obtained.

Next, an interlayer insulating film 1407 is formed, and a semiconductor region 1408 having a P-type impurity region thereon is formed.
409, and further, gate electrodes 1410 and 1411 provided thereover with a gate insulating film interposed therebetween to obtain P-channel thin film transistors 1412 and 1413.
Thus, FIG. 14B is obtained.

Finally, after an interlayer insulating film is entirely formed, necessary electrodes, for example, 1414 to 1423 are formed. Thus, a circuit in which a P-channel thin film transistor and an N-channel thin film transistor are mixed as shown in FIG. 14C is obtained.

[0047]

[Embodiment 1] In this embodiment, a method of manufacturing a thin film transistor will be mainly described. The manufacturing method will be described with reference to FIG. First, an inexpensive 700 such as quartz glass
On a glass substrate that can withstand heat treatment at a temperature of not higher than C, for example, about 600 ° C., a silicon oxide film as a blocking film is formed on the substrate by magnetron RF (high frequency) sputtering.
It is manufactured to a thickness of 00 to 300 nm. The process conditions are substantially 100% oxygen, an oxygen atmosphere of 99.9% or more, a film formation temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 P.
a. The deposition rate using quartz or single crystal silicon as the target was 3 to 10 nm / min.

A silicon film is formed thereon by LPCVD and spa
It was formed by a sputtering method or a plasma CVD method. LP
When formed by the CVD method, the crystallization temperature is 100 to 2
At 450-550 ° C, for example 530 ° C
Disilane (Si_TwoH₆) Or trisilane (Si_ThreeH₈)
The film was supplied to a CVD apparatus to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The deposition rate was 5 to 25 nm / min.
Was. N channel type thin film transistor and P channel type thin film
Transistor threshold voltage (V_th)
1 × 1 with borax mixed with diborane to control
0¹⁵~ 1 × 10 ¹⁸cm^-3During the film formation
Is also good.

In the case of the sputtering method, the back pressure of the sputtering was set to 1 × 10 ⁻⁵ Pa or less, and a single crystal silicon was used as a target in an atmosphere containing 20 to 80% of hydrogen mixed with argon. For example, argon 20%, hydrogen 80%
And Film formation temperature is 150 ° C, frequency is 13.56M
Hz, the sputter output was 400-800 W, and the pressure during film formation was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is set to, for example, 300 ° C., and monosilane (S
iH ₄ ) or disilane (Si ₂ H ₆ ) was used. These were introduced into a PCVD apparatus, and a high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. If the oxygen concentration is high, crystallization is difficult, and the thermal annealing temperature must be high or the thermal annealing time must be long. On the other hand, if the amount is too small, a leak occurs in which a current flows between the source and the drain due to the backlight (the light source arranged behind the display element), even though the thin film transistor is in an off state. Therefore, the concentration of oxygen is set in the range of 4 × 10 ¹⁹ to 4 × 10 ²⁰ cm ⁻³ . The concentration of hydrogen was 4 × 10 ²⁰ cm ⁻³ , which was 1 atomic% as compared with 4 × 10 ²² cm ^{−3 of} silicon. In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7
× 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, the display thin film transistor 5 × 10 oxygen by ion implantation only in a channel formation region of which constitutes the element ²⁰
You may add so that it may be set to about 5 * 10 < ²¹ > cm < ^-3 >. At this time, since light is not irradiated to the thin film transistor forming the peripheral circuit, the device can be operated at a high frequency by reducing the mixing of oxygen and obtaining a higher carrier mobility.

Next, the silicon film in an amorphous state is
After fabrication to a thickness of 00 nm, e.g.
Heat treatment at a medium temperature in a non-oxidizing atmosphere at a temperature of ~ 700 ° C for 12 to 70 hours, for example, 600
It was kept at a temperature of degree C. Since a silicon oxide film having an amorphous structure is formed on the substrate surface below the silicon film, no specific nucleus is generated by this heat treatment, and the whole is uniformly heat-annealed. That is, it has an amorphous structure during film formation,
Further, hydrogen is simply mixed.

As a result of the annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and partially exhibits a crystalline state. In particular, in a region having a relatively high order after silicon is formed, the region tends to be crystallized particularly to a crystalline state. However, since the silicon existing between these regions is bonded to each other, the silicons are pulled by each other. As a result of measurement by laser Raman spectroscopy, a peak having a lower wavenumber than the Raman peak of 521 cm ^-1 of single crystal silicon and having a center at about 515 cm ^-1 is obtained. The apparent crystal grain size thereof is 5 to 50 nm, calculated from the half width of the Raman peak, which is about the same as that of the microcrystal. A structure was formed, and a film having a semi-amorphous structure in which silicon was bonded (anchored) to each other between the clusters could be formed.

As a result, the film is substantially free of grain boundaries (GB).
Carriers can easily move from one cluster to another through the anchored locations between the clusters, thus exhibiting higher carrier mobilities than so-called GB clearly present polycrystalline silicon. That is, as the hole mobility, 10 to 200 cm
² / Vs, as electron mobility 15 to 300 cm ² / Vs
was gotten.

On the other hand, if the film is polycrystallized by annealing at a high temperature of 900 to 1200 ° C. instead of annealing at the medium temperature as described above, segregation of impurities in the film occurs due to solid phase growth from nuclei. , GB contain many impurities such as oxygen, nitrogen, and carbon, and have high mobility in the crystal.
A barrier is created at B to hinder carrier movement there, or trap carriers, resulting in a carrier mobility of less than 10 cm ² / Vs. That is, in the present embodiment, for the reason described above,
A silicon semiconductor having a semi-amorphous or semi-crystalline structure is used. Then, this semiconductor film is
Patterning using a photomask of the semiconductor region 1
101 to 1104 were formed. The size of one semiconductor region was, for example, 10 μm × 50 μm.

On this, a silicon oxide film 1105 was formed as a gate insulating film to a thickness of 50 to 200 nm, for example, 100 nm. This was produced under the same conditions as those for producing the silicon oxide film as the blocking layer. By mixing fluorine or a compound thereof (hydrogen fluoride, silicon fluoride, or the like) at the time of film formation, fluorine having a concentration of 10 ¹⁵ to 10 ¹⁹ cm ⁻³ , for example, 5 × 10 ¹⁶ cm ⁻³ is added to the film. It may be added to immobilize sodium ions and the like.

After this, phosphorus is 1 to 5 × 10 ^{21 on the} upper side.
cm.sup.- ³ silicon film or a multilayer structure film 110 of molybdenum, tungsten, molybdenum silicide, and tungsten silicide thereon.
6 was formed. This was patterned using a second photomask to form gate electrodes 1107 to 1110. At this time, the width of the gate electrode was, for example, 10 μm, and the thickness thereof was 0.5 μm in total, that is, a phosphorus-doped silicon film of 0.2 μm and a molybdenum film of 0.3 μm.

Further, a photoresist is applied to the whole,
The photoresist is patterned using the third photomask, and the semiconductor region 1 is formed when ion implantation is performed.
The semiconductor regions 1101 and 1104 are hidden so that ions are implanted only into the regions 102 and 1103, and the borrow is 1 to 5 ×
P-type impurity regions 1111 to 1114 were formed by ion implantation at a dose of 10 ¹⁵ cm ^-2 . Similarly, a photoresist is newly applied to the entire surface, the photoresist is patterned using a fourth photomask, and the semiconductor is formed so that ions are implanted only into the semiconductor regions 1101 and 1104 when the ions are implanted. Hide areas 1102 and 1103 and add phosphorus to 1-5 × 10 ¹⁵ cm
N-type impurity regions 1115 to 1118 were formed by ion implantation at a dose of ^-2 .

The introduction of these impurities was performed through a silicon oxide film. However, the silicon oxide film on the silicon may be removed using the gate electrode as a mask, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, heat annealing was performed again at 600 ° C. for 10 to 50 hours. Impurities in the source and drain regions of each thin film transistor were activated to produce P ⁺ and N ⁺ . In addition, a channel forming region is substantially formed as an intrinsic (I-type) semi-amorphous semiconductor under the gate electrode.

In this way, a P-channel type, an N-channel type, or both types of thin film transistors can be manufactured without applying a temperature at 700 ° C. or more in all the steps even though the self-aligned type is used.
Therefore, the device can be manufactured without using expensive quartz or the like as a substrate material. Therefore, for example, it can be said that the process is extremely suitable for a large-sized liquid crystal display device.

In this embodiment, the thermal annealing was performed twice during the formation of the semiconductor region (FIG. 11A) and after the ion implantation into the source and drain regions (FIG. 11D). However, the annealing before and after the formation of the semiconductor region is omitted depending on the characteristics of the thin film transistor to be sought, and the two annealings are performed once after the ion implantation process, thereby simplifying the manufacturing process and reducing the manufacturing time. Shortening may be achieved.

After that, as shown in FIG. 11E, a silicon oxide film was entirely formed by the above-mentioned sputtering method, and this was used as an interlayer insulating film. This interlayer insulating film is
In addition to silicon oxide, phosphorus glass, borogataras, phosphorus-boron glass, or the like may be used. In addition, a vapor phase growth method such as an LPCVD method, a photo CVD method, and a normal pressure CVD method was suitable for the formation method.
Materials exhibiting sufficient properties were obtained by a method utilizing liquid / solid chemical reactions. In particular, it has been found that the latter method is suitable for reducing costs and increasing the area. The thickness of the interlayer insulating film is, for example, 0.2 to 0.6 μm.
However, since this is determined by the size of the thin film transistor, it may be thicker or thinner.

Thereafter, a window for an electrode was formed in the interlayer insulating film using a fifth photomask, and aluminum was formed on the whole of the window by a sputtering method. It is also possible to use a heat-resistant metal such as chromium instead of aluminum. Then, aluminum was patterned using a sixth photomask to form electrodes / leads 1119 to 1128. Thus, FIG.
(E) was obtained. At this time, although not shown in FIG. 11, a signal line connecting the driver circuit and the thin film transistor can be formed at the same time.

Further, the resistivity is further set to 10 ² to 10 ¹²
An amorphous silicon film of Ωcm, preferably 10 ⁴ to 10 ⁸ Ωcm, was formed with a thickness of, for example, 30 to 200 nm. Then, patterning is performed using a seventh photomask, and wirings 1307 and 13 functioning as resistors are formed.
08 was formed. In FIG. 13, a hatched portion indicates that there is a contact between wirings. FIG. 15 shows a cross section of the device manufactured by the above steps. FIG.
15A, reference numeral 1502 denotes a resistance wiring formed of the above amorphous silicon.

Then, the surface is flattened with an organic resin 150.
1. For example, a transparent polyimide resin is applied and formed, an electrode hole is formed in a necessary portion of a display element region by an eighth photomask, and a transparent conductive material film such as tin oxide or indium oxide is further formed. , Nickel oxide, zinc oxide, or alloys / compounds thereof, for example, a film of indium tin oxide (ITO) was formed by a sputtering method. This was patterned by a laser scribe (laser etching) method without using a photomask, for example. Of course, it is also possible to perform patterning using a mask as usual, but especially when the area of the display device is large, advanced mask alignment is required, and an increase in the number of times of alignment of the mask is a yield. It is desirable to avoid it if possible because it leads to a decrease in Mask alignment is not required in the laser scribe method, and the patterning of the transparent conductive film is at least 10 times as large as the minimum pattern width of 0.3 μm possible by the laser scribe method. This is the ideal method for patterning. By patterning in this manner, the pixel electrode 150
3 was formed.

Then, this ITO was formed at a temperature of room temperature to 150 ° C., and annealed in oxygen at 200 to 400 ° C. or in the air.

Thereafter, the display device was manufactured through various steps necessary for manufacturing a display device, for example, a liquid crystal display device, for example, formation of a counter electrode, and liquid crystal injection for a liquid crystal display device. The details are not described because they are not directly related to the present invention.

[Embodiment 2] FIG. 11 (E) was obtained in the same manner as in Embodiment 1. After that, as shown in FIG. 15B, a flattening organic resin 1504, for example, a light-transmitting polyimide resin is applied to the surface, and a peripheral region including a protection circuit and a necessary portion of a display element region are formed. The electrode hole is formed by the photomask of No. 8, and a film of a transparent conductive material, for example, tin oxide, indium oxide, nickel oxide, zinc oxide, or an alloy or compound thereof,
For example, a film of indium tin oxide (ITO) was formed by a sputtering method. This was patterned using a ninth photomask. Then, in the display element region, the pixel electrode 1505 was formed, and in the peripheral region, a wiring functioning as a resistor (corresponding to 1307 and 1308 in FIG. 13) was formed.

The ITO was formed at a temperature of room temperature to 150 ° C., and annealed in oxygen at 200 to 400 ° C. or in the air.

After that, the display device was manufactured through various steps necessary for manufacturing a display device, for example, a liquid crystal display device, for example, formation of a counter electrode, and liquid crystal injection for a liquid crystal display device. The details are not described because they are not directly related to the present invention.

[0072]

According to the present invention, there is provided a display device using a liquid crystal, a ferroelectric, or another material having an electro-optical effect, in which a display element is driven by a method using a thin film transistor. Can be protected from surge voltage,
The reliability, durability, and life of the display device can be improved.

[Brief description of the drawings]

FIG. 1 illustrates an example of a structure of a display element portion.

FIG. 2 illustrates an example of a structure of a display element portion.

FIG. 3 illustrates an example of a structure of a display element portion.

FIG. 4 illustrates an example of a structure of a display element portion.

FIG. 5 shows an application example of the protection circuit of the present invention.

FIG. 6 shows an example of a protection circuit of the present invention.

FIG. 7 shows an example of a protection circuit of the present invention.

FIG. 8 shows an example of a protection circuit of the present invention.

FIG. 9 shows an example of a protection circuit of the present invention.

FIG. 10 illustrates a method for manufacturing a protection circuit of the present invention.

FIG. 11 illustrates a method for manufacturing a protection circuit of the present invention.

FIG. 12 illustrates a method for manufacturing a protection circuit of the present invention.

FIG. 13 shows an example of a protection circuit of the present invention.

FIG. 14 illustrates a method for manufacturing a protection circuit of the present invention.

FIG. 15 shows an example of a protection circuit of the present invention.

[Explanation of symbols]

1301 ... Semiconductor region including N-type impurity region 1302 ... Semiconductor region including P-type impurity region 1303 ... Gate electrode 1304 ... Metal electrode and lead 1305 connecting between impurity regions Metal electrodes and leads for connecting between impurity regions 1306: signal lines 1307, 1308: wiring functioning as resistors

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 612B 619A 623Z (72) Inventor Yasuhiko Takemura 398, Hase, Atsugi-shi, Kanagawa KK Semiconductor Energy Laboratory

Claims (8)

[Claims] 1. A display device comprising: a peripheral region having a P-channel thin film transistor and an N-channel thin film transistor; and a protection circuit having a diode, wherein the P-channel thin film transistor and the N-channel thin film transistor are a semiconductor film; A gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; a planarizing resin film on the peripheral region; the planarizing resin film extending to the diode A display device characterized by the above-mentioned. 2. A display device comprising: a peripheral region having a P-channel thin film transistor and an N-channel thin film transistor; and a protection circuit having a diode, wherein the P-channel thin film transistor and the N-channel thin film transistor have a source region and a drain region. A semiconductor film having a semiconductor film having a channel region; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; a planarizing resin film on the peripheral region; The resin film extends to the diode, and the source region and the drain region have an oxygen concentration of 1 × 10
A display device having a size of ¹⁹ cm ^-3 or less. 3. A display device comprising: a peripheral region having a P-channel thin film transistor and an N-channel thin film transistor; and a protection circuit having a diode, wherein the P-channel thin film transistor and the N-channel thin film transistor have a source region and a drain region. A semiconductor film having a semiconductor film having a channel region; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; a planarizing resin film on the peripheral region; A display device, wherein a resin film extends over the diode, and an oxygen concentration in the channel formation region is 5 × 10 ²¹ cm ⁻³ or less. 4. The display device according to claim 1, wherein the gate insulating film is a silicon oxide film containing fluorine. 5. The display device according to claim 1, wherein the gate electrode is a silicon film. 6. The display device according to claim 1, wherein the gate electrode is a multilayer structure film of molybdenum, tungsten, molybdenum silicide, and tungsten silicide on a silicon film. 7. The display device according to claim 1, wherein the diode is a PIN diode. 8. The display device according to claim 1, wherein the flattening organic resin film is a light-transmitting polyimide film.