JP2000151747A - Data processing circuit, data transmission system and method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing circuit which can correctly receive data through a data transmission line. SOLUTION: In an MD device 2, adaptive transform acoustic coding(ATRAC) data read from a mini disk(MD) 3 are transmitted to a link/layer circuit 12 through an IEEE 1394 serial bus BUS and, in the link/layer circuit 12, continuity of the received ATRAC data is monitored. When there is an omission, an omission data demand signal for specifying omitted data is transmitted to a host computer 6 from a host computer 16. Thus, these omitted ATRAC data are read from the MD 3 again and transmitted to the link/layer circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a data processing circuit,
The present invention relates to a data transmission system and a data transmission method.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Electronics and Information Technology) has realized high-speed data transfer and real-time transfer.
Electrical and Electronic Engineers) The 1394 serial interface has been standardized. Such an IEEE
The data processing circuit of the E1394 serial interface mainly includes a physical layer circuit that directly drives the IEEE 1394 serial bus and a link layer circuit that controls data transfer of the physical layer, and a physical layer circuit of a plurality of data processing circuits. The circuits are connected via an IEEE 1394 serial bus, and one or more applications are connected to the link layer circuit of each data processing circuit.

Further, in a system using the above-mentioned IEEE 1394 serial interface, an application connected to one data processing circuit and an application connected to another data processing circuit are connected to each other by the IEEE 1394 standard.
Asynchronous transfer that transmits a signal when a reception permission signal is received via the 394 serial bus, and transmits a reception confirmation signal when a signal is received, or in an isocycle. One
An isochronous transfer in which data is always transmitted and received is performed once every 25 μs.

[0004]

By the way, the above-mentioned I
In a system using the IEEE 1394 serial bus BUS, an MD (Mini Di
sk) The MD data read from the MD by the device is transferred to the IEEE
There is a case in which it is desired to write data to an MD using an MD device connected to another data processing device via a 1394 serial bus. Here, in MD, ATRAC (Adaptive TRansform Acoustic Cod
ing). This ATRA
In C, compression is performed in units of 212 bytes of sampling data. For example, when a plurality of packets including 159 bytes of ATRAC data are continuously transmitted in isochronous transfer, if some packets are lost. ATRAC containing the lost packet
In addition to the data, ATRAC data before and after being integrally compressed with the ATRAC data cannot be decompressed, and there is a problem that the quality of data obtained on the receiving side becomes very low. Therefore, conventionally, ATRAC data has not been transmitted via the IEEE 1394 serial bus.

[0005] The above-mentioned problem is caused by IEEE 1394.
In addition to the case where ATRAC data is transmitted via a serial bus, the case where various data is transmitted / received via various data transmission paths similarly exists.

An object of the present invention is to provide a data processing circuit capable of receiving data accurately via a data transmission path. It is another object of the present invention to provide a data transmission system and a data transmission method capable of accurately transmitting and receiving data via a data transmission path.

[0007]

In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, a data processing circuit according to the present invention comprises a receiving circuit for receiving data via a data transmission line. A continuity detection circuit that monitors the continuity of the received data and detects missing data;
A transmission circuit for transmitting a missing data request signal for requesting the transmitting side for the detected missing data.

In the data processing circuit of the present invention, the data transmitted via the data transmission path is received by the receiving circuit.
Next, in the continuity detecting circuit, the continuity of the received data is monitored, and missing data is detected.
Next, a missing data request signal for requesting the detected missing data is transmitted from the transmitting circuit to the transmitting side. Then, on the transmitting side, the data requested by the received missing data request signal is transmitted to the data processing circuit via the data transmission path. According to the data processing circuit of the present invention, missing data can be received, and processing can be performed using the received continuous data.

In the data processing circuit of the present invention, preferably, the data includes order instruction data indicating an order of data, and the continuity detecting circuit preferably includes Based on the order instruction data,
The missing data is detected.

In the data processing circuit according to the present invention, preferably, the receiving circuit receives the data via the data transmission path when the continuity detecting circuit detects the missing data. To stop.

In the data processing circuit according to the present invention, preferably, the receiving circuit receives a plurality of packets each including a predetermined amount of the data.

Further, a data transmission system according to the present invention is a data transmission system in which a data transmission device, a data reception device, and a data transmission device are connected via a data transmission line. Sending data to the data receiving device, when receiving a missing data request signal from the data receiving device, transmits data specified by the missing data request signal, the data receiving device, via the data transmission path, A receiving circuit for receiving data, a continuity detecting circuit for monitoring continuity of the received data and detecting missing data, and transmitting the missing data request signal for requesting the detected missing data to the data And a transmission circuit for transmitting to the transmission device.

In the data transmission system according to the present invention, data is transmitted from the data transmission device to the data reception device via the data transmission path. And in the data receiving device,
The data transmitted via the data transmission path is received by the receiving circuit. Then, in the continuity detecting circuit, the continuity of the received data is monitored, and missing data is detected. Next, a missing data request signal for requesting the detected missing data is transmitted from the transmitting circuit to the data transmitting device. Then, in the data transmitting device, data requested by the received missing data request signal is transmitted to the data receiving device again via the data transmission path. According to the data transmission system of the present invention, since the missing data is transmitted from the data transmitting device to the data receiving device, the data receiving device can perform processing using the received continuous data.

A data transmission method according to the present invention is a data transmission method for transmitting and receiving data via a data transmission path, wherein data is transmitted from a transmission side to a reception side via the data transmission path, and On the side, the continuity of the data received via the data transmission path is monitored to detect missing data, and a missing data request signal for requesting the detected missing data is transmitted from the receiving side to the transmitting side. And transmitting the data specified by the missing data request signal to the receiving side when the transmitting side receives the missing data request signal.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a communication system 1 according to the present invention using an IEEE 1394 serial interface.
FIG. 2 is a block diagram showing an embodiment of the present invention. In the communication system 1, the MD device 2 is connected to the link layer circuit 9 as an application.
The MD read block 4 is driven by the DSP 5, and ATRAC data is read from the MD 3. Then, the ATRAC data read from the MD3 is transmitted in packet units to the link layer circuit 9, the physical layer circuit 10, the IEEE1394 serial bus BUS, the physical layer circuit 11, and the link layer circuit 1.
2 to the MD device 20. And MD
In the device 20, the MD write block 14 is driven by the DSP 23, and ATRAC data is recorded on the MD 13. In the present embodiment, the link layer circuit 12
In, the continuity of the received ATRAC data is monitored in packet units, and when it is determined that there is no continuity,
An instruction is transmitted from the host computer 16 to the host computer 6 requesting that ATRAC data subsequent to the ATRAC data having lost continuity be transmitted again.
Thereby, ATRAC data after the ATRAC data whose continuity has been lost is read out again from the MD device 2 and transmitted to the MD device 20 in packet units via the IEEE 1394 serial bus BUS.

Hereinafter, the configuration of the communication system 1 will be described. As shown in FIG. 1, the communication system 1 includes, for example,
One side of the IEEE 1394 serial bus BUS
D device 2, a host computer 6, a link layer circuit 9 and a physical layer circuit 10, and a physical layer 11 and a link layer circuit 1 on the other side.
2. It has a host computer 16 and an MD device 20. In this embodiment, the link layer circuit 12 corresponds to the receiving circuit and the continuity detecting circuit of the present invention, and the host computer 16 corresponds to the transmitting circuit of the present invention.

Hereinafter, each component will be described in detail. MD device 2 The MD device 2 includes an MD read block 4 and a DSP 5
And outputs the ATRAC data S5 read from the MD3 to the link layer circuit 9. The DSP 5 controls the MD read block 4 based on a control signal S6 from the host computer 6, and reads the AT read from the MD3.
The RAC data S5 is output to the link layer circuit 9.
Here, ATRAC data S5 is audio data compressed by the ATRAC method in units of 212 bytes,
Video data data and computer data. The MD reading block 4 has a driving mechanism for rotatingly driving the MD 3 and a reading system such as an optical pickup, and reads the MD 3 under the control of the DSP 5.

Host Computer 6 The host computer 6 outputs a control signal S6 to the DSP 5. Further, the host computer 6 inputs a received packet for asynchronous communication from the host interface circuit 102 of the link layer circuit 9 as required, performs predetermined processing, and sends a received packet for asynchronous communication to the host interface circuit 102. Is output.

The host computer 6 transmits the asynchronous communication packet (the missing data request signal of the present invention) including the order indication data present-PES-number and PES-data-counter to the link layer circuit 12 and the physical Layer circuit 11, IEEE 1394 serial bus BU
S, when received from the host computer 16 via the physical layer circuit 10 and the link layer circuit 9, the order indication data pr included in the received packet
The control signal S6 is output to the DSP 5 so that the ATRAC data S5 specified by the esent-PES-number and the PES-data-counter is read again from the MD3. In particular,
Order indication data presen included in the received packet
A transport stream (TS) described later having a t-PES-number and order indication data PES-data-counter obtained by incrementing (increasing) the order indication data PES-data-counter included in the received packet by one. A control signal S6 indicating that the ATRAC data arranged in the packet is read from the MD3 again is output to the DSP5. Note that the host computer 6 receives the asynchronous communication packet including the order indication data present-PES-number and the PES-data-counter as described above, because the link layer circuit 12 on the receiving side will be described later. In the application I / F circuit 103, the order instruction data presen included in the received packet for isochronous communication
This is a case where discontinuity of t-PES-number and PES-data-counter is detected.

Link Layer Circuit 9 The link layer circuit 9 controls the isochronous transfer and the asynchronous transfer, and controls the physical layer circuit 10 under the control of the host computer 6. Here, in the isochronous transfer, data is always transmitted and received once every 125 μs, which is an isocycle,
In asynchronous transfer, a signal is transmitted from the transmitting side to the receiving side when the transmitting side receives a reception permission signal that permits the signal to be received, and when the receiving side receives the signal, the receiving side sends a reception confirmation signal to the transmitting side. Send. FIG. 2 is an internal configuration diagram of the link layer circuit 9. Specifically, as shown in FIG. 2, the link layer circuit 9 includes, for example, a link core (Link Core) 101 and a host I / F (Host Interface).
rface) circuit 102, application I / F circuit 10
3. Transmission FIFO (AT-FIFO) 104a and reception F
Asynchronous communication FIFO 104 consisting of IFO (AR-FIFO) 104b, resolver for self-ID (Resolver) 1
05, Transmission preprocessing circuit for isochronous communication (TXOPRE) 1
06, isochronous communication post-processing circuit (TXOPRO) 1
07, reception preprocessing circuit for isochronous communication (TXIPRE) 1
08, reception processing circuit for isochronous communication (TXIPRO) 1
09, an isochronous communication FIFO (I-FIFO) 110 and a configuration register (Configuration
Register, hereinafter referred to as CFR) 111.

In the link layer circuit 9 shown in FIG. 2, the application interface circuit 103, the pre-transmission processing circuit 106, the post-transmission processing circuit 107, the pre-reception processing circuit 108, the post-reception processing circuit 109, the FIFO 110,
The link core 101 and the CFR 111 constitute an isochronous communication system circuit. Further, the host interface circuit 102 includes a transmission FIFO for asynchronous communication.
104a, receiving FIFO 104b, link core 101
And the CFR 111 constitute an asynchronous communication system circuit.

[Isochronous communication system circuit] The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, and an interface circuit for these packets with a physical layer circuit 10 which directly drives the IEEE1394 serial bus BUS. , A cycle timer reset every 125 μs, a cycle monitor, and a CRC circuit. The link core 101 outputs an isochronous transmission packet to the physical layer circuit 10 every 125 μs at the time of transmission of the isochronous transfer. Further, the link core 101 receives the 12
An isochronous transmission packet is input from the physical layer circuit 10 every 5 μs.

At the time of transmission, the application I / F circuit 103 converts the ATRAC data S5 input from the DSP 5 into a 188-byte transport stream (TS: T
(Transport Stream) packets are sequentially generated, and the TS packets are output to the pre-transmission processing circuit 106. ATRAC data of 159 bytes is arranged in the payload part (data part) of each TS packet. At this time, since the ATRAC data is compressed in units of 212 bytes as described above, the ATRAC data included in the same compression unit is used.
At least a part of the AC data is arranged in a different TS packet. Here, a so-called PES (Packetized Elementary Stream) packet is configured by 159-byte ATRAC data included in eight consecutive TS packets. A PES packet is an MPEG (M
oving Picture coding Experts Group) 2 and the like, a TS packet used for transmission (storage) in an environment where a bit error occurs, and a program stream (PS) used for transmission (storage) in an environment where a bit error does not occur. : Program Stream) This is an intermediate stream for enabling conversion between packets.

Hereinafter, the data format of the TS packet will be described. FIG. 3 is a diagram for explaining the format of a TS packet. As shown in FIG.
The packet is, for example, a 4-byte transport packet header TPH, a 14-byte PES packet header PPH, a 2-byte data header DH and a 16-byte data header DH.
It consists of an 8-byte data body DB.

Transport packet header TPH
For example, as shown in FIG. 3, the synchronization byte (0x4
Sync-byte indicating 7), transport-erro indicating error indication
r-indicator, playload-unit- indicating unit start display
start-indicator, transport-priority indicating the priority of the transport packet, PID indicating the packet identifier
, Transport-scrambling-co for scrambling control
ntrol, adapt on adaptation field control
ation-field-control and con to indicate continuity
It consists of tinuity-counter.

The PES packet header PPH is
For example, it includes data indicating the length of the PES packet, whether or not copying of the PES packet is possible, and the identification of the original / copy.

The data header DH is, for example, a data-type indicating whether the data is audio data or not, and a data-transmi indicating whether the data communication path is a satellite or a cable.
Consists of ssion and tag. In this embodiment, data-typ
e indicates music data.

As shown in FIG. 4, for example, the data body DB includes an FDF-field-length indicating the data length (number of bytes) of an FDF (Fromat Dependent Field), and an audio-data-type- indicating the audio data type. 1, audio-data-type-2 indicating the classification within the audio data type, copyright indicating whether the music data can be copied, stereo-mono indicating whether the music is stereo or monaural, emphasis applied to the music Emphasis, indicating whether or not
Data-start-indicator indicating that the data being transmitted is the first PES packet of the music data, data-end-indicator indicating that the data being transmitted is the last PES packet of the music data, Packet is PE
Order indication data PES-data-conuter, which is a 3-bit cyclic count value indicating the order of the eight TS packets transmitting S, and the order of the PES packet related to the TS packet. Order indication data present-PES-nu, which is a 24-bit count value indicating
mber. In the present embodiment, the data audio-da
ta-type-1 indicates that it is ATRAC. In addition, the order instruction data PES-data-conuter and present-PES-number are used by the application I / F circuit 103 to receive the received ATRAC
Used to monitor data continuity.

The application I / F circuit 103
At the time of reception, each T input from the post-reception processing circuit 109
From the S packet, the ATRAC of 159 bytes shown in FIG.
The data is extracted and the ATRAC data is output to the application side. Application I / F circuit 103
Will be described in the description of the link layer circuit 12 described later.

The application I / F circuit 103
In addition to MD devices, for example, CD (Compact Disc)
Multimedia devices such as players, D / A converters, various computers, consumer products such as set top boxes, and data storage devices such as hard disks can be connected.

The pre-transmission processing circuit 106 receives a TS packet from the application I / F circuit 103, and adjusts the data length of the TS packet in quadlet (4 byte) units in order to perform the IEEE 1394 standard isochronous communication. , FIFO 11 for transmission of FIFO 110
Write to 0b.

The post-transmission processing circuit 107 includes a FIFO 110
A TS packet is read from the transmission FIFO 110b, and a 1394 header and a CIP header (Header) 1 and 2 shown in FIG. 5 are added to the read TS packet to generate a transmission packet for isochronous communication. The transmission packet is output to the transmission circuit of the link core 101. Specifically, as shown in FIG. 5, a transmission packet for isochronous communication includes a 32-byte 1394 header and a 32-byte header CRC (Cyclic Redundancy C
heck), 32-byte CIP header 1, 32-byte C
The IP header 2 consists of 188 bytes of data and 32 bytes of data CRC. Here, the TS packet shown in FIG. 3 is arranged in 188-byte data.

The 1394 header is data-l representing the data length.
channel, reserved, indicating ength, tag, the number of the channel to which the packet is transferred (any of 0 to 63)
It consists of a speed indicating the transfer speed and a synchronization code sy defined by each application. Also, CIP header 1
Is the SID (Source node ID) for the sending node number,
DBS (Data Block Siz) for data block length
e) FN for the number of data divisions in packetization
(Fraction Number), QPC (Quadlet Padding Count) for the number of quadlets of padding data, SPH for a flag indicating the presence or absence of a source packet header, and D for a counter for detecting the number of isochronous packets.
Has BC. Also, the CIP header 2 has an FDF (Format Depepe) used corresponding to the FMT and signal format.
Syn for ndent Field) and timestamp information
has cTime.

The pre-reception processing circuit 108
1 received via the IEEE 1394 serial bus BUS via the IEEE 1394 serial bus, the 1394 header of the received packet, C
After analyzing the contents of the IP headers 1 and 2, etc., the 188-byte data (TS packet)
Write to IFO 110a.

The post-reception processing circuit 109 includes a reception FIFO.
The TS packet read from 110a is output to the application I / F circuit 103. At this time, if the TS packet is encrypted, the post-reception processing circuit 109 decrypts the TS packet,
Output to the circuit 103.

The FIFO 110 is, for example, 960 × 32
It comprises a FIFO 110a for receiving bits and a FIFO 110b for transmitting 960 × 32 bits.

[Asynchronous Circuit] Link Core 101
Transmits / receives a packet for asynchronous communication while transmitting / receiving a reception permission signal and a reception acknowledgment signal to / from a destination when performing asynchronous transmission via the IEEE 1394 serial bus BUS, as described above. .

The host interface circuit 102 arbitrates the writing and reading of asynchronous communication packets between the host computer 6 and the transmission FIFO 104 a and the reception FIFO 104 b, and transfers various data from the host computer 6 to the CFR 111. Arbitrate transmission and reception.

The transmission FIFO 104a has IEEE1
A transmission packet for asynchronous communication to be transmitted to the 394 serial bus BUS is stored in the reception FIFO 10.
4b stores a received packet for asynchronous communication transmitted through the IEEE 1394 serial interface bus BUS.

When the bus is reset, the resolver 105
The contents of the self-ID packet transmitted through the EE1394 serial interface bus BSU are analyzed, and the CFR is analyzed.
111.

Physical Layer Circuit 10 The physical layer circuit 10 arbitrates the IEEE 1394 serial bus BUS. Also, the physical layer circuit 10 encodes the transmission packet input from the link layer circuit 9 and
Output to the 94 serial bus BUS. In addition, the physical layer circuit 10 has an IEEE 1394 serial bus B
Decodes received packets input from the US and links
Output to the layer circuit 9.

Physical Layer Circuit 11 The physical layer circuit 11 is connected to the physical layer circuit 10 via the IEEE 1394 serial bus BUS, and has the same configuration and functions as the above-described physical layer circuit 10.

Link Layer Circuit 12 As shown in FIG. 6, the link layer circuit 12 is the same as the link layer circuit 9 shown in FIG. 2 except for the application connected to the application I / F circuit 103. It has a configuration. That is, in the link layer circuit 12, the application I / F circuit 103 is connected to the MD device 20 that writes ATRAC data to the MD 13 as an application.

The processing at the time of reception in the application I / F circuit 103 of the link layer circuit 12 will be described below. The processing at the time of reception can be performed in the application I / F circuit 103 of the link layer circuit 9 shown in FIG. The application I / F circuit 103 analyzes the transport packet header TPH, PES packet header PPH, data header DH, and FDF shown in FIG. 4 of the TS packet shown in FIG. . Then, the application I / F circuit 103 extracts the 159-byte ATRAC data S12 included in the TS packet shown in FIGS. 3 and 4 input from the post-reception processing circuit 109, and outputs this to the DSP 23.

At this time, in the present embodiment, the application I / F circuit 103 uses the configuration shown in FIG. 7 and uses the arrangement instruction data PES-data-conuter and present-data shown in FIG. The PES-number is monitored to detect the continuity of the received TS packet, that is, whether there is a missing TS packet.

The application I / F circuit 103 includes, for example, as shown in FIG.
1 and a CFR writing circuit 202. The continuity detection circuit 200 receives the T
The 3-bit order instruction data PES-data-conuter shown in FIG. 4 included in the S packet is input, and the input order instruction data PES-data-conuter and the previously input order instruction data PES-data-conuter are input. It is determined whether or not there is continuity between them, and the continuity detection signal S200 indicating the result of the determination and the order input data PES-data-conuter input this time are CFR
Output to the writing circuit 202. Order instruction data PES-da
ta-conuter, when there is continuity, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1,. . . Are input to the continuity detection circuit 200 in this order.

The continuity detecting circuit 201 receives the 24-bit order instruction data present-PES-number shown in FIG. 4 included in the TS packet input from the post-reception processing circuit 109, and receives the input order instruction data present-PES-number. It is determined whether or not the PES-number has continuity. The continuity detection signal S200 indicating the result of the determination and the order input data pr input this time are determined.
esent-PES-number is output to the CFR writing circuit 202. Specifically, the continuity detection circuit 201 outputs the order indication data pres for each of eight consecutively input TS packets.
It is determined whether the ent-PES-number has been incremented (increased) by one. That is, eight consecutively input T
Order indication data present-PES-numb included in S packet
er indicates the same value, and the order indication data present-
A value obtained by incrementing the value of the PES-number by 1 and the data indicating the order of eight TS packets that have been successively input.
It is determined whether the present-PES-number indicates.

The CFR writing circuit 202 includes the continuity detection signal S200 and the order instruction data PES-data-conuter input from the continuity detection circuit 200, and the continuity detection circuit 2
If at least one of the continuity detection signals S200 and S201 indicates that there is no continuity based on the continuity detection signal S201 and the order instruction data present-PES-number input from 01, The order instruction data PES-data-conuter and present-PES-number input and stored when it is determined that there is continuity are CF
Write to R111.

[0049] The host computer 16 host computer 16, as described above, the link
The discontinuity of the present-PES-number and the PES-data-counter included in the received packet for the isochronous communication is detected by the application I / F circuit 103 of the layer circuit 12, and the received packet is finally received with continuity. When the present-PES-number and the PES-data-counter of the received packet are written to the CFR 111, an interrupt signal is input from the host interface circuit 102 by the writing, and the present-PES-numb read from the CFR 111 is input.
The transmission packet for asynchronous communication including the er and the PES-data-counter is output to the link layer circuit 12.
The transmission packet is output to the host computer 6 via the link layer circuit 12, the physical layer circuit 11, the IEEE 1394 serial bus BUS, the physical layer circuit 10, and the link layer circuit 9. Further, the host computer 16 outputs a control signal S16 to the DSP 23.

MD Device 20 The MD device 20 includes the MD writing block 14 and the DS
A having P23 and input from the link layer circuit 12
Write the TRAC data S12 to the MD13. DSP5
Controls the MD writing block 14 based on a control signal S16 from the host computer 16,
The ATRAC data S12 input from the layer circuit 12 is written to the MD 13. The MD writing block 14
It has a drive mechanism for rotating and driving D3 and a readout system such as an optical pickup.

Hereinafter, the operation of the communication system 1 shown in FIG. 1 will be described. FIG. 8 is a flowchart for explaining the operation of the communication system 1 shown in FIG. Step S1 First, the user operates an operation unit (not shown) to
When the D read instruction is issued, a control signal S6 is output from the host computer 6 to the DSP 5, and the MD read block 4 controls the MD 3 according to the control from the DSP 5.
From the ATRAC data S5. The read ATRAC data S5 is output to the application I / F circuit 103 of the link layer circuit 9 shown in FIG.

Next, in the application I / F circuit 103 of the link layer circuit 9, the TS packets shown in FIGS. 3 and 4 including the ATRAC data S5 read from the MD 3 are generated, and the TS packets are transmitted. After the data length is adjusted in units of 4 bytes in the pre-processing circuit 106, the transmission FIFO 110 of the FIFO 110
b. Then, in the post-transmission processing circuit 107, as shown in FIG. 5, a 1394 header, a CIP
Headers 1 and 2 are added, and a transmission packet for isochronous communication is generated. Then, the transmission packet is output to the link core 101, and every 125 μs, the physical layer circuit 10 shown in FIG.
The data is isochronously transferred to the link layer circuit 12 via the 1394 serial bus BUS and the physical layer circuit 11.

Step S2 The transmission packet from the link layer circuit 9 is input to the reception preprocessing circuit 108 as a reception packet via the link core 101 of the link layer circuit 12 shown in FIG.
In the reception pre-processing circuit 108, one of the received packets
After the contents of the 394 header, the CIP headers 1, 2 and the like are analyzed, the 188-byte TS included in the received packet is analyzed.
The packet is written to the receiving FIFO 110a. Then, the TS packet is read from the reception FIFO 110 a and output to the application I / F circuit 103 via the post-reception processing circuit 109.

Then, in the application I / F circuit 103 of the link layer circuit 12 shown in FIG.
The order indication data PES-data shown in FIG. 4 included in the packet
It is determined whether or not -conuter and present-PES-number have continuity. If it is determined that there is no continuity, the process of step S3 is performed. If it is determined that there is continuity, step S3 is performed. The process of S1 is repeated.

In step S3, the application I / F circuit 103 determines in step S2 the order instruction data PES-da included in the TS packet.
When it is determined that the ta-conuter and the present-PES-number do not have continuity, the link core 1 is transmitted via the CFR 111.
01, an interrupt signal is output, and reception of a packet for isochronous communication via the IEEE 1394 serial bus BUS is stopped. Step S4 Next, the CFR writing circuit 202 of the application I / F circuit 103 shown in FIG.
data-conuter and present-PES-number are converted to CFR111
Write to. And the order instruction data PES-data-conuter
When the present-PES-number is written into the CFR 111, an interrupt signal is output from the host interface circuit 102 to the host computer 16.

Step S5 When the host computer 16 receives the interrupt signal from the host interface circuit 102, the host computer 16 receives the order instruction data PES-data-conuter and present-PES-
number, and reads the read order instruction data PES-
A transmission packet for asynchronous communication including the data-conuter and the present-PES-number is output to the host interface circuit 102. The transmission packet for the asynchronous communication is transmitted to the host interface circuit 10 shown in FIG.
After being stored in the transmission FIFO 104a through the link core 101, the link core 101 and the physical layer circuit 1 shown in FIG.
1. Asynchronously transmitted to the link layer circuit 9 via the IEEE 1394 serial bus BUS and the physical layer circuit 10.

Step S6 The transmission packet for the asynchronous communication is stored in the reception FIFO 104b as a reception packet via the resolver 105 in the link layer circuit 9 shown in FIG.
2 to the host computer 6. Then, in the host computer 6, the order instruction data PES-data-conuter and pres
The control signal S6 is output to the DSP 5 so that the ATRAC data subsequent to the ATRAC data specified by the ent-PES-number is read again from the MD3. And M
The ATRAC data S5 read from D3 goes through the same process as in step S1 described above, and the link layer circuit 9, the physical layer circuit 10, the IEEE
The data is transmitted to the MD device 20 via the E1394 serial bus BUS and the link layer circuit 12.

As described above, according to the communication system 1, the IEEE 1394 is transmitted from the MD device 2 to the MD device 20.
When transmitting a packet for isochronous communication including ATRAC data via the serial bus BUS, the ATR included in the received packet for isochronous communication is transmitted.
The link layer circuit 12 detects the continuity of the AC data, transmits a packet for asynchronous communication specifying the missing ATRAC data to the host computer 6, and transmits the packet for isochronous communication including ATRAC data after the missing ATRAC data. The packet is transmitted from the link layer circuit 9 to the link layer circuit 12 again. Therefore, according to the communication system 1, the MD device 20
, All ATRAs read from the MD device 2
The C data can be accurately written to the MD 13. As a result, when the ATRAC data written in the MD 13 is decompressed and reproduced, the ATRAC data can be decompressed accurately. That is, according to the communication system 1, the AT via the IEEE 1394 serial bus BUS
The transmission quality of RAC data can be improved, and ATRAC data can be substantially transmitted via the IEEE 1394 serial bus BUS.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the order indication data PES-data-conuter and the present-
Although the ATRAC data continuity is detected using the PES-number, one type of order indication data indicating the ATRAC data continuity may be used.

Further, in the above-described embodiment, the case where the packet including the ATRAC data is transmitted by the isochronous communication and the missing data request is transmitted by the asynchronous communication has been described as an example. Is not particularly limited.

Further, in the above-described embodiment, the MD device 2 and the MD device 20 are used as applications in the link layer circuit 9 and the link layer circuit 12, respectively.
Are illustrated, but the type and number of applications connected to these are arbitrary.

[0062]

As described above, according to the data processing circuit of the present invention, even if the received data is missing, by transmitting the missing data request signal to the transmitting side, the missing data is transmitted from the transmitting side. Data can be received again, and processing using continuous data without any loss can be performed. According to the data transmission system of the present invention,
When the data received by the data receiving device is missing, the missing data is transmitted from the data transmitting device to the data receiving device based on the missing data request signal. Can be performed. Further, according to the data transmission method of the present invention, when there is missing data received on the receiving side, based on the missing data request signal,
Since the missing data is transmitted from the transmitting side to the receiving side, the receiving side can perform processing using continuous data without missing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a communication system according to the present invention applied to an IEEE 1394 serial interface.

FIG. 2 is an internal configuration diagram of a link layer circuit on a transmission side.

FIG. 3 is a diagram for explaining a format of a transport packet TS.

FIG. 4 is a diagram for explaining a format in a data body DB shown in FIG. 3;

FIG. 5 is a diagram for explaining a format of an isochronous communication packet transmitted via an IEEE1394 serial bus.

FIG. 6 is a diagram for explaining a connection form between a link layer circuit on the receiving side and an application.

FIG. 7 is a partial configuration diagram in an application I / F circuit shown in FIG. 6;

FIG. 8 is a flowchart for explaining an operation of the communication system shown in FIG. 1;

[Explanation of symbols]

1 ... communication system, 2,20 ... MD device, 3,13 ... M
D, 5, 23 DSP, 6, 16 Host computer, 9, 12 Link layer circuit, 10, 11 Physical layer circuit, 101 Link core, 102 Host interface circuit, 103 Application I
/ F circuit, 104: FIFO for asynchronous communication, 1
05: resolver, 106: transmission preprocessing circuit for isochronous communication, 107: transmission postprocessing circuit for isochronous communication, 108: reception preprocessing circuit for isochronous communication, 1
09 ... post-reception processing circuit for isochronous communication, 111 ...
CFR, 200, 201 ... continuity detection circuit, 202 ... C
FR writing circuit

Claims (16)

[Claims] 1. A receiving circuit for receiving data via a data transmission line, a continuity detecting circuit for monitoring continuity of the received data and detecting missing data, and the detected missing data And a transmission circuit for transmitting a missing data request signal requesting the transmission side. 2. The method according to claim 1, wherein the data includes order instruction data indicating an order of the data, and the continuity detecting circuit is configured to detect the missing data based on the order instruction data included in the received data. 2. The data processing circuit according to claim 1, wherein the data processing circuit detects the data. 3. The data processing according to claim 1, wherein said receiving circuit stops receiving said data via said data transmission path when said continuity detecting circuit detects said missing data. circuit. 4. The data processing circuit according to claim 1, wherein said receiving circuit receives a plurality of packets each including a predetermined amount of said data. 5. The continuity detecting circuit detects the missing data for each packet, and the transmitting circuit requests the transmitting side for the missing data for each packet. The data processing circuit according to claim 4, wherein the missing data request signal is transmitted. 6. The data is compressed in units of a predetermined amount of continuous data, and at least a part of data included in the same unit of compression is:
The data processing circuit according to claim 4, wherein the data processing circuit is included in different ones of the packets. 7. The data processing circuit according to claim 4, wherein said packet is transmitted through said data transmission path at predetermined time intervals. 8. The transmission circuit transmits the missing data request signal to the transmission side when receiving a reception permission signal from the transmission side via the data transmission path, the reception permission signal permitting reception of a signal. 2. The data processing circuit according to claim 1, wherein when the missing data request signal is properly received by the transmitting side, a reception confirmation signal is received from the transmitting side. 9. The data processing circuit according to claim 1, further comprising an output circuit for outputting the received data to an application. 10. The data processing circuit according to claim 1, wherein said data transmission path is a serial bus. 11. A data transmission system in which a data transmission device and a data reception device are connected via a data transmission line, wherein the data transmission device transmits data to the data reception device via the data transmission line. Receiving a missing data request signal from the data receiving device, transmitting data specified by the missing data request signal, the data receiving device receiving a data via the data transmission path; A continuity detection circuit that monitors continuity of received data and detects missing data, and a transmission circuit that transmits the missing data request signal that requests the detected missing data to the data transmission device. Data transmission system having. 12. The data includes order instruction data indicating an order of data, and the continuity detecting circuit is configured to detect the missing data based on the order instruction data included in the received data. The data transmission system according to claim 11, wherein the data transmission system detects the data. 13. The reception circuit stops receiving the data via the data transmission path when the continuity detection circuit detects the missing data.
2. A data transmission system according to claim 1. 14. The data transmission system according to claim 11, wherein said data transmission device transmits a plurality of packets each including a predetermined amount of said data via said data transmission path. 15. The data is compressed in units of a continuous predetermined amount of data, and at least a part of data included in the same unit of compression is:
The data transmission system according to claim 14, wherein the data transmission system is included in different ones of the packets. 16. A data transmission method for transmitting and receiving data via a data transmission path, wherein the data is transmitted from a transmission side to a reception side via the data transmission path, and the reception side transmits the data via the data transmission path. Monitoring the continuity of the received data to detect missing data, transmitting a missing data request signal requesting the detected missing data from the receiving side to the transmitting side, at the transmitting side, A data transmission method, comprising: upon receiving a missing data request signal, transmitting data specified by the missing data request signal to the receiving side.