JP2000151388A - Device and method for output protection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the output signal of a board having respective functions in a controller at the actuation of an FPGA (field programmable gate array) or when a fault when the FPGA is used for the board and the signal such as data is outputted from the board. SOLUTION: This output protection device has a monitored means 4 constituted of a circuit configured in an FPGA 2, a monitor means 5 which monitors whether or not the FPGA 2 is normally configured according to the signal generated by the monitored means 4, and a gate means 3 which makes a choice of whether or not the output signal from the FPGA 2 is transmitted to the outside according to the monitoring result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to (FPGA: Fi
eld Programmable GateArra
y) With regard to technology, in particular, output protection for reading the predetermined circuit data, monitoring the operation of the field programmable array that configures its own internal circuit, and invalidating the output from the field programmable array when the field programmable array abnormally operates. The present invention relates to an apparatus and an output protection method.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional example, which is a circuit configuration when a field programmable array 2 is used as a bus interface.
The buffer control signal of the three-state buffer 3 was controlled by the reset signal 8. As such a conventional technique, for example, there is one described in Japanese Patent No. 2752947. That is, the prior art field programmable gate array start-up detection system is a system having a field programmable gate array of a type in which gates inside a built-in integrated circuit are connected based on logic circuit information externally read each time power is turned on. So,
As the logic circuit information, the logic circuit is divided into a plurality of blocks, and at the time of activation of the field programmable gate array, an arbitrary startup confirmation data is set for each block in an internal register, and a startup confirmation terminal for outputting the contents of the internal register to the outside is provided. The logic circuit information created in the above is supplied to the field programmable gate array, and based on the comparison result between the output data from the startup confirmation terminal and any startup confirmation data set as the logic circuit information when the field programmable gate array is activated. The configuration is such that an abnormality of the field programmable gate array is detected.
More specifically, the logic circuit is divided into a plurality of blocks, and at the time of activation of the field programmable gate array, an arbitrary start confirmation data is set for each block in an internal register and a start confirmation terminal for outputting the contents of the internal register to the outside is provided. A field programmable gate array in which the logic circuit information created as described above is realized, a CPU that previously recognizes arbitrary startup confirmation data for each block whose setting is designated as the logic circuit information, and a startup confirmation of the field programmable gate array Terminal output data and C
A start-up confirmation circuit is provided for collating the start-up confirmation data recognized by the PU and determining whether the field-programmable gate array is normal or abnormal in accordance with the match or non-coincidence. Thereby, in the initial processing of the system by the CPU or the like, the activation of the field programmable gate array can be confirmed, and the CPU system is not activated without the activation of the field programmable gate array. It is also possible to prepare a recovery process for resetting and restarting the gate array. In addition, when the gate of the integrated circuit is connected by the read logic circuit information, the data output to the startup confirmation terminal provided for each block of the logic circuit is confirmed by the startup confirmation circuit. It can be determined for each block of the logic circuit whether or not has been activated normally.

[0003]

However, in the prior art, the data output to the bus in the device is controlled only by the reset signal. Therefore, regardless of the operation of the field programmable array 2, the data output to the bus in the device is controlled. Since the data output is permitted, when the field programmable array 2 is started with the ROM 1 not mounted due to an operation error, undefined data is output to the bus in the device to affect the data on the bus. As a result, there is a problem that the system of the apparatus is brought down.

The field programmable array 2
When the clock signal supplied to the field programmable array 2 is interrupted for some reason or the normal operation cannot be guaranteed due to a failure of the field programmable array 2 due to lack of clock monitoring capability of the device itself, the signal is transferred to a bus in the device. There is also a problem that data is output and the bus in the device is affected.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a control device for a system such as a computer or a computer in which a board having each function in the control device is used. An object of the present invention is to provide an output protection device and an output protection method for controlling an output signal when a signal such as data is output from this board using a programmable array when a field programmable array is activated or a failure occurs. .

[0006]

The gist of the present invention resides in that a predetermined circuit data stored in a memory means is read based on a clock signal supplied from the outside to configure its own internal circuit. An output protection device that monitors the operation of the field programmable array to be adjusted and invalidates the output from the field programmable array when the field programmable array abnormally operates, and is configured by a circuit configured in the field programmable array. The monitoring target means, and whether or not the field programmable array is normally configured and operating is monitored based on a signal generated by the monitoring target means,
When detecting that the signal generated by the monitoring target means is different from a desired signal, the monitoring target means outputs a buffer control signal of a logical value for invalidating the output from the field programmable array, and the monitoring target means generates the buffer control signal. Monitoring means for outputting a buffer control signal having a logical value for enabling an output from the field programmable array when detecting that the signal matches a desired signal; and An output protection device has a gate means for selecting whether or not to transmit an output from a programmable array to the outside. The gist of claim 2 of the present invention resides in that the operation of a field programmable array for reading predetermined circuit data held in a memory means and configuring its own internal circuit based on an externally applied clock signal is described. An output protection device for monitoring and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed. The output protection device is configured by a circuit configured in the field programmable array and divides the clock signal by a predetermined frequency. A clock frequency dividing means for generating a frequency-divided clock signal divided based on the ratio; and determining whether or not the field programmable array is normally configured and operating based on a signal state of the frequency-divided clock signal. Monitor and And outputting a buffer control signal having a logical value for invalidating an output from the field programmable array when a clock loss is detected based on the clock signal or the clock signal, wherein the divided clock signal or the clock signal is the configuration signal. Clock disconnection detection means for outputting a buffer control signal having a logical value for enabling an output from the field programmable array when it is detected that the buffer control signal is normally generated, based on the logical value of the buffer control signal. A gate means for selecting whether or not to transmit an output from the field programmable array to the outside. The gist of claim 3 of the present invention is to monitor the operation of a field programmable array that configures its own internal circuit by reading predetermined circuit data held in a ROM based on an externally applied clock signal. And an output protection device for invalidating an output from the field programmable array during abnormal operation of the field programmable array, the output protection device comprising a circuit configured in the field programmable array, and converting the clock signal into a predetermined frequency division ratio. A clock frequency divider circuit for generating a frequency-divided clock signal that is frequency-divided based on the clock signal, and monitoring whether the field programmable array is normally configured and operating based on the signal state of the frequency-divided clock signal. And the divided clock Or a buffer control signal of a logical value for invalidating the output from the field programmable array when detecting a clock loss based on the clock signal or the clock signal, and the divided clock signal or the clock signal is output to the configuration. A clock disconnection detection circuit that outputs a buffer control signal having a logical value that enables an output from the field programmable array when it is detected that the buffer control signal is normally generated, based on the logical value of the buffer control signal. An output protection device includes a three-state buffer for selecting whether to transmit an output from the field programmable array to the outside. According to another aspect of the present invention, there is provided an output protection device for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed. A monitoring target means configured by a circuit configured therein, and whether or not the field programmable array is normally configured and operating is monitored based on a signal generated by the monitoring target means,
When detecting that the signal generated by the monitoring target means is different from a desired signal, the monitoring target means outputs a buffer control signal of a logical value for invalidating the output from the field programmable array, and the monitoring target means generates the buffer control signal. Monitoring means for outputting a buffer control signal having a logical value for enabling an output from the field programmable array when detecting that the signal matches a desired signal; and An output protection device has a gate means for selecting whether or not to transmit an output from a programmable array to the outside. According to another aspect of the present invention, there is provided an output protection device for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed. A clock frequency dividing unit configured to generate a frequency-divided clock signal obtained by dividing a clock signal based on a predetermined frequency division ratio based on an externally supplied clock signal; Whether or not the array is configured and operating normally is monitored based on the signal state of the divided clock signal, and when a clock loss is detected based on the divided clock signal or the clock signal. The field programmable array A buffer control signal of a logical value that invalidates the output from the device and outputs the divided clock signal or the clock signal from the field programmable array when detecting that the clock signal is normally generated based on the configuration. And a gate for selecting whether to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. Means for protecting an output. Claim 6 of the present invention
The gist of the above is an output protection device that monitors the operation of the field programmable array and invalidates the output from the field programmable array when the field programmable array abnormally operates, wherein the circuit is configured in the field programmable array. A clock frequency divider circuit for generating a frequency-divided clock signal obtained by dividing a clock signal based on a predetermined frequency division ratio based on an externally applied clock signal, and the field programmable array is configured normally. Whether the divided programmable clock signal is operating based on the signal state of the divided clock signal and output from the field programmable array when a clock loss is detected based on the divided clock signal or the clock signal. Disable Output a buffer control signal having a logical value, and enable the output from the field programmable array when detecting that the divided clock signal or the clock signal is normally generated based on the configuration. A clock disconnection detection circuit that outputs a buffer control signal of a logical value, and a three-state buffer that selects whether to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. The feature resides in an output protection device. The gist of claim 7 of the present invention is:
The output protection device according to any one of claims 1 to 6, wherein the divided clock signal is variable in a predetermined frequency range by changing the circuit data. According to another aspect of the present invention, the clock disconnection detection circuit includes: a counter that starts counting in response to the input of the divided clock signal; a register that stores a count value of the counter; A register capable of setting and clearing a timer value by software from outside the array, a comparator for comparing the count value with the timer value, and a clock disconnection signal from the outside of the field programmable array set by a signal from the comparator The output protection device according to any one of claims 1 to 7, further comprising a set-reset flip-flop that is reset by (1). The gist of claim 9 of the present invention is that the register and the register are configured to be accessible from the outside of the field programmable array, and the register has a count value obtained from the counter. 9. The output protection device according to claim 8, wherein reading and clearing are possible, and the register is capable of setting and clearing the timer value. The gist of claim 10 of the present invention is that the count value of the register is read out at a constant interval by the software, and when the count value is different from the count value read immediately before, the clock signal is normally output. 9. The output according to claim 8, wherein it is assumed that the counter is input and the counter is operating, and if the count value is the same as the count value read immediately before, the clock signal is recognized as abnormal. Exists in protective equipment. According to another aspect of the present invention, an operation of a field programmable array for reading predetermined circuit data held in a memory means and configuring its own internal circuit based on an externally applied clock signal is described. What is claimed is: 1. An output protection method for monitoring and invalidating an output from a field programmable array during abnormal operation of a field programmable array, comprising: a monitoring target process including a circuit configured in the field programmable array; Whether the array is configured and operating normally is monitored based on the signal generated by the monitoring target process, and it is detected that the signal generated by the monitoring target process is different from a desired signal. When you feel A buffer control signal of a logical value for invalidating the output from the programmable array is output, and when it is detected that the signal generated by the monitoring target process matches a desired signal, the output from the field programmable array is enabled. A monitoring step of outputting a buffer control signal of a logical value to be performed, and a gating step of selecting whether to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. The output protection method. The gist of the twelfth aspect of the present invention is an operation of a field programmable array that reads predetermined circuit data held in a memory means based on a clock signal supplied from the outside and configures its own internal circuit. An output protection method for monitoring and invalidating an output from a field programmable array during abnormal operation of the field programmable array, comprising a circuit configured in the field programmable array, wherein the clock signal is divided by a predetermined frequency. A clock dividing step of generating a divided clock signal divided based on the ratio, and determining whether or not the field programmable array is normally configured and operating based on a signal state of the divided clock signal. Monitor and A buffer control signal having a logical value for invalidating an output from the field programmable array when a clock loss is detected based on the clock signal or the clock signal. A clock disconnection detecting step of outputting a buffer control signal having a logical value that enables an output from the field programmable array when it is detected that the buffer control signal is normally generated, based on the logical value of the buffer control signal. And a gate step of selecting whether to transmit an output from the field programmable array to the outside in accordance with the output. The gist of claim 13 of the present invention is to monitor the operation of a field programmable array which reads predetermined circuit data held in a ROM based on an externally supplied clock signal and configures its own internal circuit. And an output protection method for invalidating an output from the field programmable array during abnormal operation of the field programmable array, comprising a circuit configured in the field programmable array, wherein the clock signal has a predetermined dividing ratio. A clock dividing step of generating a divided clock signal divided on the basis of the above, and monitoring whether or not the field programmable array is normally configured and operating based on the signal state of the divided clock signal Along with
A buffer control signal of a logical value that invalidates an output from the field programmable array when detecting a clock break based on the divided clock signal or the clock signal, wherein the divided clock signal or the clock signal is A clock disconnection detecting step of outputting a buffer control signal having a logical value that enables an output from the field programmable array when it is detected that the buffer control signal is normally generated based on the configuration; and a logic of the buffer control signal. An output protection method characterized by having a gate step of selecting whether or not to transmit an output from the field programmable array to the outside according to a value. The gist of claim 14 of the present invention is to monitor the operation of the field programmable array,
An output protection method for invalidating an output from a field programmable array during abnormal operation of the field programmable array, wherein a monitoring target process including a circuit configured in the field programmable array, Whether or not it is configured and operating is monitored based on the signal generated by the monitoring target process, and when it is detected that the signal generated by the monitoring target process is different from a desired signal. A buffer control signal of a logical value for invalidating an output from the field programmable array is output, and when it is detected that a signal generated by the monitoring target process matches a desired signal, an output from the field programmable array is output. The logical value to enable A monitoring step of outputting § control signal,
An output protection method includes a gate step of selecting whether or not to transmit an output from the field programmable array to the outside according to a logical value of the buffer control signal. The gist of claim 15 of the present invention is an output protection method for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed. A clock dividing step of generating a divided clock signal obtained by dividing a clock signal based on a predetermined dividing ratio based on an externally supplied clock signal; and Whether or not the array is configured and operating normally is monitored based on the signal state of the divided clock signal, and when a clock loss is detected based on the divided clock signal or the clock signal. The field programmable B) outputting a buffer control signal of a logical value for invalidating the output from the a.b., and detecting that the divided clock signal or the clock signal is normally generated based on the configuration. And a clock disconnection detecting step of outputting a buffer control signal having a logical value for enabling an output from the CPU, and selecting whether or not to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. An output protection method characterized by having a gate step. The gist of claim 16 of the present invention is an output protection method for monitoring operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed. A clock divider circuit configured to generate a divided clock signal obtained by dividing a clock signal based on a predetermined dividing ratio based on an externally supplied clock signal; Whether or not the array is configured and operating normally is monitored based on the signal state of the divided clock signal, and when a clock loss is detected based on the divided clock signal or the clock signal. The field programmable A buffer control signal of a logical value for invalidating the output from the A, and when it is detected that the divided clock signal or the clock signal is normally generated based on the configuration, the field programmable array And a clock disconnection detection circuit that outputs a buffer control signal having a logical value that enables an output from the device, and selects whether or not to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. An output protection method characterized by having a three-state buffer.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a first embodiment according to the present invention.
FIG. 2 is a block diagram illustrating a configuration of the embodiment. The output protection device of the present invention shown in FIG. 1 is a control device for a system such as a computer and a computer, which outputs a signal such as data from the board using the FPGA 2 to a board having each function in the control device. In order to control the output signal when the FPGA 2 is started or when a failure occurs, a memory means (RO) is provided based on a clock signal 9 externally supplied from a control device of a system such as a computer or a computer.
M) FPGA 2 that reads predetermined circuit data held in 1 and configures its own internal circuit
The operation of the FPGA 2 is monitored when the operation of the FPGA 2 is abnormal.
A clock divider circuit (monitoring means, clock dividing means) 4, a clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5, a three-state buffer (3ST buffer, (Gate means) 3 for executing the output protection method of the present invention.

The clock frequency dividing circuit (monitoring means, clock frequency dividing means) 4 is constituted by a circuit configured in the FPGA 2, and is a frequency-divided clock obtained by dividing the clock signal 9 based on a predetermined frequency dividing ratio. Generate signal 6.

In this embodiment, the frequency-divided clock signal 6 is varied in a predetermined frequency range by changing predetermined circuit data held in the memory means 1.

A clock loss detection circuit (monitoring means, clock loss detection means) 5 monitors whether or not the FPGA 2 is normally configured and operating based on the signal state of the divided clock signal 6, and When a clock loss is detected based on the divided clock signal 6 or the clock signal 9, a buffer control signal 7 having a logical value for invalidating the output from the FPGA 2 is output, and the divided clock signal 6 or the clock signal 9 is configured. FPGA2 is detected when it is generated normally based on
And outputs a buffer control signal 7 of a logical value for validating the output from.

By using the clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5 having such a hardware configuration, data output to a bus in the apparatus can be controlled. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed.

The three-state buffer (3ST buffer, gate means) 3 selects whether or not to transmit the output from the FPGA 2 to the outside according to the logical value of the buffer control signal 7.

The clock loss detection circuit (monitoring means, clock loss detection means) 5 includes a counter 104, a register 101,
A register 103, a comparator 102, and a set / reset flip-flop 105 are provided. The counter 104 starts counting in response to the input of the divided clock signal 6.

The register 101 stores the count value of the counter 104. The register 103 can set and clear a timer value from outside the FPGA 2 by software. Register 101 and register 103 are FPGA
2 is configured to be accessible from the outside, and the count value obtained from the counter 104 can be read and cleared from the register 101. Register 103
Can set and clear the timer value.

The comparator 102 compares the values of the registers 101 and 103. The set reset flip-flop 105 is set by a signal from the comparator 102 and is reset by a clock cutoff signal from outside the FPGA 2. By setting the timer value in this way,
The data output timing can be made arbitrarily variable.

By adopting such a hardware configuration, the clock loss detection circuit (monitoring means, clock loss detection means) 5 is capable of reading the count value of the register 101 read out at regular intervals by software from the last time. When the count value is different from the read count value, it is considered that the clock signal 9 is normally input and the register 101 is operating.
If the count value is the same as the count value read immediately before, it is recognized that the clock signal 9 is abnormal.

As described above, when the FPGA 2 is used as a bus interface in the device, it is determined whether or not the FPGA 2 has been started so that output data does not become unstable during the configuration (loading of circuit data) of the FPGA 2. Clock disconnection detection circuit (monitoring means, retriggerable monostable multivibrator 13)
By detecting and controlling the output data using the clock disconnection detecting means 5, it is possible to prevent the data on the bus in the device from being affected and prevent the system from being down.

Further, even during operation, control is performed so that data is not output from the FPGA 2 to the bus in the device when the divided clock signal 6 or the clock signal 9 is cut off, so that data on the bus is not destroyed. .

In FIG. 1, while the FPGA 2 is being configured, a clock loss detection signal from the clock loss detection circuit (monitoring means, clock loss detection means) 5 outputs a logical value H, and the three-state buffer 3 is disabled. Therefore, data output from the FPGA 2 to the bus in the device is prohibited. Thus, data output to the bus in the device can be controlled. Also, due to an operation mistake,
Even when the system is started without mounting the ROM 1, data on the bus in the apparatus can be prevented from being destroyed.

When the configuration of the FPGA 2 is completed, a clock frequency dividing circuit 4 is formed in the FPGA 2 and a clock signal 9 is supplied to a clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5. When the clock signal 9 is supplied to the clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5, the clock disconnection detection signal becomes a logical value L, and the three-state buffer 3 is enabled, so that the bus from the FPGA 2 to the internal bus Data output to is allowed.

If the divided clock signal 6 or the clock signal 9 is interrupted for some reason during operation,
Clock loss detection circuit (monitoring means, clock loss detection means)
5 recognizes that the clock has been cut off, the clock cutoff detection signal becomes a logical value H, and the three-state buffer 3 is disabled, so that data output from the FPGA 2 to the bus in the device is prohibited. Thus, data output to the bus in the device can be controlled. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed.

The output protection method configures its own internal circuit by reading predetermined circuit data held in the ROM 1 based on a clock signal 9 externally supplied from a control device of a system such as a computer or a computer. An output protection method for monitoring the operation of the FPGA 2 and invalidating the output from the FPGA 2 when the FPGA 2 operates abnormally, comprising: a clock frequency dividing step executed by a clock frequency dividing circuit (monitoring target means, clock frequency dividing means) 4; The clock loss detection step executed by the clock loss detection circuit (monitoring means, clock loss detection means) 5, the three-state buffer (3
(ST buffer, gate means) 3.

The clock frequency dividing step is constituted by a circuit configured in the FPGA 2, and generates a frequency-divided clock signal 6 obtained by frequency-dividing the clock signal 9 based on a predetermined frequency dividing ratio. The clock disconnection detection step monitors whether or not the FPGA 2 is normally configured and operating based on the signal state of the divided clock signal 6, and performs a clock based on the divided clock signal 6 or the clock signal 9. When a disconnection is detected, a buffer control signal 7 of a logical value for invalidating the output from the FPGA 2 is output,
When detecting that the frequency-divided clock signal 6 or the clock signal 9 is normally generated based on the configuration, a buffer control signal 7 having a logical value for enabling the output from the FPGA 2 is output. The gate step selects whether or not to transmit the output from the FPGA 2 to the outside according to the logical value of the buffer control signal 7.

Hereinafter, the first and second embodiments of the present invention will be described.
This will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention. Referring to FIG. 1, the output protection device of the FPGA 2 and the output protection method of the FPGA 2 include a ROM 1 including data for configuring (configuring) a circuit of the FPGA 2 when the FPGA 2 is activated, and a circuit data read from the ROM 1 to construct an internal circuit. An FPGA 2, a three-state buffer 3 for controlling output data from the FPGA 2,
By monitoring the state of a clock frequency dividing circuit 4 which is internally configured (configured) and divides a clock signal 9 inputted to the FPGA 2, and a frequency-divided clock signal 6 frequency-divided by the clock frequency dividing circuit 4. A clock disconnection detecting circuit (monitoring unit, clock disconnection detecting unit) 5 for determining whether or not the FPGA 2 is operating normally is provided. By using the clock disconnection detection circuit (monitoring means, clock disconnection detection means) 5 having such a hardware configuration, data output to a bus in the device can be controlled. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed.

FIG. 2 is a block diagram showing the configuration of an embodiment of the clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5 provided in the output protection device of the FPGA 2 in FIG. The clock loss detection circuit (monitoring means, clock loss detection means) 5 includes a resistor 10 (R in the figure), a capacitor 11 (C in the figure) for determining the time constant of pulse expansion, and a time constant of pulse expansion. Resistor 12 and retriggerable
A monostable multivibrator 13 (hereinafter, multivibrator) is provided.

Next, the operation will be described with reference to the drawings. FIG. 3 is a timing chart showing the operation of the output protection device of the FPGA 2 of FIG. The frequency-divided clock signal 6 is a signal frequency-divided by the clock frequency dividing circuit 4 configured (configured) inside the FPGA 2, and the reset signal 8 resets (initializes) the entire configuration circuit of the output protection device of the present embodiment. The buffer control signal 7 is a clock loss detection signal of the clock loss detection circuit (monitoring means, clock loss detection means) 5.

FIG. 3 is a timing chart showing the operation of the output protection device of the FPGA 2 of FIG. In FIG. 3, the reset of the output protection device of the present embodiment is released in response to the reset signal 8 at the timing of time T0. When the reset is released, the FPGA 2 reads data from the ROM 1 and executes a configuration for configuring a circuit in the FPGA 2. Accordingly, the state of the FPGA 2 during this time is in the activated state, the divided clock signal 6 is not output, and accordingly, the clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5 causes the divided clock signal 6 or The three-state buffer 3 detects the clock disconnection based on the clock signal 9 and outputs a logical value H of the buffer control signal 7.
(Inhibition of output at T0 in the figure), and as a result, the three-state buffer 3 is disabled. By using the clock disconnection detection circuit (monitoring means, clock disconnection detection means) 5 having such a hardware configuration, data output to a bus in the device can be controlled. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed.

Next, at time T1, the circuit configuration of the FPGA 2 is completed (configuration is completed), the clock frequency dividing circuit 4 operates normally, and the frequency-divided clock signal 6 is output. As a result, the clock loss detection circuit (monitoring means, clock loss detection means) 5 releases the detection of the clock loss, outputs the logical value L of the buffer control signal 7, and permits the output of the three-state buffer 3 (T1 in the figure). As a result, the three-state buffer 3 is enabled.

At this time, since the clock frequency dividing circuit 4 operates normally and the clock loss detecting circuit (monitoring means, clock loss detecting means) 5 does not detect the clock loss, the FPGA 2
Is normal operation (normal operation at T1 in the figure).

In the clock disconnection detecting circuit (monitoring means, clock disconnection detecting means) 5, the multivibrator 13 responds to the falling clock of the divided clock signal 6 by a time constant determined by the capacitor 11 and the resistor 12. Start counting. However, before counting up, the count is initialized based on the fall of the divided clock signal 6 (time T2, T3), and the detection of the clock break is monitored. Here, the time based on the time constant determined by the capacitor 11 and the resistor 12 is set to a time longer than one clock of the divided clock signal 6.

Next, if the clock signal 9 is cut off at time T4 for some reason during normal operation, or the divided clock signal 6 is cut off due to the destruction of the internal circuit of the FPGA 2,
Clock loss detection circuit (monitoring means, clock loss detection means)
Reference numeral 5 denotes a clock disconnection detected at time T5 after a time constant determined by the capacitor 11 and the resistor 12 from time T4, outputs a logical value H as the buffer control signal 7, and disables the three-state buffer 3 FPGA2
From the device to the bus in the device is prohibited (T5 in the figure).
Output prohibition). Clock loss detection circuit (monitoring means, clock loss detection means) 5 having such a hardware configuration
, It is possible to control data output to a bus in the device. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed.

By determining the time constant of the capacitor 11 and the resistor 12 so as to make the time between T4 and T5 as short as possible, the influence on the bus in the device is prevented.

As described above, the FPG of this embodiment
The output protection device of A2 and the output protection method of FPGA2 are as follows.
When the FPGA 2 is activated and when the FPGA 2 is abnormal (in a state where it cannot operate halfway), it is possible to prevent the influence on the bus in the device.

The first embodiment can be summarized as follows.
A clock disconnection circuit (monitoring means, clock disconnection detecting means) 5 monitors that a clock frequency dividing circuit 4 configured (configured) by a circuit in the FPGA 2 to operate normally in a normal operation of the FPGA 2. Since the configuration is such that control to prohibit data output to the internal bus can be performed, it is possible to prevent data destruction on the internal bus of the device and a system down of the device due to the stoppage of the operation during the startup of the FPGA 2. be able to.

In addition, since the clock frequency dividing circuit 4 is provided in the FPGA 2, when the frequency of the clock signal 9 increases, the data of the clock frequency dividing circuit 4 in the ROM 1 is changed to data corresponding to the frequency. Therefore, even if the frequency of the clock signal 9 is increased, the hardware configuration is the same and can be easily realized.

(Second Embodiment) Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the output protection device of the field programmable array according to the present invention. Referring to FIG. 4, N
The AND circuit 14 and the clock loss detection circuit (monitoring means, clock loss detection means) 5 of FIG. 1 are configured.

FIG. 5 shows a clock disconnection detection circuit (monitoring means,
2 shows the configuration of a clock disconnection detecting means 5. The clock loss detection circuit (monitoring means, clock loss detection means) 5 includes a counter 104 that starts counting in response to the input of the divided clock signal 6, a register 101 that stores the count value of the counter 104, and software from the outside of the FPGA 2. Register 10 that can set and clear the timer value
3, a comparator 102 that compares the values of the registers 101 and 103, and a set / reset flip-flop 105 (hereinafter, SRFF) that is set by a signal from the comparator 102 and is reset by a clock cutoff signal from outside the FPGA 2. ing. With such a hardware configuration, data output to a bus in the device can be controlled. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed. Also, by setting the timer value,
The data output timing can be made arbitrarily variable.

Here, the register 101 and the register 103
Is configured to be accessible from outside the FPGA 2, the count value obtained from the counter 104 can be read and cleared from the register 101, and the register 103 can set and clear the timer value. .

The count value of the register 101 is read out at regular intervals by software. If the count value is different from the value read immediately before, the clock signal 9 is normally input, and the counter 101 operates. The clock signal 9 is recognized as abnormal if the values are the same.

In FIG. 5, after starting the FPGA 2, the values of the registers 101 and 103 are cleared, and the timer value is set in the register 103. The count value obtained by the counter 104 based on the divided clock signal 6 from the clock dividing circuit 4 is stored in the register 101 and is updated as long as the divided clock signal 6 is normally input.

When the timer value set in the register 103 matches the count value stored in the register 101, the comparator 102 outputs a pulse signal of a logical value H to the set terminal S of the SRFF 105, and at the same time, the contents of the register 101 are It is cleared and counts again from zero.

In the SRFF 105 which receives the logical value H pulse signal from the comparator 102 at the set terminal S, the clock cutoff detection signal becomes the logical value H output, and the NAND circuit 14
Accordingly, if the reset signal 8 is the logical value H, the buffer control signal 7 becomes the logical value L, and the data output from the enabled three-state buffer 3 to the bus in the device is permitted. Thus, data output to the bus in the device can be controlled. Also, due to an operation mistake, R
Even when the OM1 is started without mounting the OM1, data on the bus in the device can be prevented from being destroyed. By setting the timer value, the data output timing can be arbitrarily made variable.

FIG. 6 is a timing chart showing the operation of each signal of the output protection device of FIG. After the reset signal 8 is released, the FPGA 2 reads data from the ROM 1 and
Configure a circuit in the FPGA 2 (configuration). While the FPGA 2 is running, the output of the three-state buffer 3 is prohibited as described above, and as a result, the three-state buffer 3 is disabled.

Next, after the circuit configuration of the FPGA 2 is completed at the time Ta (after the completion of the configuration), a timer value is set in the register 103 by software. By setting the timer value, the data output timing can be made arbitrarily variable. When the frequency-divided clock signal 6 is output from the clock frequency dividing circuit 4, the counter 10 in the clock-loss detecting circuit (monitoring means, clock-loss detecting means) 5
When 1 starts counting, and when the values of the register 101 and the register 103 match at the time Tb, the detection of the clock interruption is released, the three-state buffer 3 is enabled, and the data output from the three-state buffer 3 is permitted.

When the divided clock signal 6 or the clock signal 9 is cut off at time Tc, the register 10 in the clock cutoff detecting circuit (monitoring means, clock cutoff detecting means) 5
The count value of 1 is not updated, and it is considered that the clock has been cut off as described above, the clock cutoff signal is input to the SRFF 105 by software, the buffer control signal 7 becomes a logical value H, and the three-state buffer 3 The state is disabled, and data output from the three-state buffer 3 to the bus in the device is prohibited. Thus, data output to the bus in the device can be controlled. Further, even if the operation is started without mounting the ROM 1 due to an operation error, data on the bus in the apparatus can be prevented from being destroyed.

The second embodiment can be summarized as follows.
A clock disconnection circuit (monitoring means, clock disconnection detecting means) 5 monitors that a clock frequency dividing circuit 4 configured (configured) by a circuit in the FPGA 2 to operate normally in a normal operation of the FPGA 2. Since the configuration is such that control to prohibit data output to the internal bus can be performed, it is possible to prevent data destruction on the internal bus of the device and a system down of the device due to the stoppage of the operation during the startup of the FPGA 2. be able to.

Also, since the clock frequency dividing circuit 4 is provided in the FPGA 2, when the frequency of the clock signal 9 increases, the data of the clock frequency dividing circuit 4 in the ROM 1 is changed to one corresponding to the frequency. Therefore, even if the frequency of the clock signal 9 is increased, the hardware configuration is the same and can be easily realized.

Further, there is an effect that data output from the FPGA 2 to the bus in the device can be controlled by time. For example, when it is desired to prohibit access to a bus in the apparatus at a start-up or reset due to a system configuration, a data output timing can be arbitrarily varied by setting a timer value.

In the present embodiment, the present invention is not limited to a field programmable array, but can be applied to a programmable logic device suitable for applying the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0052]

According to the present invention, the normal operation of the field programmable array is monitored by the clock cutoff detection circuit to monitor the normal operation of the clock frequency dividing circuit composed of the circuits in the field programmable array. Is configured to be able to perform control to prohibit data output to the bus, so that it is possible to prevent data destruction on the bus in the device and system shutdown of the device due to the stoppage of the operation during the activation of the field programmable array. .

In order to provide the clock frequency dividing circuit in the field programmable array, when the frequency of the clock signal becomes high, the data of the clock frequency dividing circuit in the ROM is changed to one corresponding to the frequency to cope with the frequency. With such a configuration, even if the frequency of the clock signal 9 increases, the hardware configuration is the same and can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a clock disconnection detection circuit provided in the output protection device of the field programmable array of FIG. 1;

FIG. 3 is a timing chart showing an operation of the output protection device of the field programmable array of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a second embodiment of an output protection device for a field programmable array according to the present invention.

FIG. 5 is a block diagram illustrating a configuration of an embodiment of a clock cutoff detection circuit provided in the output protection device of the field programmable array of FIG. 4;

6 is a timing chart showing an operation of the output protection device of the field programmable array of FIG. 4;

FIG. 7 is a block diagram showing a configuration of a conventional example, and is a circuit configuration when a field programmable array is used as a bus interface.

[Explanation of symbols]

1. ROM (memory means) 2. Field programmable array (FPGA: Fi)
eld Programmable Gate Arr
ay) 3 ... three-state buffer (3ST buffer, gate means) 4 ... clock divider circuit (monitoring means, clock divider means) 5 ... clock loss detection circuit (monitoring means, clock loss detection means) 6 ... frequency-divided clock Signal 7: Buffer control signal 8: Reset signal 9: Clock signal 10: Resistor (R) 11: Capacitor (C) 12: Resistor (R) 13: Retriggerable monostable multivibrator 14: NAND circuit 101: Register 102 ... Comparator 103: register 104: counter 105: set / reset flip-flop

Claims (16)

[Claims] An operation of a field programmable array which configures its own internal circuit by reading predetermined circuit data held in a memory means based on a clock signal given from the outside and monitors an abnormality of the field programmable array An output protection device for disabling an output from a field programmable array during operation, comprising: a monitoring target unit including a circuit configured in the field programmable array; and Whether or not it is operating is monitored based on the signal generated by the monitoring target means, and when it is detected that the signal generated by the monitoring target means is different from a desired signal, the field programmable array A buffer control signal of a logical value for invalidating the output of the logic circuit, and a logical value for validating the output from the field programmable array when detecting that a signal generated by the monitoring target means matches a desired signal. Monitoring means for outputting a buffer control signal, and gate means for selecting whether to transmit an output from the field programmable array to the outside according to a logical value of the buffer control signal. apparatus. 2. An operation of a field programmable array which configures its own internal circuit by reading predetermined circuit data held in a memory means based on an externally applied clock signal and monitors an abnormality of the field programmable array. An output protection device for invalidating an output from a field programmable array during operation, comprising: a circuit configured in the field programmable array, wherein the clock signal is divided based on a predetermined division ratio. Clock dividing means for generating a divided clock signal; and monitoring whether or not the field programmable array is normally configured and operating based on the signal state of the divided clock signal and the divided clock signal. Signal or the clock A buffer control signal of a logical value for invalidating the output from the field programmable array when detecting a clock loss based on the clock signal, and the divided clock signal or the clock signal is normal based on the configuration. Clock disconnection detecting means for outputting a buffer control signal of a logical value that enables an output from the field programmable array when it is detected that the buffer has been generated, and the field programmable according to the logical value of the buffer control signal. An output protection device comprising: gate means for selecting whether to transmit an output from an array to the outside. 3. An operation of a field programmable array which reads predetermined circuit data stored in a ROM based on an externally applied clock signal and configures its own internal circuit, and monitors an abnormal operation of the field programmable array. An output protection device for invalidating an output from a field programmable array at times, comprising a circuit configured in the field programmable array, and dividing the clock signal based on a predetermined division ratio. A clock dividing circuit for generating a clock signal, and monitoring whether or not the field programmable array is properly configured and operating based on a signal state of the divided clock signal and the divided clock signal. Or the clock A buffer control signal of a logical value that invalidates the output from the field programmable array when detecting a clock loss based on the signal, and the divided clock signal or the clock signal is normally output based on the configuration. A clock disconnection detection circuit that outputs a buffer control signal having a logical value that enables an output from the field programmable array when it is detected that the field programmable array has been generated; and the field programmable array according to the logical value of the buffer control signal. An output protection device comprising a three-state buffer for selecting whether or not to output an output from a device to the outside. 4. An output protection device for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed, comprising a circuit configured in the field programmable array. A monitoring target means configured, and whether or not the field programmable array is normally configured and operating is monitored based on a signal generated by the monitoring target means, and a signal generated by the monitoring target means. Outputs a logical value buffer control signal that invalidates the output from the field programmable array when it detects that the signal is different from the desired signal, and the signal generated by the monitoring target means matches the desired signal. Said that Monitoring means for outputting a buffer control signal having a logical value for enabling an output from the field programmable array; and selecting whether or not to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. An output protection device, comprising a gate means for performing the operation. 5. An output protection device for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed, comprising a circuit configured in the field programmable array. A clock frequency dividing means configured to generate a frequency-divided clock signal obtained by dividing a clock signal based on a predetermined frequency division ratio based on an externally applied clock signal; and that the field programmable array is normally configured. Whether the device is operating or not is monitored based on the signal state of the divided clock signal, and an output from the field programmable array is detected when a clock break is detected based on the divided clock signal or the clock signal. Disable A logic for outputting a buffer control signal of a logical value and enabling an output from the field programmable array when detecting that the divided clock signal or the clock signal is normally generated based on the configuration. Clock disconnection detecting means for outputting a buffer control signal of a value, and gate means for selecting whether or not to transmit an output from the field programmable array to the outside according to a logical value of the buffer control signal. Output protection device. 6. An output protection device for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed, comprising a circuit configured in the field programmable array. A clock frequency divider circuit configured to generate a frequency-divided clock signal obtained by dividing a clock signal based on a predetermined frequency division ratio based on an externally applied clock signal; and that the field programmable array is normally configured. Whether the device is operating or not is monitored based on the signal state of the divided clock signal, and an output from the field programmable array is detected when a clock break is detected based on the divided clock signal or the clock signal. Disable A logic for outputting a buffer control signal of a logical value and enabling an output from the field programmable array when detecting that the divided clock signal or the clock signal is normally generated based on the configuration. A clock disconnection detection circuit that outputs a value buffer control signal; and a three-state buffer that selects whether or not to transmit an output from the field programmable array to the outside according to a logical value of the buffer control signal. Output protection device. 7. The output protection device according to claim 1, wherein the frequency-divided clock signal is variable in a predetermined frequency range by changing the circuit data. 8. A clock disconnection detection circuit, comprising: a counter for starting counting in response to the input of the divided clock signal; a register for storing a count value of the counter; and a timer value by software from outside the field programmable array. A register for setting and clearing the count value; a comparator for comparing the count value with the timer value; a set / reset flip-flop which is set by a signal from the comparator and is reset by a clock cutoff signal from outside the field programmable array The output protection device according to any one of claims 1 to 7, further comprising: 9. The register and the register are configured to be accessible from outside the field programmable array, and the register can read and clear the count value obtained from the counter, 9. The output protection device according to claim 8, wherein the register is capable of setting and clearing the timer value. 10. The count value of the register is read at a constant interval by the software, and when the count value is different from the count value read immediately before, the clock signal is normally input and the counter operates. 9. The output protection device according to claim 8, wherein the clock signal is recognized as abnormal if the count value is the same as the count value read immediately before. 11. An operation of a field programmable array which configures its own internal circuit by reading predetermined circuit data held in a memory means based on an externally applied clock signal and monitors an abnormality of the field programmable array. An output protection method for invalidating an output from a field programmable array during operation, comprising: a monitoring target process including a circuit configured in the field programmable array; and Whether or not it is operating is monitored based on the signal generated by the monitoring target process, and the field programmable array is detected when it is detected that the signal generated by the monitoring target process is different from a desired signal. A logic for outputting a buffer control signal having a logical value for disabling these outputs, and for enabling the output from the field programmable array when it is detected that a signal generated by the process to be monitored matches a desired signal. A monitoring step of outputting a value buffer control signal; and a gating step of selecting whether or not to transmit an output from the field programmable array to the outside according to a logical value of the buffer control signal. Protection method. 12. An operation of a field programmable array which configures its own internal circuit by reading predetermined circuit data held in a memory means based on an externally applied clock signal and monitors an abnormality of the field programmable array. An output protection method for invalidating an output from a field programmable array during operation, comprising a circuit configured in the field programmable array, wherein the clock signal is divided based on a predetermined division ratio. A clock dividing step of generating a divided clock signal, and monitoring whether or not the field programmable array is normally configured and operating based on a signal state of the divided clock signal and the divided clock. Signal or the A buffer control signal of a logical value for invalidating an output from the field programmable array when detecting a clock loss based on the clock signal is output, and the divided clock signal or the clock signal is output based on the configuration. A clock disconnection detecting step of outputting a buffer control signal having a logical value that enables an output from the field programmable array when it is detected that the field is generated normally; and the field according to the logical value of the buffer control signal. An output protection method comprising a gate step of selecting whether to transmit an output from a programmable array to the outside. 13. An operation of a field programmable array which reads predetermined circuit data held in a ROM based on a clock signal given from the outside and configures its own internal circuit and monitors an abnormal operation of the field programmable array. An output protection method for disabling an output from a field programmable array at times, comprising a circuit configured in the field programmable array, and dividing the clock signal based on a predetermined division ratio. A clock dividing step of generating a clock signal, and monitoring whether or not the field programmable array is properly configured and operating based on a signal state of the divided clock signal and the divided clock signal. Or the clock A buffer control signal having a logical value for invalidating an output from the field programmable array when detecting a clock loss based on a signal is output, and the frequency-divided clock signal or the clock signal is normally output based on the configuration. A clock disconnection detection step of outputting a buffer control signal having a logical value that enables an output from the field programmable array when it is detected that the field programmable array is generated, and the field programmable array according to the logical value of the buffer control signal An output protection method comprising: a gate step of selecting whether to transmit an output from an external device to the outside. 14. An output protection method for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed, comprising a circuit configured in the field programmable array. A monitoring target process to be configured, and whether or not the field programmable array is normally configured and operating is monitored based on a signal generated by the monitoring target process, and a signal generated by the monitoring target process. Outputs a buffer control signal of a logical value that invalidates the output from the field programmable array when detecting that the signal is different from the desired signal, and the signal generated by the process to be monitored matches the desired signal. When the A monitoring step of outputting a buffer control signal having a logical value that enables an output from the field programmable array; and determining whether to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. An output protection method comprising a selecting gate step. 15. An output protection method for monitoring an operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed, comprising a circuit configured in the field programmable array. A clock frequency dividing step configured to generate a frequency-divided clock signal obtained by dividing a clock signal based on a predetermined frequency division ratio based on an externally applied clock signal; and that the field programmable array is properly configured. Whether the device is operating or not is monitored based on the signal state of the divided clock signal, and an output from the field programmable array is detected when a clock break is detected based on the divided clock signal or the clock signal. Disabled Output a buffer control signal having a logical value, and enable the output from the field programmable array when detecting that the divided clock signal or the clock signal is normally generated based on the configuration. A clock disconnection detecting step of outputting a buffer control signal of a logical value; and a gating step of selecting whether or not to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. And the output protection method. 16. An output protection method for monitoring operation of a field programmable array and invalidating an output from the field programmable array when an abnormal operation of the field programmable array is performed, comprising a circuit configured in the field programmable array. A clock frequency divider circuit configured to generate a frequency-divided clock signal obtained by dividing a clock signal based on a predetermined frequency division ratio based on an externally applied clock signal; and that the field programmable array is normally configured. Whether the device is operating or not is monitored based on the signal state of the divided clock signal, and an output from the field programmable array is detected when a clock break is detected based on the divided clock signal or the clock signal. Disabled Output a buffer control signal having a logical value, and enable the output from the field programmable array when detecting that the divided clock signal or the clock signal is normally generated based on the configuration. A clock disconnection detection circuit that outputs a buffer control signal of a logical value; and a three-state buffer that selects whether to transmit an output from the field programmable array to the outside according to the logical value of the buffer control signal. Characteristic output protection method.