JP2000151310A5 - - Google Patents
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- JP2000151310A5 JP2000151310A5 JP1999242466A JP24246699A JP2000151310A5 JP 2000151310 A5 JP2000151310 A5 JP 2000151310A5 JP 1999242466 A JP1999242466 A JP 1999242466A JP 24246699 A JP24246699 A JP 24246699A JP 2000151310 A5 JP2000151310 A5 JP 2000151310A5
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- 239000004065 semiconductor Substances 0.000 claims 133
- 239000000758 substrate Substances 0.000 claims 4
- 230000005669 field effect Effects 0.000 claims 3
- 230000003321 amplification Effects 0.000 claims 1
- 230000000875 corresponding Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
Claims (24)
入力端子と、
出力端子と、
第１電源端子と、
第２電源端子と、
バイアス供給端子と、
出力制御回路と、
出力モード指定端子とを具備して成り、
上記複数の半導体増幅素子は、第１の半導体増幅素子と第２の半導体増幅素子とを有し、
上記第１の半導体増幅素子は、
制御端子には入力端子に供給される信号に応答した信号が供給されると共に、バ イアス供給端子より所定レベルのバイアスが供給され、
第１端子が第１電源端子に接続され、
第２端子が第２電源端子に接続され、
上記第２の半導体増幅素子は、
制御端子が第１の半導体増幅素子の第１端子に電気的に接続されると共に、バイ アス供給端子に接続され、
第１端子が第１電源端子と出力端子とに接続され、
第２端子が第２電源端子に接続され、
上記第１の半導体増幅素子の第１端子と第２端子との間を流れる電流が、上記第２の半導体増幅素子の第１端子と第２端子との間を流れる電流より小さくなるよう半導体増幅素子が構成され、
出力制御回路は、
上記第２の半導体増幅素子の制御端子とバイアス供給端子との間に接続され、
第１の出力モードでは、半導体増幅回路の出力が所定のレベルに制限されるように、上記第２の半導体増幅素子の制御端子に供給するバイアスレベルを制御し、第２の出力モードでは、半導体増幅回路の出力に応じて、上記第２の半導体増幅素子の制御端子に供給するバイアスレベルを制御する半導体増幅回路。A plurality of semiconductor amplifying elements, each having a first terminal and a second terminal and a control terminal,
An input terminal,
An output terminal,
A first power supply terminal;
A second power supply terminal;
A bias supply terminal;
An output control circuit;
Made by and an output mode designation terminal,
It said plurality of semiconductor amplifying element has a first semiconductor amplifying device and the second semiconductor amplifying device,
The first semiconductor amplifying element includes:
With a signal in response to a signal supplied to the input terminal is supplied to the control terminal, a predetermined level of bias is supplied from the bias supply terminal,
A first terminal connected to the first power supply terminal;
A second terminal connected to the second power supply terminal;
The second semiconductor amplifying element includes:
A control terminal is electrically connected to a first terminal of the first semiconductor amplifying element, and is connected to a bias supply terminal;
The first terminal is connected to the output terminal and the first power supply terminal,
A second terminal connected to the second power supply terminal;
The first terminal and the current flowing between the second terminal of the first semiconductor amplifying element, semiconductor amplifying to be smaller than the current flowing between the first terminal and the second terminal of the second semiconductor amplifying device element is configured,
The output control circuit is
Connected between the control terminal and the bias supply terminal of said second semiconductor amplifying device,
In the first output mode, the bias level supplied to the control terminal of the second semiconductor amplifier is controlled so that the output of the semiconductor amplifier circuit is limited to a predetermined level. A semiconductor amplifier circuit that controls a bias level supplied to a control terminal of the second semiconductor amplifier element according to an output of the amplifier circuit.
更に第３の半導体増幅素子を有し、
第３の半導体増幅素子は、上記第１の半導体増幅素子と入力端子との間に接続され、
制御端子が入力端子に接続されると共に、バイアス供給端子より所定レベルのバイアスが供給され、
第１端子が第１電源端子に接続されると共に上記第１の半導体増幅素子の制御端子に電気的に接続され、
第２端子が第２電源端子に接続され、
第３の半導体増幅素子の第１端子と第２端子との間を流れる電流が、上記第２の半導体増幅素子の第１端子と第２端子との間を流れる電流より小さくなるよう半導体増幅素子が構成されたことを特徴とする半導体増幅回路。In claim 1 , the plurality of semiconductor amplifying elements are:
Furthermore, it has a third semiconductor amplifying element,
Third semiconductor amplifying element is connected between the input terminal and the first semiconductor amplifying device,
While the control terminal is connected to the input terminal, a bias of a predetermined level is supplied from the bias supply terminal,
A first terminal connected to the first power supply terminal and electrically connected to a control terminal of the first semiconductor amplifying element;
A second terminal connected to the second power supply terminal;
The third of the first terminal and the current flowing between the second terminal of the semiconductor amplifying element, a first terminal and a semiconductor amplifying element to be smaller than the current flowing between the second terminal of the second semiconductor amplifying device the semiconductor amplifier circuit, characterized in that but configured.
上記第１の出力モードでは、最大出力時に第２の半導体増幅素子の制御端子へ供給するバイアスレベルが、他の半導体増幅素子の制御端子へ供給するバイアスレベルより低いことを特徴とする半導体増幅回路。 The output control circuit according to claim 2,
In the first output mode, the bias level is supplied to the control terminal of the second semiconductor amplifying element at the maximum output, semiconductor amplifying circuit, wherein the lower bias level is supplied to the control terminal of the other semiconductor amplifier element .
補正用半導体増幅素子とスイッチ用半導体増幅素子とを具備して成り、
補正用半導体増幅素子は、
第１端子は上記バイアス供給端子に接続され、
第２端子は第２電源端子に接続され、
制御端子は抵抗性素子を介してバイアス供給端子に接続され、
スイッチ用半導体増幅素子は、
第１端子は上記補正用半導体増幅素子の制御端子に接続され、
第２端子は第２電源端子に接続され、
制御端子は上記出力モード指定端子に接続されたことを特徴とする半導体増幅回路。 The output control circuit according to claim 3,
Made by and a correction semiconductor amplifying element and semiconductor amplifying element switches,
The semiconductor amplifying element for correction is
A first terminal connected to the bias supply terminal;
The second terminal is connected to the second power terminal,
The control terminal is connected to the bias supply terminal via a resistive element,
Semiconductor amplifying elements for switches
A first terminal connected to a control terminal of the correction semiconductor amplifying element;
The second terminal is connected to the second power terminal,
A semiconductor amplifier circuit, wherein a control terminal is connected to the output mode designation terminal.
少なくとも上記第２の半導体増幅素子と上記補正用半導体増幅素子とが、同一半導体基板上に形成されたことを特徴とする半導体増幅回路。 The semiconductor amplifier circuit according to claim 4,
The semiconductor amplifier circuit and at least the second semiconductor amplifying element and the correction semiconductor amplifying element, characterized in that formed on the same semiconductor substrate.
１の半導体基板上に形成されたことを特徴とする半導体増幅回路。 The semiconductor amplifier circuit according to claim 5,
A semiconductor amplifier circuit formed on one semiconductor substrate.
上記複数の半導体増幅素子、上記補正用半導体増幅素子および上記スイッチ用半導体増幅素子が電界効果トランジスタを用いて形成されたことを特徴とする半導体増幅回路。In claim 6 , the semiconductor amplifier circuit comprises:
The semiconductor amplifier circuit, characterized in that said plurality of semiconductor amplifying elements, the correction semiconductor amplifying elements and semiconductor amplifying element for the switch is formed using a field effect transistor.
上記複数の半導体増幅素子、上記補正用半導体増幅素子および上記スイッチ用半導体増幅素子がバイポーラ型トランジスタを用いて形成されたことを特徴とする半導体増幅回路。In claim 6 , the semiconductor amplifier circuit comprises:
The semiconductor amplifier circuit, characterized in that said plurality of semiconductor amplifying elements, the correction semiconductor amplifying elements and semiconductor amplifying element for the switch is formed using a bipolar transistor.
上記複数の半導体増幅素子、上記補正用半導体増幅素子および上記スイッチ用半導体増幅素子がヘテロ接合バイポーラトランジスタを用いて形成されたことを特徴とする半導体増幅回路。In claim 6 , the semiconductor amplifier circuit comprises:
The semiconductor amplifier circuit, characterized in that said plurality of semiconductor amplifying elements, the correction semiconductor amplifying elements and semiconductor amplifying element for the switch is formed by using a heterojunction bipolar transistor.
入力端子と、
出力端子と、
第１電源端子と、
第２電源端子と、
バイアス供給端子と、
出力制御回路と、
出力モード指定端子とを具備して成り、
上記複数の半導体増幅素子は、第１の半導体増幅素子と第２の半導体増幅素子とを有し、
上記第１の半導体増幅素子は、
制御端子には入力端子に供給される信号に応答した信号が供給されると共に、バ イアス供給端子より所定レベルのバイアスが供給され、
第１端子が第１電源端子に接続され、
第２端子が第２電源端子に接続され、
上記第２の半導体増幅素子は、
制御端子が第１の半導体増幅素子の第１端子に電気的に接続されると共に、上記 出力制御回路に接続され、
第１端子が第１電源端子と出力端子とに接続され、
第２端子が第２電源端子に接続され、
出力制御回路は、
第２の半導体増幅素子の制御端子とバイアス供給端子との間に接続され、
第１の出力モードでは、第２の半導体増幅素子の制御端子に供給するバイアスレベルが一定となるように制御し、
第２の出力モードでは、半導体増幅回路の出力に応じて、第２の半導体増幅素子の制御端子に供給するバイアスレベルを制御する半導体増幅回路。And multiple semiconductor amplifying device that having a first terminal and a control terminal and a second terminal,
An input terminal,
An output terminal,
A first power supply terminal;
A second power supply terminal;
A bias supply terminal;
An output control circuit;
Made by and an output mode designation terminal,
It said plurality of semiconductor amplifying element has a first semiconductor amplifying device and the second semiconductor amplifying device,
The first semiconductor amplifying element includes:
With a signal in response to a signal supplied to the input terminal is supplied to the control terminal, a predetermined level of bias is supplied from the bias supply terminal,
A first terminal connected to the first power supply terminal;
A second terminal connected to the second power supply terminal;
The second semiconductor amplifying element includes:
A control terminal is electrically connected to the first terminal of the first semiconductor amplifying element, and is connected to the output control circuit;
The first terminal is connected to the output terminal and the first power supply terminal,
A second terminal connected to the second power supply terminal;
The output control circuit is
Connected between the control terminal and the bias supply terminal of the second semiconductor amplifying device,
In the first output mode, control is performed such that the bias level supplied to the control terminal of the second semiconductor amplifying element is constant,
In a second output mode, a semiconductor amplifier circuit that controls a bias level supplied to a control terminal of a second semiconductor amplifier according to an output of the semiconductor amplifier circuit.
更に第３の半導体増幅素子を有し、
第３の半導体増幅素子は、上記第１の半導体増幅素子と入力端子との間に接続され、
制御端子が入力端子に接続されると共に、バイアス供給端子より所定レベルのバイアスが供給され、
第１端子が第１電源端子に接続されると共に上記第１の半導体増幅素子の制御端子に電気的に接続され、
第２端子が第２電源端子に接続されたことを特徴とする半導体増幅回路。In claim 10 , the plurality of semiconductor amplifying elements are:
Furthermore, it has a third semiconductor amplifying element,
Third semiconductor amplifying element is connected between the input terminal and the first semiconductor amplifying device,
While the control terminal is connected to the input terminal, a bias of a predetermined level is supplied from the bias supply terminal,
A first terminal connected to the first power supply terminal and electrically connected to a control terminal of the first semiconductor amplifying element;
A semiconductor amplifier circuit having a second terminal connected to a second power supply terminal.
上記第１の出力モードでは、最大出力時に第２の半導体増幅素子の制御端子に供給するバイアスレベルが、上記第１又は上記第３の半導体増幅素子に供給するバイアスレベルより低いことを特徴とする半導体増幅回路。 The output control circuit according to claim 11,
In the first output mode, the bias level to the control terminal of the second semiconductor amplifying element at the maximum output, and wherein the lower bias level supplied to the first or the third semiconductor amplifying element Semiconductor amplifier circuit.
１の半導体基板上に形成されたことを特徴とする半導体増幅回路。In claim 12 , the semiconductor amplifier circuit comprises:
A semiconductor amplifier circuit formed on one semiconductor substrate.
上記複数の半導体増幅素子が電界効果トランジスタを用いて形成されたことを特徴とする半導体増幅回路。 The semiconductor amplifier circuit according to claim 13,
A semiconductor amplifier circuit, wherein the plurality of semiconductor amplifier elements are formed using a field effect transistor.
上記複数の半導体増幅素子がバイポーラ型トランジスタを用いて形成されたことを特徴とする半導体増幅回路。 The semiconductor amplifier circuit according to claim 13,
A semiconductor amplifier circuit, wherein the plurality of semiconductor amplifier elements are formed using bipolar transistors.
上記複数の半導体増幅素子がヘテロ接合バイポーラトランジスタを用いて形成されたことを特徴とする半導体増幅回路。 The semiconductor amplifier circuit according to claim 13,
A semiconductor amplifier circuit, wherein the plurality of semiconductor amplifier elements are formed using heterojunction bipolar transistors.
入力端子と、
出力端子と、
第１電源端子と、
第２電源端子と、
第１バイアス供給端子と、
第２バイアス供給端子とを具備して成り、
上記複数の半導体増幅素子は、第１の半導体増幅素子と第２の半導体増幅素子とを有し、
第１の半導体増幅素子は、
制御端子には入力端子に供給される信号に応答した信号が供給されると共に、第 １バイアス供給端子より所定レベルのバイアスが供給され、
第１端子が第１電源端子に接続され、
第２端子が第２電源端子に接続され、
第２の半導体増幅素子は、
制御端子が第１の半導体増幅素子の第１端子に電気的に接続されると共に、第２ バイアス供給端子に接続され、
第１端子が第１電源端子と出力端子とに接続され、
第２端子が第２電源端子に接続され、
第１の出力モードでは、第２バイアス供給端子より供給するバイアスレベルが一定となるよう制御し、
第２の出力モードでは、半導体増幅回路の出力に応じて、第２バイアス供給端子より供給するバイアスレベルを制御する半導体増幅回路。And multiple semiconductor amplifying device that having a first terminal and a control terminal and a second terminal,
An input terminal,
An output terminal,
A first power supply terminal;
A second power supply terminal;
A first bias supply terminal;
Made by and a second bias supply terminal,
It said plurality of semiconductor amplifying element has a first semiconductor amplifying device and the second semiconductor amplifying device,
The first semiconductor amplifying element is
With a signal in response to a signal supplied to the input terminal is supplied to the control terminal, a predetermined level of bias is supplied from the first bias supply terminal,
A first terminal connected to the first power supply terminal;
A second terminal connected to the second power supply terminal;
The second semiconductor amplifying element is
A control terminal is electrically connected to a first terminal of the first semiconductor amplifying element, and is connected to a second bias supply terminal;
The first terminal is connected to the output terminal and the first power supply terminal,
A second terminal connected to the second power supply terminal;
In the first output mode to control so that the bias level is supplied from the second bias supply terminal becomes constant,
In the second output mode, a semiconductor amplifier circuit that controls a bias level supplied from a second bias supply terminal according to an output of the semiconductor amplifier circuit.
更に第３の半導体増幅素子を有し、
第３の半導体増幅素子は、上記第１の半導体増幅素子と入力端子との間に接続され、
制御端子が入力端子に接続されると共に、第１バイアス供給端子より所定レベルのバイアスが供給され、
第１端子が第１電源端子に接続されると共に上記第１の半導体増幅素子の制御端子に電気的に接続され、
第２端子が第２電源端子に接続されたことを特徴とする半導体増幅回路。In claim 17 , the plurality of semiconductor amplifying elements are:
Furthermore, it has a third semiconductor amplifying element,
Third semiconductor amplifying element is connected between the input terminal and the first semiconductor amplifying device,
The control terminal is connected to the input terminal, and a predetermined level of bias is supplied from the first bias supply terminal.
A first terminal connected to the first power supply terminal and electrically connected to a control terminal of the first semiconductor amplifying element;
A semiconductor amplifier circuit having a second terminal connected to a second power supply terminal.
上記第１の出力モードでは、最大出力時に第２バイアス供給端子より供給するバイアスレベルは、上記第１バイアス供給端子より供給するバイアスレベルより低いことを特徴とする半導体増幅回路。In claim 18 , the output control circuit comprises:
In the first output mode, the bias level is supplied from the second bias supply terminal at the maximum output, semiconductor amplifying circuit, wherein the lower bias level is supplied from the first bias supply terminal.
１の半導体基板上に形成されたことを特徴とする半導体増幅回路。 The semiconductor amplifier circuit according to claim 19,
A semiconductor amplifier circuit formed on one semiconductor substrate.
上記複数の半導体増幅素子が電界効果トランジスタを用いて形成されたことを特徴とする半導体増幅回路。In claim 20 , the semiconductor amplifier circuit comprises:
A semiconductor amplifier circuit, wherein the plurality of semiconductor amplifier elements are formed using a field effect transistor.
上記複数の半導体増幅素子がバイポーラ型トランジスタを用いて形成されたことを特徴とする半導体増幅回路。In claim 20 , the semiconductor amplifier circuit comprises:
A semiconductor amplifier circuit, wherein the plurality of semiconductor amplifier elements are formed using bipolar transistors.
上記複数の半導体増幅素子がヘテロ接合バイポーラトランジスタを用いて形成されたことを特徴とする半導体増幅回路。In claim 20 , the semiconductor amplifier circuit comprises:
A semiconductor amplifier circuit, wherein the plurality of semiconductor amplifier elements are formed using heterojunction bipolar transistors.
入力端子と、An input terminal,
出力端子と、An output terminal,
第１電源端子と、A first power supply terminal;
第２電源端子と、A second power supply terminal;
バイアス供給端子と、A bias supply terminal;
出力制御回路と、An output control circuit;
出力モード指定端子とを具備して成り、An output mode designation terminal;
上記複数の半導体増幅素子は、第１段の半導体増幅素子と出力段の半導体増幅素子とを有し、The plurality of semiconductor amplifiers include a first-stage semiconductor amplifier and an output-stage semiconductor amplifier,
上記第１段の半導体増幅素子は、The first-stage semiconductor amplifying element includes:
制御端子には入力端子に供給される信号に応答した信号が供給されると共に、バA signal corresponding to the signal supplied to the input terminal is supplied to the control terminal, and the control terminal receives the signal. イアス供給端子より所定レベルのバイアスが供給され、A bias of a predetermined level is supplied from the bias supply terminal,
第１端子が第１電源端子に接続され、A first terminal connected to the first power supply terminal;
第２端子が第２電源端子に接続され、A second terminal connected to the second power supply terminal;
上記出力段の半導体増幅素子は、The semiconductor amplifying element at the output stage is:
制御端子が第１段の半導体増幅素子の第１端子に電気的に接続されると共に、バThe control terminal is electrically connected to the first terminal of the first-stage semiconductor amplifying device, and イアス供給端子に接続され、Connected to the IAS supply terminal,
第１端子が第１電源端子と出力端子とに接続され、A first terminal connected to the first power supply terminal and the output terminal;
第２端子が第２電源端子に接続され、A second terminal connected to the second power supply terminal;
上記第１段の半導体増幅素子の第１端子と第２端子との間を流れる電流が、上記出力段の半導体増幅素子の第１端子と第２端子との間を流れる電流より小さくなるよう半導体増幅素子が構成され、The semiconductor that the current flowing between the first terminal and the second terminal of the first-stage semiconductor amplifying element is smaller than the current that flows between the first terminal and the second terminal of the output-stage semiconductor amplifying element. An amplification element is configured,
出力制御回路は、The output control circuit is
上記出力段の半導体増幅素子の制御端子とバイアス供給端子との間に接続され、第１の出力モードでは、半導体増幅回路の出力が所定のレベルに制限されるように、上記出力段の半導体増幅素子の制御端子に供給するバイアスレベルを制御し、The semiconductor amplifier of the output stage is connected between the control terminal and the bias supply terminal of the semiconductor amplifier of the output stage, and in the first output mode, the output of the semiconductor amplifier is limited to a predetermined level. Control the bias level supplied to the control terminal of the element,
第２の出力モードでは、半導体増幅回路の出力に応じて、上記出力段の半導体増幅素子の制御端子に供給するバイアスレベルを制御する半導体増幅回路。In a second output mode, a semiconductor amplifier circuit that controls a bias level supplied to a control terminal of a semiconductor amplifier element in the output stage according to an output of the semiconductor amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24246699A JP3766239B2 (en) | 1998-08-31 | 1999-08-30 | Semiconductor amplifier circuit and wireless communication device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10-244709 | 1998-08-31 | ||
| JP24470998 | 1998-08-31 | ||
| JP24246699A JP3766239B2 (en) | 1998-08-31 | 1999-08-30 | Semiconductor amplifier circuit and wireless communication device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003362053A Division JP2004088804A (en) | 1998-08-31 | 2003-10-22 | Semiconductor amplifier circuit and radio communication device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2000151310A JP2000151310A (en) | 2000-05-30 |
| JP2000151310A5 true JP2000151310A5 (en) | 2004-10-28 |
| JP3766239B2 JP3766239B2 (en) | 2006-04-12 |
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ID=26535770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24246699A Expired - Fee Related JP3766239B2 (en) | 1998-08-31 | 1999-08-30 | Semiconductor amplifier circuit and wireless communication device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3766239B2 (en) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002052588A1 (en) | 2000-12-25 | 2002-07-04 | Hitachi, Ltd. | Semiconductor device, and method and apparatus for manufacturing semiconductor device |
| TW594888B (en) | 2001-09-05 | 2004-06-21 | Hitachi Ltd | Semiconductor device and manufacturing method thereof and wireless communication device |
| JP3838547B2 (en) | 2001-12-11 | 2006-10-25 | 株式会社ルネサステクノロジ | Power supply device for high frequency power amplifier circuit |
| JP3932259B2 (en) | 2001-12-12 | 2007-06-20 | 株式会社ルネサステクノロジ | High frequency power amplifier circuit and electronic component for wireless communication |
| KR20040022254A (en) * | 2002-09-03 | 2004-03-12 | (주)나리지 온 | Power amplifier device for including power control device |
| JPWO2004023649A1 (en) | 2002-09-05 | 2006-01-05 | 株式会社ルネサステクノロジ | Electronic component for high frequency power amplification and wireless communication system |
| JP2004140518A (en) | 2002-10-16 | 2004-05-13 | Renesas Technology Corp | High frequency power amplification electronic component and wireless communication system |
| JP2004140633A (en) | 2002-10-18 | 2004-05-13 | Hitachi Ltd | Electronic component for high-frequency power amplification and wireless communication system |
| JP4160365B2 (en) | 2002-11-07 | 2008-10-01 | 株式会社ルネサステクノロジ | Electronic component for high frequency power amplification and wireless communication system |
| JP2004328107A (en) | 2003-04-22 | 2004-11-18 | Renesas Technology Corp | Semiconductor integrated circuit for high frequency power amplification and electronic component for high frequency power amplification, and wireless communication system |
| JP2004328555A (en) | 2003-04-28 | 2004-11-18 | Renesas Technology Corp | High-frequency electric power amplifying electronic component, and radio communications system |
| JP4287193B2 (en) | 2003-05-15 | 2009-07-01 | 株式会社ルネサステクノロジ | Electronic component for high frequency power amplification and wireless communication system |
| JP2005020476A (en) | 2003-06-27 | 2005-01-20 | Renesas Technology Corp | High frequency power amplifier circuit and wireless communication system |
| JP2005223877A (en) | 2004-01-05 | 2005-08-18 | Renesas Technology Corp | High-frequency power amplifier circuit |
| JP2005229268A (en) | 2004-02-12 | 2005-08-25 | Renesas Technology Corp | High frequency power amplifier circuit and radio communication system |
| JP2006013566A (en) | 2004-06-22 | 2006-01-12 | Renesas Technology Corp | Electronic part for high-frequency power amplification |
| JP2006013753A (en) | 2004-06-24 | 2006-01-12 | Renesas Technology Corp | Wireless communication system and semiconductor integrated circuit |
| JP2006094075A (en) | 2004-09-24 | 2006-04-06 | Renesas Technology Corp | Semiconductor integrated circuit for high-frequency power amplification and electronic component equipped therewith |
| JP2006094076A (en) | 2004-09-24 | 2006-04-06 | Renesas Technology Corp | High-frequency power amplifier circuit and electronic component for high-frequency power amplification |
| JP4488309B2 (en) | 2005-02-28 | 2010-06-23 | 株式会社ルネサステクノロジ | Electronic components for high frequency power amplification |
| JP4683468B2 (en) | 2005-03-22 | 2011-05-18 | ルネサスエレクトロニクス株式会社 | High frequency power amplifier circuit |
| WO2009063535A1 (en) | 2007-11-16 | 2009-05-22 | Fujitsu Limited | Bias circuit and method for controlling bias circuit |
| JP2011124679A (en) * | 2009-12-09 | 2011-06-23 | Tdk Corp | Power amplifier |
| JP2016025453A (en) | 2014-07-18 | 2016-02-08 | セイコーエプソン株式会社 | Circuit device, electronic apparatus, and movable body |
-
1999
- 1999-08-30 JP JP24246699A patent/JP3766239B2/en not_active Expired - Fee Related
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