JPS58115930A - Electronic switching amplifier circuit - Google Patents

Electronic switching amplifier circuit

Info

Publication number
JPS58115930A
JPS58115930A JP56212830A JP21283081A JPS58115930A JP S58115930 A JPS58115930 A JP S58115930A JP 56212830 A JP56212830 A JP 56212830A JP 21283081 A JP21283081 A JP 21283081A JP S58115930 A JPS58115930 A JP S58115930A
Authority
JP
Japan
Prior art keywords
input
circuit
signal
gain
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56212830A
Other languages
Japanese (ja)
Inventor
Kazuo Takahagi
高萩 和男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56212830A priority Critical patent/JPS58115930A/en
Publication of JPS58115930A publication Critical patent/JPS58115930A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means

Landscapes

  • Electronic Switches (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To realize an electronic switching amplifier circuit which amplifies an arbitrary input signal out of input signals to a lot of input terminals with an arbitrary gain, with a comparatively simple circuit. CONSTITUTION:An output signal is picked up at an output terminal 3 through an amplifier 14. Since the output signal is fed back to each differential circuit with negative feedback circuits consisting respectively of resistors 38, 39;40, 41;42, 43 and 44, 45 provided depending on input differential circuits, the gain between the input and output to a signal to an input terminal 26 depends on the resistors 38, 39, the gain to a signal to an input terminal 27 depends on the resistors 40, 41, the gain to a signal to an input terminal 28 depends on the resistors 42, 43 and the gain of a signal to an input terminal 29 depends on the resistors 44, 15 respectively. An arbitrary gain is set at each input terminal by selecting the value of the resistors 38-45.

Description

【発明の詳細な説明】 本発明は電子切換増幅回路に関し、複数個の入力信号の
うちの任意1信号のみを、任意のfu得で増幅すること
を可能とした電子切換増幅回路を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic switching amplifier circuit, and provides an electronic switching amplifier circuit that can amplify only one arbitrary signal among a plurality of input signals with an arbitrary fu gain. It is.

第1図に従来の電子切換回路の例を示す。回路は、トラ
ンジスタ8.9よりなる差動回路とトランジスタ10.
11よりなる差動回路の一対の差動回路と、この差動回
路対の出力を共通入力とする増幅回路14とこの増幅回
路14の出力を前述差動回路対へ負帰還させるための共
通負帰還回路を形成する抵抗16.17と制御端4.6
の信号により交互に動作、停止させられるトランジスタ
12.13の対で構成されている。なお、16は負荷抵
抗である。
FIG. 1 shows an example of a conventional electronic switching circuit. The circuit consists of a differential circuit consisting of transistors 8.9 and 10.
11, an amplifier circuit 14 which uses the output of the differential circuit pair as a common input, and a common negative circuit for negative feedback of the output of the amplifier circuit 14 to the differential circuit pair. Resistor 16.17 and control terminal 4.6 forming a feedback circuit
It consists of a pair of transistors 12 and 13 which are alternately activated and deactivated by the signal . Note that 16 is a load resistance.

かかる回路において、入力端1,2に加えられた入力信
号はトランジスタ12.13動作ニ基イて選択される。
In such a circuit, the input signals applied to input terminals 1 and 2 are selected based on the operation of transistors 12 and 13.

tなわち、トランジスタ12.13のうち動作している
いづれか一方のトランジスタのコレクタにエミッタが接
続されている差動回路への入力信号のみが選択され負荷
抵抗15への出力となり増幅回路14へ入力され出力端
子3へ出力信号としてとり出される。例えばトランジス
タ12が動作13が停止の場合は、トランジスタ12の
コレクタに接続されたトランジスタ8,9よりなる差動
回路の入力端1への信号のみが出力端3へ出力信号とし
てとり出され、一方停止しているトランジスター3のコ
レクタに接続されタトランジスタ10,11よりなる差
動回路の入力端2への信号は出力端3へは出力されない
ことになる。
In other words, only the input signal to the differential circuit whose emitter is connected to the collector of one of the operating transistors 12 and 13 is selected and output to the load resistor 15 and input to the amplifier circuit 14. and output to the output terminal 3 as an output signal. For example, when the operation 13 of the transistor 12 is stopped, only the signal to the input terminal 1 of the differential circuit consisting of the transistors 8 and 9 connected to the collector of the transistor 12 is taken out as an output signal to the output terminal 3; The signal to the input terminal 2 of the differential circuit consisting of the transistors 10 and 11 connected to the collector of the stopped transistor 3 is not output to the output terminal 3.

ところで、かかる従来の回路においては、差動回路が一
対であるため入力端が一対しか設定できず入力信号が3
種以上のときは選択が不可能となる欠点がある。さらに
負帰還回路が双方の差動回路に共通であるため、入力信
号と出力信号間の利得は抵抗16.17の値により一義
的に定められ入力端子1と2への入力信号に対し同一値
のみしか得られず、異なった利得を必要とする回路への
適用は不可能であるという欠点もあった。
By the way, in such a conventional circuit, since the differential circuit is a pair, only one pair of input terminals can be set, and the input signal is
There is a drawback that selection is impossible when there are more than one species. Furthermore, since the negative feedback circuit is common to both differential circuits, the gain between the input signal and the output signal is uniquely determined by the value of the resistor 16.17, and is the same value for the input signals to input terminals 1 and 2. It also has the disadvantage that it is impossible to apply it to circuits that require different gains.

本発明は、かかる欠点を解消し、任意の数の入力信号の
うち任意の入力信号を任意の利得で増幅することのでき
る増幅回路を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide an amplifier circuit that can amplify any input signal out of any number of input signals with any gain.

第2図に、本発明にかかる回路例を示す。第2図におい
て18と19 、20と21.22と23゜24と25
は差動回路を構成するトランジスタ対である。端子26
.27.28.29は前述4個の差動回路にそれぞれ設
けられた4個の入力端である。入力端26〜29への入
力信号は制御端子30.31,32.33へ印加する制
御信号により、トランジスタ30〜33のうちの任意の
もののみを完全動作状態とし、残りを完全停止状態とす
ることにより、出力端3へ選択的にとり出される。すな
わちトランジスタ30〜33の中で1つのトランジスタ
のみ完全動作状態とするならば、そのコレクタに接続さ
れている差動回路のみが完全動作状態となり、残りの差
動回路は完全停止状態となる。この結果完全動作状態の
差動回路へ接続された入力端子への入力信号のみが選択
され差動回路の負荷15への出力信号となる。この出力
信号は増幅回路14を通り出力端3へ出力信号として取
り出される。出力信号は、入力の差動回路別に設けられ
た抵抗38と39.40と41゜42と43.44と4
6よりなる負帰還回路によって差動回路別に帰還される
ため、入力端子26への信号に対する入出力間の利得は
抵抗38と39、入力端子27への信号に対する入出力
間の利得は抵抗40と41.入力端子28への信号に対
する利得は抵抗42と43.入力端子29への信号に対
する利得は抵抗44と15によって各々各々決定される
ことになる。したがって抵抗38〜45の値の選定によ
って、各入力端子毎に任意の利得値を設定することがで
きる。
FIG. 2 shows an example of a circuit according to the present invention. In Figure 2, 18 and 19, 20 and 21.22 and 23°24 and 25
are a pair of transistors forming a differential circuit. terminal 26
.. 27, 28, and 29 are four input terminals respectively provided in the four differential circuits mentioned above. The input signals to the input terminals 26 to 29 are applied to the control terminals 30.31 and 32.33, so that only any one of the transistors 30 to 33 is fully activated, and the rest are completely stopped. As a result, it is selectively taken out to the output terminal 3. That is, if only one of the transistors 30 to 33 is brought into full operation, only the differential circuit connected to its collector will be brought into full operation, and the remaining differential circuits will be completely stopped. As a result, only the input signal to the input terminal connected to the fully operational differential circuit is selected and becomes the output signal to the load 15 of the differential circuit. This output signal passes through the amplifier circuit 14 and is taken out to the output terminal 3 as an output signal. The output signal is generated by resistors 38, 39, 40, 41, 42, 43, 44, and 4 provided for each input differential circuit.
6, the gain between the input and output for the signal to the input terminal 26 is set by the resistors 38 and 39, and the gain between the input and output for the signal to the input terminal 27 is set by the resistor 40. 41. The gain for the signal to input terminal 28 is determined by resistors 42 and 43 . The gain for the signal to input terminal 29 will be determined by resistors 44 and 15, respectively. Therefore, by selecting the values of the resistors 38 to 45, any gain value can be set for each input terminal.

例えば、ゝ制御端子30〜33の信号によってトランジ
スタ34が完全動作状態、トランジスタ31〜33が完
全停止状態にあったとすれば、トランジスタ34の→レ
クタに接続されたトランジスタ18と19よりなる差動
回路のみが完全動作状態となり、一方トランジスタ31
〜33のコレクタに各々エミッタが共通接続されたトラ
ンジスタ20と21.22と23.24と25よりなる
3組の差動回路はそのいずれもが完全停止状態となる。
For example, if the transistor 34 is in a fully operational state and the transistors 31 to 33 are in a completely stopped state by the signals from the control terminals 30 to 33, then a differential circuit consisting of transistors 18 and 19 connected to the →rector of the transistor 34 only transistor 31 is fully operational, while transistor 31
The three sets of differential circuits made up of transistors 20, 21, 22, 23, 24, and 25 whose emitters are commonly connected to the collectors of transistors 21, 23, 24, and 25 are completely stopped.

このため入力端子26に印加された信号のみが出力端3
への出力信号として取り出され入力端子27〜29に印
加された信号は出力信号として出ないことになる。さら
にトランジスタ18と19の差動回路のみが動作状態で
あるから負帰還回路は、抵抗38と39によるものが有
効であり抵抗38の値をR38、抵抗39の値をR39
とす路の影響を受けずに任意の値に決定できる。
Therefore, only the signal applied to the input terminal 26 is transmitted to the output terminal 3.
The signals taken out as output signals to and applied to the input terminals 27 to 29 will not be output as output signals. Furthermore, since only the differential circuit of transistors 18 and 19 is in operation, the negative feedback circuit consisting of resistors 38 and 39 is effective, and the value of resistor 38 is set to R38, and the value of resistor 39 is set to R39.
An arbitrary value can be determined without being affected by the path.

以上のように、本発明によれば、多数の入力端子への入
力信号のうち任意の信号のみを任意の利得で増幅するこ
とのできる電子切換増幅回路を比較的簡単な回路で実現
することができ、電子機器の簡素化、信頼性の向上に非
常に有用である。
As described above, according to the present invention, it is possible to realize, with a relatively simple circuit, an electronic switching amplifier circuit that can amplify only an arbitrary signal with an arbitrary gain among signals input to a large number of input terminals. It is extremely useful for simplifying electronic equipment and improving its reliability.

なお以上の説明は入力端が4個の場合を例示して行った
が、入力端子数相当の入力差動回路、制御端子、制御ト
ランジスタ、負帰還回路を設けることにより任意の入力
端の数の電子切換増幅回路を得ることができる。なお、
第2図において46は定電流回路であり、出力端の直流
バイアス値を一定に保つことにより切換時のクリック音
をなくすのに有効であるが、本発明において必ずしも必
要なものではない。増幅回路14は負荷抵抗15と負帰
還抵抗間の干渉をなくすこと、十分な開回路利得を得る
ためなどに有効であるが必ずしも必要なものではない葬
発明の説明はNPN)ランジスタを用いた場合について
説明したが、PNPトランジスタ、FETなどを用いて
も実施することができることは当然である。さらに本発
明の回路は回路の半導体集積回路化に支障をきたすこと
のない回路要素の使用で構成されているため、全体を単
一の半導体基体内へ集積化するのにすこぶる好適である
Although the above explanation has been given by way of example in which there are four input terminals, it is possible to increase the number of input terminals to any desired number by providing input differential circuits, control terminals, control transistors, and negative feedback circuits corresponding to the number of input terminals. An electronically switched amplifier circuit can be obtained. In addition,
In FIG. 2, reference numeral 46 denotes a constant current circuit, which is effective in eliminating click sounds during switching by keeping the DC bias value at the output terminal constant, but is not necessarily necessary in the present invention. The amplifier circuit 14 is effective for eliminating interference between the load resistor 15 and the negative feedback resistor and for obtaining sufficient open circuit gain, but is not necessarily necessary. Although this has been explained above, it goes without saying that it can also be implemented using PNP transistors, FETs, and the like. Furthermore, since the circuit of the present invention is constructed using circuit elements that do not interfere with the integration of the circuit into a semiconductor integrated circuit, it is extremely suitable for integrating the entire circuit into a single semiconductor substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電子切換増幅回路の例を示す図、第2図
は本発明の一実施例にかかる電子切換増幅回路を示す図
である。 26〜29−−−・・・入力端、30〜33−一・・制
御端子、18〜25・・・・・・差動回路を構成するト
ランジスタ、34〜37・・・・・・制御回路を構成す
るトランジスタ、14・・・・・・増幅回路、46・・
・・・・・・・定電流源、15・・・・・・差動回路の
共通負荷、38〜45・・・・・・帰還回路を構成する
抵抗。
FIG. 1 is a diagram showing an example of a conventional electronic switching amplifier circuit, and FIG. 2 is a diagram showing an electronic switching amplifier circuit according to an embodiment of the present invention. 26-29-----Input terminal, 30-33---Control terminal, 18-25---Transistor forming differential circuit, 34-37---Control circuit Transistors, 14, configuring the amplifier circuit, 46...
. . . Constant current source, 15 . . . Common load of the differential circuit, 38 to 45 . . . Resistors constituting the feedback circuit.

Claims (2)

【特許請求の範囲】[Claims] (1)それぞれ別個の入力端子を有し、出力回路に共通
接続された複数個の差動回路と、同複数個の差動回路の
うちの一個のみを動作状態とし残りの差動回路を停止状
態とする゛制御回路と、前記出力回路から前記複数個の
差動回路のそれぞれの負帰還側端子へ各別に負帰還を施
す帰還回路を具備してなり、前記入力端子中の所定の入
力端子への入力信号のみを任意の利得で増幅して出力す
ることを特徴とする電子切換増幅回路。
(1) Multiple differential circuits each having separate input terminals and commonly connected to the output circuit, with only one of the multiple differential circuits in operation and the remaining differential circuits stopped. a feedback circuit that separately provides negative feedback from the output circuit to the negative feedback side terminals of each of the plurality of differential circuits, An electronic switching amplification circuit characterized by amplifying only an input signal to an input signal with a desired gain and outputting the amplified signal.
(2)制御回路が、ベースに入力端子が付設された差動
回路数と等しい数のトランジスタよりなることを特徴と
する特許請求の範囲第1項に記載の電子切換増幅回路。
(2) The electronic switching amplifier circuit according to claim 1, wherein the control circuit comprises a number of transistors equal to the number of differential circuits each having an input terminal attached to its base.
JP56212830A 1981-12-29 1981-12-29 Electronic switching amplifier circuit Pending JPS58115930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56212830A JPS58115930A (en) 1981-12-29 1981-12-29 Electronic switching amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56212830A JPS58115930A (en) 1981-12-29 1981-12-29 Electronic switching amplifier circuit

Publications (1)

Publication Number Publication Date
JPS58115930A true JPS58115930A (en) 1983-07-09

Family

ID=16629059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56212830A Pending JPS58115930A (en) 1981-12-29 1981-12-29 Electronic switching amplifier circuit

Country Status (1)

Country Link
JP (1) JPS58115930A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077119U (en) * 1983-10-31 1985-05-29 パイオニア株式会社 component car stereo system
JPS6090937U (en) * 1983-11-28 1985-06-21 東光株式会社 switch circuit
JPS63105516A (en) * 1986-10-14 1988-05-10 テクトロニックス・インコーポレイテッド Multiplexer
JPH03125509A (en) * 1989-10-11 1991-05-28 Toshiba Corp Amplifier circuit with switch
JPH04102311U (en) * 1991-02-01 1992-09-03 ミツミ電機株式会社 variable gain amplifier circuit
KR100467883B1 (en) * 1996-03-27 2005-06-20 코닌클리케 필립스 일렉트로닉스 엔.브이. Wireless receiver

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132968A (en) * 1977-04-25 1978-11-20 Sony Corp Switch circuit
JPS5482157A (en) * 1977-12-14 1979-06-30 Hitachi Ltd Electronic switch circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132968A (en) * 1977-04-25 1978-11-20 Sony Corp Switch circuit
JPS5482157A (en) * 1977-12-14 1979-06-30 Hitachi Ltd Electronic switch circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077119U (en) * 1983-10-31 1985-05-29 パイオニア株式会社 component car stereo system
JPS6090937U (en) * 1983-11-28 1985-06-21 東光株式会社 switch circuit
JPH0326687Y2 (en) * 1983-11-28 1991-06-10
JPS63105516A (en) * 1986-10-14 1988-05-10 テクトロニックス・インコーポレイテッド Multiplexer
JPH0575291B2 (en) * 1986-10-14 1993-10-20 Tektronix Inc
JPH03125509A (en) * 1989-10-11 1991-05-28 Toshiba Corp Amplifier circuit with switch
JPH04102311U (en) * 1991-02-01 1992-09-03 ミツミ電機株式会社 variable gain amplifier circuit
KR100467883B1 (en) * 1996-03-27 2005-06-20 코닌클리케 필립스 일렉트로닉스 엔.브이. Wireless receiver

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