JP2000150724A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000150724A JP2000150724A JP10324067A JP32406798A JP2000150724A JP 2000150724 A JP2000150724 A JP 2000150724A JP 10324067 A JP10324067 A JP 10324067A JP 32406798 A JP32406798 A JP 32406798A JP 2000150724 A JP2000150724 A JP 2000150724A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- insulating substrate
- supply plate
- filler
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に絶縁基板上の電源板に半導体素子を実装し、こ
れら表面が充填材で被覆された半導体装置に関する。さ
らに詳細には、本発明は、パワートランジスタを搭載し
た半導体素子を複数個絶縁基板上に電源板を介して実装
する、マルチチップモジュール構造の半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a semiconductor element is mounted on a power supply board on an insulating substrate, and the surface of which is covered with a filler. More specifically, the present invention relates to a semiconductor device having a multi-chip module structure in which a plurality of semiconductor elements each having a power transistor are mounted on an insulating substrate via a power supply plate.
【０００２】[0002]
【従来の技術】パワートランジスタを搭載した半導体素
子を複数個共通基板上に実装するパワートランジスタモ
ジュールとしての半導体装置の開発が行われている。2. Description of the Related Art A semiconductor device has been developed as a power transistor module in which a plurality of semiconductor elements each having a power transistor are mounted on a common substrate.
【０００３】この種の半導体装置においては、絶縁基板
上に電源板を搭載し、この電源板上に複数個の半導体素
子が実装される。複数個の半導体素子間はリード線によ
り相互に電気的に接続され、また半導体素子には外部接
続リード線が電気的に接続される。パワートランジスタ
がバイポーラトランジスタの場合には電源板にはコレク
タ電源電圧が供給され、MOSFETの場合には電源板にはド
レイン電源電圧が供給され、これらの電源電圧は半導体
素子にその裏面側から供給される。電源板は電気抵抗値
が小さくかつ熱伝導性に優れた例えば銅板で形成され
る。絶縁基板は例えば熱伝導性に優れた窒化アルミニウ
ムで形成される。In this type of semiconductor device, a power supply plate is mounted on an insulating substrate, and a plurality of semiconductor elements are mounted on the power supply plate. A plurality of semiconductor elements are electrically connected to each other by leads, and external connection leads are electrically connected to the semiconductor elements. When the power transistor is a bipolar transistor, the power supply plate is supplied with the collector power supply voltage. When the power transistor is a MOSFET, the power supply plate is supplied with the drain power supply voltage.These power supply voltages are supplied to the semiconductor element from the back side thereof. You. The power supply plate is formed of, for example, a copper plate having a small electric resistance value and excellent heat conductivity. The insulating substrate is formed of, for example, aluminum nitride having excellent thermal conductivity.
【０００４】絶縁基板の表面側には電源板及び電源板上
の半導体素子を取り囲むケースが取り付けられ、絶縁基
板の裏面側に金属製の放熱板が取り付けられる。ケース
内には充填材が充填され、この充填材は半導体素子、電
源板、絶縁基板のそれぞれの表面を被覆し保護する。充
填材には複雑な形状の表面を確実に被覆できる例えばシ
リコーンゲルが使用され、シリコーンゲルはケース内に
流し込まれた後に硬化される。A power supply plate and a case surrounding the semiconductor element on the power supply plate are mounted on the front side of the insulating substrate, and a metal heat radiating plate is mounted on the rear side of the insulating substrate. A filler is filled in the case, and the filler covers and protects respective surfaces of the semiconductor element, the power supply plate, and the insulating substrate. As the filler, for example, a silicone gel which can surely cover the surface of a complicated shape is used, and the silicone gel is cured after being poured into the case.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、前述の
パワートランジスタモジュールを構築する半導体装置に
おいては、以下の点について配慮がなされていない。However, in the semiconductor device for constructing the above-mentioned power transistor module, no consideration is given to the following points.
【０００６】パワートランジスタの動作には通常の論理
回路や記憶回路を構築するトランジスタの動作電圧に比
べて高電圧が必要とされるので、半導体装置の電源板端
部には高い電界集中が発生してしまう。充填材としての
シリコーンゲルは絶縁基板としての窒化アルミニウムに
比べて比誘電率がかなり低く電源板端部の電界集中を充
分に緩和することができないばかりか、シリコーンゲル
自体の絶縁破壊電圧が低い。さらに、シリコーンゲルと
窒化アルミニウムとの間の接着力を充分に確保すること
ができない。このため、電源板端部で電界集中が発生す
ると、この電源板端部において絶縁基板と充電材との界
面に部分な放電すなわち部分沿面放電が発生し、この部
分沿面放電により界面が損傷する沿面破壊が発生し、半
導体装置の絶縁破壊に対する信頼性が低下してしまう。Since the operation of the power transistor requires a higher voltage than the operating voltage of a transistor constituting a normal logic circuit or a storage circuit, a high electric field concentration occurs at the end of the power supply plate of the semiconductor device. Would. Silicone gel as a filler has a considerably lower dielectric constant than aluminum nitride as an insulating substrate, so that the electric field concentration at the end of the power supply plate cannot be sufficiently alleviated, and the dielectric breakdown voltage of the silicone gel itself is low. Furthermore, it is not possible to ensure a sufficient adhesive force between the silicone gel and the aluminum nitride. Therefore, when the electric field concentration occurs at the end of the power supply plate, partial discharge, that is, partial creeping discharge occurs at the interface between the insulating substrate and the charging material at the end of the power supply plate, and the creeping surface is damaged by the partial creeping discharge. Breakdown occurs, and the reliability of the semiconductor device against dielectric breakdown decreases.
【０００７】本発明は上記課題を解決するためになされ
たものである。従って、本発明の目的は、電源板端部に
おいて絶縁基板と充填材との間の界面に沿面放電が発生
することを防ぎ、沿面破壊の発生を防止することによ
り、絶縁破壊に対する信頼性を向上させることができる
半導体装置を提供することである。The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to improve the reliability against dielectric breakdown by preventing creeping discharge from occurring at the interface between the insulating substrate and the filler at the end of the power supply plate and preventing the occurrence of creeping breakdown. It is to provide a semiconductor device which can be operated.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に、請求項１に記載された発明は、半導体装置におい
て、半導体素子が実装された電源板と、電源板を搭載す
る絶縁基板と、半導体素子、電源板、絶縁基板のそれぞ
れの表面を被覆する充填材と、電源板端部と絶縁基板と
の間に配設され、充填材よりも破壊電圧が高く、充填材
よりも絶縁基板との接着力が高い沿面破壊防止部材と、
を備えたことである。沿面破壊防止部材は、電源板端部
の電界を緩和するために、充填材に比べて比誘電率の高
い材料で形成することが好ましい。充填材にはシリコー
ンゲルが実用的に使用できる。沿面破壊防止部材には、
下記（Ａ）乃至（Ｈ）の少なくともいずれか１つが実用
的に使用できる。 （Ａ）エポキシ樹脂 （Ｂ）酸化アルミニウムの粉末を混入させたエポキシ樹
脂 （Ｃ）窒化アルミニウムの粉末を混入させたエポキシ樹
脂 （Ｄ）雲母の粉末を混入させたエポキシ樹脂 （Ｅ）ポリエステル樹脂 （Ｆ）酸化アルミニウムの粉末を混入させたシリコーン
ゲル （Ｇ）窒化アルミニウムの粉末を混入させたシリコーン
ゲル （Ｈ）雲母の粉末を混入させたシリコーンゲル エポキシ樹脂、シリコーンゲルに混入される各種粉末は
比誘電率を高くする機能を有する。さらに、沿面破壊防
止部材には、充填材の底部分に比誘電率を高める粉末を
沈降させ硬化させたシリコーンゲルが使用できる。この
ように構成される半導体装置においては、電界が集中す
る電源板端部の絶縁基板表面と沿面破壊防止部材との２
種類の絶縁物界面の接着力を高め、絶縁物界面に沿って
沿面放電が発生することを防止することができる。さら
に、沿面破壊防止部材そのものの絶縁耐圧が充填材より
も高いので、沿面破壊防止部材の絶縁破壊を防止するこ
とができる。さらに、沿面破壊防止部材は電源板端部の
限定された領域にのみ形成され、絶縁基板と電源板との
間に温度サイクルで発生する応力を受けにくいので、沿
面破壊防止部材の剥離を防ぎ、より一層、沿面放電の発
生を防止して半導体装置の絶縁破壊に対する信頼性を向
上させることができる。さらに、エポキシ樹脂、各種粉
末を混入させたエポキシ樹脂、ポリエステル樹脂、各種
粉末を混入させたシリコーンゲルは、シリコーンゲル単
独の充填材に比べて比誘電率が高く、電源板端部での電
界集中を緩和させることができるので、より一層、沿面
放電の発生を防止して半導体装置の絶縁破壊に対する信
頼性を向上させることができる。特に各種粉末を混入さ
せたシリコーンゲルは、沿面放電の発生を防止しつつ、
硬化前の柔軟性により半導体素子、電源板、絶縁基板の
それぞれの表面が作り出す複雑な形状の表面を確実に被
覆することができる。Means for Solving the Problems To solve the above-mentioned problems, the invention described in claim 1 is a semiconductor device, comprising: a power supply plate on which a semiconductor element is mounted; an insulating substrate on which the power supply plate is mounted; A filler that covers the respective surfaces of the semiconductor element, the power supply plate, and the insulating substrate, and is disposed between an end of the power supply plate and the insulating substrate, has a higher breakdown voltage than the filler, and has a higher breakdown voltage than the filler. Creepage prevention member with high adhesive strength
It is to have. The creepage prevention member is preferably formed of a material having a higher dielectric constant than the filler in order to reduce the electric field at the end of the power supply plate. A silicone gel can be practically used as the filler. For creepage prevention members,
At least one of the following (A) to (H) can be used practically. (A) Epoxy resin (B) Epoxy resin mixed with aluminum oxide powder (C) Epoxy resin mixed with aluminum nitride powder (D) Epoxy resin mixed with mica powder (E) Polyester resin (F ) Silicone gel mixed with aluminum oxide powder (G) Silicone gel mixed with aluminum nitride powder (H) Silicone gel mixed with mica powder Various powders mixed in epoxy resin and silicone gel are dielectric materials Has the function of increasing the rate. Further, as the creepage prevention member, a silicone gel in which a powder for increasing the relative dielectric constant is settled and hardened at the bottom portion of the filler can be used. In the semiconductor device having such a configuration, the surface of the insulating substrate at the end of the power supply plate where the electric field is concentrated and the creepage prevention member are used.
It is possible to increase the adhesive force at the interface between the insulators and prevent the occurrence of creeping discharge along the insulator interface. Further, since the dielectric strength of the creeping breakdown prevention member itself is higher than that of the filler, the dielectric breakdown of the creeping breakdown preventing member can be prevented. Furthermore, the creepage prevention member is formed only in a limited area at the end portion of the power supply plate, and is hardly subjected to stress generated by a temperature cycle between the insulating substrate and the power supply plate. Further, the occurrence of creeping discharge can be prevented, and the reliability of the semiconductor device against dielectric breakdown can be improved. Furthermore, the epoxy resin, the epoxy resin mixed with various powders, the polyester resin, and the silicone gel mixed with various powders have a higher dielectric constant than the silicone gel alone filler, and the electric field concentration at the edge of the power supply plate Can be alleviated, so that the occurrence of creeping discharge can be prevented, and the reliability of the semiconductor device against dielectric breakdown can be further improved. In particular, silicone gel mixed with various powders prevents creepage discharge,
Due to the flexibility before curing, it is possible to reliably cover the surface of a complicated shape created by each surface of the semiconductor element, the power supply plate, and the insulating substrate.
【０００９】この発明の第２の特徴は、半導体装置にお
いて、半導体素子を搭載した電源板と、電源板を収納し
この電源板端部の少なくとも一部を側壁で覆う凹部を有
する絶縁基板と、半導体素子、電源板、絶縁基板のそれ
ぞれの表面を被覆する充填材と、を備えたことである。
絶縁基板の凹部はエッチングで絶縁基板表面の一部を掘
り下げることにより形成される。さらに、凹部の角部分
には丸みを付けることが、電界集中を緩和するために好
ましい。このように構成される半導体装置においては、
絶縁基板の凹部に電源板の少なくとも厚さ方向の一部を
埋設させたので、電界が集中する電源板端部、特に最も
電界が集中する電源板端下角部を凹部側壁、すなわち絶
縁基板自体で被覆することができる。従って、電源板端
下角部には沿面放電が発生する（沿面放電の原因とな
る）絶縁基板と充填材との間の界面が存在しないように
できるので、根本的に沿面破壊を防止することができ、
半導体装置の絶縁破壊に対する信頼性を向上させること
ができる。According to a second feature of the present invention, in a semiconductor device, there is provided a power supply plate on which a semiconductor element is mounted, an insulating substrate having a recess for accommodating the power supply plate and covering at least a part of an end of the power supply plate with a side wall, A filler that covers the respective surfaces of the semiconductor element, the power supply plate, and the insulating substrate.
The concave portion of the insulating substrate is formed by digging a part of the surface of the insulating substrate by etching. Further, it is preferable to round the corners of the concave portion in order to reduce the electric field concentration. In the semiconductor device configured as described above,
Since at least a part of the power supply plate in the thickness direction is buried in the concave portion of the insulating substrate, the end of the power supply plate where the electric field is concentrated, particularly the lower corner of the power supply plate end where the electric field is concentrated is the side wall of the concave portion, i.e. Can be coated. Therefore, it is possible to prevent the creepage discharge from occurring at the lower corner portion of the end of the power supply plate, so that there is no interface between the insulating substrate and the filler, which causes creepage discharge. Can,
Reliability of the semiconductor device against dielectric breakdown can be improved.
【００１０】[0010]
【発明の実施の形態】（第１実施の形態）以下、本発明
の実施の形態を図面を参照して説明する。図１は本発明
の第１の実施の形態に係る半導体装置の概略断面構成図
である。図１に示すように、半導体装置は、複数個の半
導体素子（半導体チップ）１を共通の基板上に実装した
マルチチップモジュール構造を採用し、本実施の形態に
おいては複数個の半導体素子１のそれぞれにパワートラ
ンジスタが搭載されているので、パワートランジスタモ
ジュールを構築する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional configuration diagram of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device employs a multi-chip module structure in which a plurality of semiconductor elements (semiconductor chips) 1 are mounted on a common substrate. Since each has a power transistor, a power transistor module is constructed.
【００１１】複数個の半導体素子１は共通の電源板３上
に実装され、この電源板３は絶縁基板４上に搭載され
る。半導体素子１は単結晶シリコンを母体とする半導体
基板にパワートランジスタとして例えばMISFET（Metal
Insulator Semiconductor Field Effect Transistor）
やバイポーラトランジスタを搭載したものである。半導
体素子１の表面上には図示しないが端子（ボンディング
パッド）が配設される。隣接配置された半導体素子１の
端子間はリード線２を通して電気的に接続される。さら
に、半導体素子１の端子には外部接続リード線５が電気
的に接続される。The plurality of semiconductor elements 1 are mounted on a common power supply plate 3, and this power supply plate 3 is mounted on an insulating substrate 4. The semiconductor element 1 is, for example, an MISFET (Metal
Insulator Semiconductor Field Effect Transistor)
And a bipolar transistor. Although not shown, terminals (bonding pads) are provided on the surface of the semiconductor element 1. The terminals of the semiconductor elements 1 arranged adjacent to each other are electrically connected through lead wires 2. Further, an external connection lead wire 5 is electrically connected to a terminal of the semiconductor element 1.
【００１２】半導体素子１にMISFETが搭載される場合、
電源板３にはドレイン電源電圧が供給され、このドレイ
ン電源電圧は半導体素子１にその裏面側から供給され
る。半導体素子１にバイポーラトランジスタが搭載され
る場合、電源板３にはコレクタ電源電圧が供給され、こ
のコレクタ電源電圧は半導体素子１にその裏面側から供
給される。詳細に図示していないが、電源板３には外部
接続リード線５が直接電気的に接続されており、外部か
ら電源板３にドレイン電源電圧やコレクタ電源電圧が供
給される。電源板３には電気抵抗値が小さく熱伝導性に
優れた銅（Cu）板が実用的に使用でき、例えば電源板３
の厚さは0.3mmで形成される。When the MISFET is mounted on the semiconductor element 1,
The power supply plate 3 is supplied with a drain power supply voltage, and the drain power supply voltage is supplied to the semiconductor element 1 from the back side thereof. When a bipolar transistor is mounted on the semiconductor element 1, a collector power supply voltage is supplied to the power supply plate 3, and the collector power supply voltage is supplied to the semiconductor element 1 from the back side. Although not shown in detail, an external connection lead wire 5 is directly electrically connected to the power supply plate 3, and a drain power supply voltage and a collector power supply voltage are supplied to the power supply plate 3 from the outside. For the power supply plate 3, a copper (Cu) plate having a small electric resistance value and excellent heat conductivity can be used practically.
Is formed with a thickness of 0.3 mm.
【００１３】絶縁基板４には熱伝導性に優れた窒化アル
ミニウム（AlN）板が実用的に使用でき、例えば絶縁基
板４の厚さは1.0mmで形成される。As the insulating substrate 4, an aluminum nitride (AlN) plate having excellent thermal conductivity can be practically used. For example, the thickness of the insulating substrate 4 is 1.0 mm.
【００１４】絶縁基板４は金属製の放熱板６上に搭載さ
れ、この放熱板６の周縁部には半導体素子１、電源板３
及び絶縁基板４の外周囲を取り囲むケース７が配設され
るとともに、ケース７内部には半導体素子１等を外部環
境から保護するための充填材１０が充填される。半導体
素子１の端子や電源板３に電気的に接続された外部接続
リード線５はターミナルホルダ９に取り付けられてお
り、このターミナルホルダ９は封止部材８を介してケー
ス７上側に取り付けられる。The insulating substrate 4 is mounted on a metal radiator plate 6, and the semiconductor element 1 and the power supply plate 3
A case 7 surrounding the outer periphery of the insulating substrate 4 is provided, and the inside of the case 7 is filled with a filler 10 for protecting the semiconductor element 1 and the like from the external environment. The external connection lead wires 5 electrically connected to the terminals of the semiconductor element 1 and the power supply plate 3 are attached to a terminal holder 9, and the terminal holder 9 is attached to the upper side of the case 7 via a sealing member 8.
【００１５】充填材１０には本実施の形態においてシリ
コーンゲルが使用され、シリコーンゲルはケース７内に
流動性を有する状態で流し込まれこの後に硬化させたも
のである。シリコーンゲルは、同図１に示すように、半
導体素子１、電源板３、絶縁基板４のそれぞれの表面が
作り出す複雑な形状の表面を確実に被覆することができ
る。In the present embodiment, a silicone gel is used for the filler 10, and the silicone gel is poured into the case 7 in a fluid state and then cured. As shown in FIG. 1, the silicone gel can reliably cover the surfaces of the semiconductor element 1, the power supply plate 3, and the insulating substrate 4, which have complicated shapes.
【００１６】本実施の形態に係る半導体装置において
は、電源板３の端部と絶縁基板４との間であって電源板
３の周縁部の全域に沿面破壊防止部材１１が配設され
る。本実施の形態において、沿面破壊防止部材１１は電
源板３の周縁部に塗り固められたエポキシ樹脂で形成さ
れる。エポキシ樹脂は、充填材１０のシリコーンゲルと
絶縁基板４の窒化アルミニウムとの間の接着力に比べ
て、窒化アルミニウムとの間及びシリコーンゲルとの間
のそれぞれの接着力を高くすることができ、さらにシリ
コーンゲルに比べて高い破壊電圧を有する。さらに、窒
化アルミニウムの比誘電率は約8.8、シリコーンゲルの
比誘電率は約2.8であるのに対して、エポキシ樹脂の比
誘電率は3.5〜5.0で窒化アルミニウムに比べて低いがシ
リコーンゲルに対しては高い比誘電率を有する。比誘電
率が高ければ高いほど、電源板３の端部に発生する電界
を緩和させることができる。In the semiconductor device according to the present embodiment, a creeping breakdown prevention member 11 is disposed between the end of the power supply plate 3 and the insulating substrate 4 and over the entire periphery of the power supply plate 3. In the present embodiment, the creepage prevention member 11 is formed of an epoxy resin applied to the periphery of the power supply plate 3. The epoxy resin can increase the adhesive force between the silicone gel of the filler 10 and the aluminum gel of the insulating substrate 4 as compared with the adhesive force between the silicon gel and the aluminum nitride, Furthermore, it has a higher breakdown voltage than silicone gel. Furthermore, while the relative permittivity of aluminum nitride is about 8.8 and the relative permittivity of silicone gel is about 2.8, the relative permittivity of epoxy resin is 3.5 to 5.0, which is lower than that of aluminum nitride, but is lower than that of silicone gel. Have a high relative dielectric constant. The higher the relative permittivity, the more the electric field generated at the end of the power supply plate 3 can be reduced.
【００１７】図２は電界分布図であり、横軸は電源板３
端からの距離（mm）、縦軸は1kVを電源板３に加えた時
の電界強度（kV/mm）をそれぞれ示す。図２に示すよう
に、電源板３端から約0.2mmまでの領域においては電界
強度が非常に大きい。沿面破壊防止部材１１は図２に示
す電源板３端部の電界強度が大きい領域、具体的には少
なくとも電源板３端から約0.2mmまでの領域に配設され
ることが好ましい。FIG. 2 is an electric field distribution diagram.
The distance from the end (mm) and the vertical axis indicate the electric field strength (kV / mm) when 1 kV is applied to the power supply plate 3. As shown in FIG. 2, the electric field intensity is extremely large in a region from the end of the power supply plate 3 to about 0.2 mm. The creepage prevention member 11 is preferably disposed in a region where the electric field strength at the end of the power supply plate 3 shown in FIG. 2 is large, specifically, at least in a region about 0.2 mm from the end of the power supply plate 3.
【００１８】さらに、沿面破壊防止部材１１には、エポ
キシ樹脂に限らず、絶縁基板４との間の接着力を高め、
かつ破壊電圧が高くできるポリエステル樹脂を使用する
ことができる。Further, the creepage prevention member 11 is not limited to the epoxy resin, but has an increased adhesive force with the insulating substrate 4.
In addition, a polyester resin capable of increasing the breakdown voltage can be used.
【００１９】さらに、沿面破壊防止部材１１には、材料
自体の比誘電率を高める各種粉末を混入させたエポキシ
樹脂を使用することができる。粉末には、比誘電率が約
8.3の酸化アルミニウム、比誘電率が約7の窒化アルミニ
ウム、比誘電率が約7の雲母のいずれか又は複数組み合
わせたものが実用的に使用できる。これらの粉末が混入
されたエポキシ樹脂は、比誘電率が高いだけでなく、耐
熱性、耐部分放電（耐沿面放電）特性のそれぞれにおい
ても優れている。Further, as the creepage prevention member 11, an epoxy resin mixed with various powders for increasing the relative dielectric constant of the material itself can be used. The powder has a relative dielectric constant of about
Any one or a combination of aluminum oxide having a relative dielectric constant of about 8.3, aluminum nitride having a relative dielectric constant of about 7, and mica having a relative dielectric constant of about 7 can be practically used. The epoxy resin in which these powders are mixed has not only a high dielectric constant but also excellent heat resistance and partial discharge (anti-creeping discharge) characteristics.
【００２０】このように構成される半導体装置において
は、電界が集中する電源板３の端部の絶縁基板４の表面
と沿面破壊防止部材１１との２種類の絶縁物界面の接着
力を高め、この絶縁物界面に沿って沿面放電が発生する
ことを防止することができる。さらに、沿面破壊防止部
材１１そのものの絶縁耐圧が充填材１０よりも高いの
で、沿面破壊防止部材１１の絶縁破壊を防止することが
できる。さらに、沿面破壊防止部材１１は電源板３の端
部の限定された領域にのみ形成され、絶縁基板４と電源
板３との間に温度サイクルで発生する応力を受けにくい
ので、沿面破壊防止部材１１の絶縁基板４からの剥離を
防ぎ、より一層、沿面放電の発生を防止して半導体装置
の絶縁破壊に対する信頼性を向上させることができる。In the semiconductor device configured as described above, the adhesive force at the interface between the two types of insulators between the surface of the insulating substrate 4 at the end of the power supply plate 3 where the electric field is concentrated and the creeping breakdown prevention member 11 is increased. It is possible to prevent creeping discharge from occurring along the insulator interface. Furthermore, since the dielectric strength of the creeping breakdown prevention member 11 itself is higher than that of the filler 10, the dielectric breakdown of the creeping breakdown preventing member 11 can be prevented. Further, the creepage breaking prevention member 11 is formed only in a limited area at the end of the power supply plate 3 and is less susceptible to stress generated between the insulating substrate 4 and the power supply plate 3 due to a temperature cycle. 11 can be prevented from being separated from the insulating substrate 4 and the occurrence of creeping discharge can be further prevented, so that the reliability of the semiconductor device against dielectric breakdown can be improved.
【００２１】さらに、エポキシ樹脂、ポリエステル樹
脂、各種粉末を混入させたエポキシ樹脂はいずれも充填
材１０のシリコーンゲルに比べて比誘電率が高く、電源
板３の端部での電界強度を減少させることができるの
で、より一層、沿面放電の発生を防止して半導体装置の
絶縁破壊に対する信頼性を向上させることができる。Furthermore, epoxy resin, polyester resin, and epoxy resin mixed with various powders all have a higher relative dielectric constant than the silicone gel of the filler 10 and reduce the electric field strength at the end of the power supply plate 3. Therefore, the occurrence of creeping discharge can be prevented, and the reliability of the semiconductor device against dielectric breakdown can be further improved.
【００２２】（第２の実施の形態）本実施の形態は、前
述の第１の実施の形態に係る半導体装置の沿面破壊防止
部材（エポキシ樹脂やポリエステル樹脂）１１に代え
て、シリコーンゲルを主成分とする沿面破壊防止部材を
備えた場合を説明するものである。図３は本発明の第２
の実施の形態に係る半導体装置の概略断面構成図であ
る。(Second Embodiment) In the present embodiment, a silicone gel is mainly used in place of the creepage prevention member (epoxy resin or polyester resin) 11 of the semiconductor device according to the first embodiment. It is to explain a case where a creepage prevention member as a component is provided. FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a schematic cross-sectional configuration diagram of a semiconductor device according to an embodiment.
【００２３】図３に示すように、本実施の形態に係る半
導体装置は、電源板３の端部を含む半導体素子１、電源
板３、絶縁基板４のそれぞれを被覆するように、充填材
１０の底部分に沿面破壊防止部材１２を備える。沿面破
壊防止部材１２は、充填材１０と同様のシリコーンゲル
を主成分として形成されており、電源板３の端部の電界
集中を緩和するための比誘電率が高い粉末が混入された
シリコーンゲルで形成される。比誘電率が高い粉末には
前述の第１の実施の形態に係る半導体装置で説明したよ
うに酸化アルミニウム、窒化アルミニウム、雲母のいず
れか又はそれらを組み合わせたものが実用的に使用でき
る。すなわち、沿面破壊防止部材１２は、酸化アルミニ
ウムの粉末を混入させたシリコーンゲル、窒化アルミニ
ウムの粉末を混入させたシリコーンゲル、雲母の粉末を
混入させたシリコーンゲル等で形成される。As shown in FIG. 3, in the semiconductor device according to the present embodiment, the filler 10 is formed so as to cover the semiconductor element 1 including the end of the power supply plate 3, the power supply plate 3, and the insulating substrate 4. Is provided with a creeping fracture prevention member 12 at the bottom portion. The creepage breaking prevention member 12 is formed mainly of the same silicone gel as the filler 10, and is mixed with a silicone gel mixed with a powder having a high relative dielectric constant for alleviating the electric field concentration at the end of the power supply plate 3. Is formed. As described in the semiconductor device according to the first embodiment, any one of aluminum oxide, aluminum nitride, mica, or a combination thereof can be practically used as the powder having a high relative dielectric constant. That is, the creepage prevention member 12 is formed of a silicone gel mixed with aluminum oxide powder, a silicone gel mixed with aluminum nitride powder, a silicone gel mixed with mica powder, or the like.
【００２４】沿面破壊防止部材１２の形成方法は以下の
通りである。 （１）まず初めに、半導体素子１が実装された電源板３
を搭載する絶縁基板４をケース７内において放熱板６上
に取り付ける。 （２）次に、ケース７内に充填材１０のシリコーンゲル
を流し込む。 （３）引き続き比誘電率を高める粉末を充填材１０のシ
リコーンゲル内に混入させる。 （４）この粉末がある程度沈降した時点で充填材１０の
シリコーンゲルを硬化させる。これにより、シリコーン
ゲル単独の充填材１０がケース７の上側に形成されると
ともに、ケース７の下側つまり充填材１０の底部分には
比誘電率を高める粉末が混入されたシリコーンゲルから
なる沿面破壊防止部材１２を形成することができる。The method of forming the creepage prevention member 12 is as follows. (1) First, the power supply plate 3 on which the semiconductor element 1 is mounted
Is mounted on the heat sink 6 in the case 7. (2) Next, the silicone gel of the filler 10 is poured into the case 7. (3) Subsequently, a powder for increasing the relative dielectric constant is mixed into the silicone gel of the filler 10. (4) When the powder has settled to some extent, the silicone gel of the filler 10 is cured. As a result, the filling material 10 made of silicone gel alone is formed on the upper side of the case 7, and the lower surface of the case 7, that is, the bottom portion of the filling material 10, is made of a silicone gel mixed with a powder for increasing the dielectric constant. The break prevention member 12 can be formed.
【００２５】このように構成される半導体装置において
は、シリコーンゲルに酸化アルミニウム、窒化アルミニ
ウム又は雲母のいずれかの粉末を混入させて沿面破壊防
止部材１２を形成することにより、電源板３の端部の電
界集中を緩和させることができる。具体的には、電源板
３の端部において部分沿面放電開始電圧は5〜10%程度上
昇させることができる。前述の第１の実施の形態に係る
半導体装置の沿面破壊防止部材１１のエポキシ樹脂に比
べて部分沿面放電開始電圧の上昇は少ないものの、沿面
破壊防止部材１２はフレキシブル性をもつシリコーンゲ
ルを主成分としているので、電源板３の端部の複雑な形
状の表面を確実に被覆することができ、また熱サイクル
で発生する応力を吸収することができる。従って、沿面
破壊防止部材１２は電源板３の端部を含み半導体素子
１、電源板３、絶縁基板４のそれぞれの表面にわたって
全域に形成することができる。In the semiconductor device configured as described above, the creepage breakage prevention member 12 is formed by mixing any one of aluminum oxide, aluminum nitride, and mica powder into the silicone gel. Electric field concentration can be reduced. Specifically, the partial creeping discharge starting voltage at the end of the power supply plate 3 can be increased by about 5 to 10%. Although the rise of the partial creeping discharge starting voltage is smaller than that of the epoxy resin of the creeping breakdown prevention member 11 of the semiconductor device according to the first embodiment, the creeping breakdown prevention member 12 is mainly composed of silicone gel having flexibility. Therefore, the surface of the complicated shape at the end of the power supply plate 3 can be surely covered, and the stress generated by the thermal cycle can be absorbed. Therefore, the creepage prevention member 12 can be formed over the entire surface of the semiconductor element 1, the power supply plate 3, and the insulating substrate 4 including the end of the power supply plate 3.
【００２６】（第３の実施の形態）本実施の形態は、半
導体装置の絶縁基板４そのものに沿面破壊防止機能を備
えた場合を説明するものである。図４は本発明の第３の
実施の形態に係る半導体装置の概略断面構成図である。(Third Embodiment) This embodiment describes a case where the insulating substrate 4 of the semiconductor device itself has a creeping surface breakdown preventing function. FIG. 4 is a schematic sectional configuration diagram of a semiconductor device according to the third embodiment of the present invention.
【００２７】図４に示すように、本実施の形態に係る半
導体装置は、電源板３を収納しこの電源板３の端部の少
なくとも一部を側壁４Ｗで覆う凹部４Ｄを有する絶縁基
板４を備える。この絶縁基板４の凹部４Ｄには電源板３
の厚さ方向の一部分（底部分）が少なくとも埋設され
る。すなわち、電源板３の端部は絶縁基板４の側壁４
Ｗ、詳細には充電材１０や前述の第１の実施の形態で説
明したエポキシ樹脂や第２の実施の形態で説明した粉末
を混入させたシリコーンゲルに比べて比誘電率が高い窒
化アルミニウムからなる絶縁基板４自体で覆うことがで
きる。従って、電源板３の端部の電界強度を効果的に緩
和させることができる。As shown in FIG. 4, the semiconductor device according to the present embodiment includes an insulating substrate 4 having a concave portion 4D that houses a power supply plate 3 and covers at least a part of an end of the power supply plate 3 with a side wall 4W. Prepare. The power supply plate 3 is provided in the recess 4D of the insulating substrate 4.
At least a portion (bottom portion) in the thickness direction is embedded. That is, the end of the power supply plate 3 is
W, more specifically, from the charging material 10 or aluminum nitride having a higher dielectric constant than the silicone gel mixed with the epoxy resin described in the first embodiment or the powder described in the second embodiment. Can be covered with the insulating substrate 4 itself. Therefore, the electric field intensity at the end of the power supply plate 3 can be effectively reduced.
【００２８】凹部４Ｄを形成するために、この凹部４Ｄ
の深さに相当する分、厚い絶縁基板４が使用される。例
えば、0.1〜0.2mm程度厚い絶縁基板４が実用的に使用で
きる。凹部４Ｄはエッチング技術により0.1〜0.2mm程度
の深さで蝕刻され掘り下げられる。等方性エッチング技
術などを利用し、凹部４Ｄの底面と側壁４Ｗとの角部に
丸みを付けることにより、電源板３の端の下角部の電界
集中をより一層緩和させることができるので、部分沿面
放電開始電圧を上昇させることができる。In order to form the concave portion 4D, the concave portion 4D
The thick insulating substrate 4 is used corresponding to the depth. For example, an insulating substrate 4 having a thickness of about 0.1 to 0.2 mm can be practically used. The recess 4D is etched and dug down to a depth of about 0.1 to 0.2 mm by an etching technique. By using an isotropic etching technique or the like to round the corner between the bottom surface of the recess 4D and the side wall 4W, the electric field concentration at the lower corner of the end of the power supply plate 3 can be further alleviated. The creeping discharge starting voltage can be increased.
【００２９】このように構成される半導体装置において
は、絶縁基板４の凹部４Ｄに電源板３の少なくとも厚さ
方向の一部を埋設させ、電界が集中する電源板３の端部
特に電界強度が最も大きい電源板３端下角部を凹部４Ｄ
の側壁４Ｗ、すなわち絶縁基板４自体で被覆したので、
電源板３端下角部には沿面放電が発生する（沿面放電の
原因となる）絶縁基板４と充填材１０との間の界面が存
在しなくなる。従って、根本的に沿面破壊を防止するこ
とができ、半導体装置の絶縁破壊に対する信頼性を向上
させることができる。In the semiconductor device configured as described above, at least a part of the power supply plate 3 in the thickness direction is buried in the concave portion 4D of the insulating substrate 4, and the end portion of the power supply plate 3 where the electric field is concentrated, particularly the electric field strength is reduced. The lower corner of the largest power supply plate 3 is recessed 4D
Side wall 4W, that is, the insulating substrate 4 itself,
An interface between the insulating substrate 4 where the creeping discharge occurs (causing creeping discharge) and the filler 10 does not exist at the lower corner of the end of the power supply plate 3. Therefore, it is possible to fundamentally prevent creeping breakdown and improve reliability of the semiconductor device against dielectric breakdown.
【００３０】（第４の実施の形態）本実施の形態は、前
述の第１の実施の形態に係る半導体装置と第３の実施の
形態に係る半導体装置とを組み合わせた場合を説明する
ものである。図５は本発明の第４の実施の形態に係る半
導体装置の概略断面構成図である。(Fourth Embodiment) The present embodiment describes a case where the semiconductor device according to the first embodiment and the semiconductor device according to the third embodiment are combined. is there. FIG. 5 is a schematic sectional configuration diagram of a semiconductor device according to the fourth embodiment of the present invention.
【００３１】図５に示すように、本実施の形態に係る半
導体装置は、凹部４Ｄを有する絶縁基板４を備え、この
絶縁基板４の凹部４Ｄに一部が埋設された電源板３の端
部と絶縁基板４との間に沿面破壊防止部材１１を配設す
る。電源板３の端部においては絶縁基板４に埋設された
部分と埋設されていない部分との境界付近の電界強度が
大きくなるので、この領域に沿面破壊防止部材１１が配
設される。沿面破壊防止部材１１には前述のようにエポ
キシ樹脂、ポリエステル樹脂、各種粉末が混入されたエ
ポキシ樹脂が実用的に使用できる。As shown in FIG. 5, the semiconductor device according to the present embodiment includes an insulating substrate 4 having a concave portion 4D, and an end portion of the power supply plate 3 partially buried in the concave portion 4D of the insulating substrate 4. A creepage prevention member 11 is disposed between the insulating substrate 4 and the insulating substrate 4. At the end of the power supply plate 3, the electric field strength near the boundary between the portion buried in the insulating substrate 4 and the portion not buried becomes large, so that the creeping breakdown prevention member 11 is provided in this region. As described above, an epoxy resin, a polyester resin, or an epoxy resin mixed with various powders can be practically used for the creeping fracture prevention member 11.
【００３２】なお、本発明は前述の実施の形態に限定さ
れない。例えば、本発明は、第２の実施の形態に係る半
導体装置と第３の実施の形態に係る半導体装置とを組み
合わせることもでき、少なくとも絶縁基板４の凹部４Ｄ
に一部が埋設された電源板３の端部を被覆するように各
種粉末を沈降させ硬化させたシリコーンゲルからなる沿
面破壊防止部材１２を形成してもよい。The present invention is not limited to the above embodiment. For example, according to the present invention, the semiconductor device according to the second embodiment and the semiconductor device according to the third embodiment can be combined.
A creeping prevention member 12 made of silicone gel in which various powders are settled and cured so as to cover the end of the power supply plate 3 partially embedded in the power supply plate 3 may be formed.
【００３３】さらに、本発明は、半導体装置の電源板３
にアルミニウム板（アルミニウム箔）を使用することが
できる。Further, the present invention relates to a power supply plate 3 for a semiconductor device.
An aluminum plate (aluminum foil) can be used.
【００３４】[0034]
【発明の効果】本発明は、電源板端部において絶縁基板
と充填材との間の界面に沿面放電が発生することを防
ぎ、沿面破壊の発生を防止することにより、絶縁破壊に
対する信頼性を向上させることができる半導体装置を提
供することができる。As described above, according to the present invention, it is possible to prevent the occurrence of creeping discharge at the interface between the insulating substrate and the filler at the end of the power supply plate, and to prevent the occurrence of creeping breakdown, thereby improving the reliability against breakdown. A semiconductor device which can be improved can be provided.
【図１】本発明の第１の実施の形態に係る半導体装置の
概略断面構成図である。FIG. 1 is a schematic cross-sectional configuration diagram of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施の形態に係る電界分布図で
ある。FIG. 2 is an electric field distribution diagram according to the first embodiment of the present invention.
【図３】本発明の第２の実施の形態に係る半導体装置の
概略断面構成図である。FIG. 3 is a schematic sectional configuration diagram of a semiconductor device according to a second embodiment of the present invention.
【図４】本発明の第３の実施の形態に係る半導体装置の
概略断面構成図である。FIG. 4 is a schematic sectional configuration diagram of a semiconductor device according to a third embodiment of the present invention.
【図５】本発明の第４の実施の形態に係る半導体装置の
概略断面構成図である。FIG. 5 is a schematic sectional configuration diagram of a semiconductor device according to a fourth embodiment of the present invention.
１ 半導体素子 ２ リード線 ３ 電源板 ４ 絶縁基板 ４Ｄ 凹部 ４Ｗ 側壁 ５ 外部接続リード線 ６ 放熱板 ７ ケース ８ 封止部材 ９ ターミナルホルダ １０ 充填材 １１，１２ 沿面破壊防止部材 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Lead wire 3 Power supply board 4 Insulating board 4D Depression 4W Side wall 5 External connection lead wire 6 Heat sink 7 Case 8 Sealing member 9 Terminal holder 10 Filler 11, 12 Creepage prevention member
───────────────────────────────────────────────────── フロントページの続き (72)発明者 清水 敏夫 東京都府中市東芝町１番地 株式会社東芝 府中工場内 (72)発明者 木島 研二 東京都府中市東芝町１番地 株式会社東芝 府中工場内 (72)発明者 佐藤 和弘 東京都府中市東芝町１番地 株式会社東芝 府中工場内 Ｆターム(参考） 4M109 AA01 BA03 CA02 EA02 EA10 EC07 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshio Shimizu 1 Toshiba-cho, Fuchu-shi, Tokyo Inside the Toshiba Fuchu Plant, Inc. 72) Inventor Kazuhiro Sato 1 Toshiba-cho, Fuchu-shi, Tokyo F-term in the Fuchu factory of Toshiba Corporation (reference) 4M109 AA01 BA03 CA02 EA02 EA10 EC07
Claims (5)
被覆する充填材と、 前記電源板端部と絶縁基板との間に配設され、前記充填
材よりも破壊電圧が高く、充填材よりも絶縁基板との接
着力が高い沿面破壊防止部材と、 を備えたことを特徴とする半導体装置。A power supply plate on which a semiconductor element is mounted; an insulating substrate on which the power supply plate is mounted; a filler covering respective surfaces of the semiconductor element, the power supply plate, and the insulating substrate; And a creepage prevention member disposed between the insulating substrate and the insulating substrate and having a higher breakdown voltage than the filler and having a higher adhesive strength to the insulating substrate than the filler.
て比誘電率の高い材料で形成されたことを特徴する請求
項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the creepage prevention member is formed of a material having a higher dielectric constant than a filler.
率を高める粉末を沈降させ硬化させたシリコーンゲルで
あることを特徴とする請求項１又は請求項２に記載の半
導体装置。3. The filling material is a silicone gel, and the creepage prevention member is a silicone gel in which a powder for increasing a dielectric constant is settled and hardened on a bottom portion of the filling material. 3. The semiconductor device according to claim 1 or 2.
至（Ｈ）の少なくともいずれか１つであることを特徴す
る請求項１乃至請求項３のいずれかに記載の半導体装
置。 （Ａ）エポキシ樹脂 （Ｂ）酸化アルミニウムの粉末を混入させたエポキシ樹
脂 （Ｃ）窒化アルミニウムの粉末を混入させたエポキシ樹
脂 （Ｄ）雲母の粉末を混入させたエポキシ樹脂 （Ｅ）ポリエステル樹脂 （Ｆ）酸化アルミニウムの粉末を混入させたシリコーン
ゲル （Ｇ）窒化アルミニウムの粉末を混入させたシリコーン
ゲル （Ｈ）雲母の粉末を混入させたシリコーンゲル4. The semiconductor device according to claim 1, wherein the creepage prevention member is at least one of the following (A) to (H). (A) Epoxy resin (B) Epoxy resin mixed with aluminum oxide powder (C) Epoxy resin mixed with aluminum nitride powder (D) Epoxy resin mixed with mica powder (E) Polyester resin (F ) Silicone gel mixed with aluminum oxide powder (G) Silicone gel mixed with aluminum nitride powder (H) Silicone gel mixed with mica powder
側壁で覆う凹部を有する絶縁基板と、 前記半導体素子、電源板、絶縁基板のそれぞれの表面を
被覆する充填材と、 を備えたことを特徴とする半導体装置。5. A power supply board on which a semiconductor element is mounted; an insulating substrate having a recess accommodating the power supply board and covering at least a part of an end of the power supply board with a side wall; A semiconductor device, comprising: a filler that covers each surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32406798A JP3703978B2 (en) | 1998-11-13 | 1998-11-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32406798A JP3703978B2 (en) | 1998-11-13 | 1998-11-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000150724A true JP2000150724A (en) | 2000-05-30 |
| JP3703978B2 JP3703978B2 (en) | 2005-10-05 |
Family
ID=18161788
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32406798A Expired - Fee Related JP3703978B2 (en) | 1998-11-13 | 1998-11-13 | Semiconductor device |
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| Country | Link |
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| JP (1) | JP3703978B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010064565A1 (en) * | 2008-12-05 | 2010-06-10 | 三菱重工業株式会社 | Inverter-integrated electric compressor and inverter device thereof |
| WO2013080749A1 (en) * | 2011-11-29 | 2013-06-06 | 日立オートモティブシステムズ株式会社 | Electronic module |
| JP2014157924A (en) * | 2013-02-15 | 2014-08-28 | Fuji Electric Co Ltd | Semiconductor device manufacturing method |
| JP2015198227A (en) * | 2014-04-03 | 2015-11-09 | 富士電機株式会社 | semiconductor device |
| US9704768B2 (en) | 2013-12-17 | 2017-07-11 | Mitsubishi Electric Corporation | Power semiconductor module |
| JP2018098442A (en) * | 2016-12-16 | 2018-06-21 | 富士電機株式会社 | Semiconductor device |
| DE112017007351B4 (en) | 2017-03-29 | 2023-02-23 | Mitsubishi Electric Corporation | POWER SEMICONDUCTOR MODULE |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6540324B2 (en) | 2015-07-23 | 2019-07-10 | 富士電機株式会社 | Semiconductor module and method of manufacturing semiconductor module |
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1998
- 1998-11-13 JP JP32406798A patent/JP3703978B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010064565A1 (en) * | 2008-12-05 | 2010-06-10 | 三菱重工業株式会社 | Inverter-integrated electric compressor and inverter device thereof |
| JP2010133366A (en) * | 2008-12-05 | 2010-06-17 | Mitsubishi Heavy Ind Ltd | Inverter-integrated electric compressor and inverter device thereof |
| US8717765B2 (en) | 2008-12-05 | 2014-05-06 | Mitsubishi Heavy Industries, Ltd. | Integrated-inverter electric compressor and inverter unit thereof |
| WO2013080749A1 (en) * | 2011-11-29 | 2013-06-06 | 日立オートモティブシステムズ株式会社 | Electronic module |
| JP2014157924A (en) * | 2013-02-15 | 2014-08-28 | Fuji Electric Co Ltd | Semiconductor device manufacturing method |
| US9704768B2 (en) | 2013-12-17 | 2017-07-11 | Mitsubishi Electric Corporation | Power semiconductor module |
| JP2015198227A (en) * | 2014-04-03 | 2015-11-09 | 富士電機株式会社 | semiconductor device |
| JP2018098442A (en) * | 2016-12-16 | 2018-06-21 | 富士電機株式会社 | Semiconductor device |
| DE112017007351B4 (en) | 2017-03-29 | 2023-02-23 | Mitsubishi Electric Corporation | POWER SEMICONDUCTOR MODULE |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3703978B2 (en) | 2005-10-05 |
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