JP2000150678A5 - - Google Patents
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- JP2000150678A5 JP2000150678A5 JP1998319415A JP31941598A JP2000150678A5 JP 2000150678 A5 JP2000150678 A5 JP 2000150678A5 JP 1998319415 A JP1998319415 A JP 1998319415A JP 31941598 A JP31941598 A JP 31941598A JP 2000150678 A5 JP2000150678 A5 JP 2000150678A5
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- gate
- side wall
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Description
【請求項１７】 半導体基板の主表面に設けられた第１ゲート絶縁膜と、
その上に形成された第１ゲート電極と、
前記第１ゲート電極の上に第２ゲート絶縁膜を介して形成された第２ゲート電極と、
前記第２ゲート電極の側壁に形成された保護膜とを備えている不揮発性半導体記憶装置。
17. A first gate insulating film provided on the main surface of a semiconductor substrate, and
The first gate electrode formed on it and
A second gate electrode formed on the first gate electrode via a second gate insulating film,
A non-volatile semiconductor storage device including a protective film formed on the side wall of the second gate electrode.
【請求項１８】 半導体基板の主表面に設けられた第１ゲート絶縁膜と、
その上に形成された第１ゲート電極と、
前記第１ゲート電極の上に第２ゲート絶縁膜を介して形成された第２ゲート電極と、
前記第１ゲート電極の側壁に接する絶縁膜と第１ゲート絶縁膜とが形成する段差側壁に、多結晶シリコンが絶縁体化されたシリコン化合物とを有する不揮発性半導体記憶装置。
18. A first gate insulating film provided on the main surface of a semiconductor substrate,
The first gate electrode formed on it and
A second gate electrode formed on the first gate electrode via a second gate insulating film,
Wherein the insulating film and the step sidewall and to form the first gate insulating film in contact with the side wall of the first gate electrode, the nonvolatile semiconductor memory device having a silicon compound polycrystalline silicon is insulated embodied.
【請求項１９】 半導体基板の上に、第１ゲート絶縁膜を介して第１ゲート層がエッチングされることにより形成された第１ゲート電極と、
その第１ゲート電極の上に、第２ゲート絶縁膜を介して第２ゲート層がエッチングされることにより形成された第２ゲート電極とを備えた不揮発性半導体記憶装置であって、
前記第１ゲート電極の側壁が接する絶縁膜と前記第１ゲート絶縁膜とによって形成される角度が、前記第１ゲート電極の側壁に沿って延びる方向に直交する断面で、前記第１ゲート電極側に対して９０°を超え、前記第１ゲート電極の側壁が接する絶縁膜の両側壁の各々には、前記第１ゲート電極の幅が上方ほど広くなるようにテーパがつけられている不揮発性半導体記憶装置。
To 19. On the semiconductor substrate, a first gate electrode a first gate layer through the first gate insulating film is formed by etching,
Over the first gate electrode, the second gate layer through the second gate insulating film is a non-volatile semiconductor memory device having a second gate electrode which is formed by etching,
The angle formed by the insulating film in contact with the side wall of the first gate electrode and the first gate insulating film is a cross section orthogonal to the direction extending along the side wall of the first gate electrode, and is on the side of the first gate electrode. A non-volatile semiconductor that exceeds 90 ° and is tapered so that the width of the first gate electrode becomes wider toward the upper side on each of the side walls of the insulating film in contact with the side wall of the first gate electrode. Storage device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10319415A JP2000150678A (en) | 1998-11-10 | 1998-11-10 | Nonvolatile semiconductor memory and fabrication thereof |
| US09/286,421 US6228712B1 (en) | 1998-11-10 | 1999-04-06 | Non-volatile semiconductor memory device and manufacturing method thereof |
| US09/790,700 US6452226B2 (en) | 1998-11-10 | 2001-02-23 | Non-volatile semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10319415A JP2000150678A (en) | 1998-11-10 | 1998-11-10 | Nonvolatile semiconductor memory and fabrication thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000150678A JP2000150678A (en) | 2000-05-30 |
| JP2000150678A5 true JP2000150678A5 (en) | 2005-12-22 |
Family
ID=18109947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10319415A Pending JP2000150678A (en) | 1998-11-10 | 1998-11-10 | Nonvolatile semiconductor memory and fabrication thereof |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US6228712B1 (en) |
| JP (1) | JP2000150678A (en) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6238998B1 (en) * | 1998-11-20 | 2001-05-29 | International Business Machines Corporation | Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall |
| JP3345880B2 (en) * | 1999-06-29 | 2002-11-18 | 日本電気株式会社 | Semiconductor device including non-volatile memory cell and field effect transistor and method of manufacturing the same |
| TW552669B (en) * | 2000-06-19 | 2003-09-11 | Infineon Technologies Corp | Process for etching polysilicon gate stacks with raised shallow trench isolation structures |
| US6569735B2 (en) * | 2001-03-20 | 2003-05-27 | Macronix International Co., Ltd. | Manufacturing method for isolation on non-volatile memory |
| US6699777B2 (en) * | 2001-10-04 | 2004-03-02 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
| US6677211B2 (en) * | 2002-01-14 | 2004-01-13 | Macronix International Co., Ltd. | Method for eliminating polysilicon residue |
| JP2003258132A (en) | 2002-03-05 | 2003-09-12 | Seiko Epson Corp | Manufacturing method of non-volatile memory device |
| JP2004031546A (en) * | 2002-06-25 | 2004-01-29 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| US6841824B2 (en) | 2002-09-04 | 2005-01-11 | Infineon Technologies Ag | Flash memory cell and the method of making separate sidewall oxidation |
| US20040209468A1 (en) * | 2003-04-17 | 2004-10-21 | Applied Materials Inc. | Method for fabricating a gate structure of a field effect transistor |
| US6777299B1 (en) | 2003-07-07 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for removal of a spacer |
| US7508075B2 (en) * | 2003-08-01 | 2009-03-24 | Micron Technology, Inc. | Self-aligned poly-metal structures |
| US7091098B2 (en) * | 2004-04-07 | 2006-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with spacer having batch and non-batch layers |
| US6984563B1 (en) * | 2004-07-01 | 2006-01-10 | Fasl Llc | Floating gate semiconductor component and method of manufacture |
| US7425482B2 (en) * | 2004-10-13 | 2008-09-16 | Magna-Chip Semiconductor, Ltd. | Non-volatile memory device and method for fabricating the same |
| US20060102197A1 (en) * | 2004-11-16 | 2006-05-18 | Kang-Lie Chiang | Post-etch treatment to remove residues |
| KR100684452B1 (en) | 2004-12-29 | 2007-02-16 | 동부일렉트로닉스 주식회사 | Method for etching the dielectric layer of flash memory device |
| JP4649265B2 (en) * | 2005-04-28 | 2011-03-09 | 株式会社東芝 | Method for manufacturing nonvolatile semiconductor memory device |
| US7679130B2 (en) | 2005-05-10 | 2010-03-16 | Infineon Technologies Ag | Deep trench isolation structures and methods of formation thereof |
| JP2007005380A (en) * | 2005-06-21 | 2007-01-11 | Toshiba Corp | Semiconductor device |
| US20070004141A1 (en) * | 2005-07-04 | 2007-01-04 | Hynix Semiconductor Inc. | Method of manufacturing flash memory device |
| JP2007188961A (en) * | 2006-01-11 | 2007-07-26 | Toshiba Corp | Semiconductor memory device, and method of manufacturing same |
| US7535060B2 (en) * | 2006-03-08 | 2009-05-19 | Freescale Semiconductor, Inc. | Charge storage structure formation in transistor with vertical channel region |
| JP2009231592A (en) * | 2008-03-24 | 2009-10-08 | Nec Electronics Corp | Method for manufacturing semiconductor device |
| KR100981530B1 (en) * | 2008-05-26 | 2010-09-10 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| KR101085620B1 (en) * | 2009-06-25 | 2011-11-22 | 주식회사 하이닉스반도체 | Manufacturing method of gate pattern for nonvolatile memory device |
| JP5621381B2 (en) | 2010-07-28 | 2014-11-12 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| CN102420193B (en) * | 2010-09-25 | 2013-07-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of memory device |
| KR20120089513A (en) * | 2010-12-13 | 2012-08-13 | 삼성전자주식회사 | Non-volatile memory devices and methods of fabricating the same |
| US8389356B2 (en) * | 2011-03-10 | 2013-03-05 | Wafertech, Llc | Flash cell with floating gate transistors formed using spacer technology |
| KR20120120729A (en) * | 2011-04-25 | 2012-11-02 | 에스케이하이닉스 주식회사 | Method for manufacturing metal pattern in semiconductor device |
| US20140306286A1 (en) * | 2013-04-10 | 2014-10-16 | International Business Machines Corporation | Tapered fin field effect transistor |
| JP6188503B2 (en) | 2013-09-06 | 2017-08-30 | キヤノン株式会社 | Recording element substrate, manufacturing method thereof, recording head, and recording apparatus |
| CN104752360B (en) * | 2013-12-30 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | memory device and forming method thereof |
| CN111430357B (en) * | 2020-04-10 | 2023-07-04 | 长江存储科技有限责任公司 | Forming method of three-dimensional memory |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0817235B2 (en) * | 1990-08-29 | 1996-02-21 | 株式会社東芝 | Offset gate structure transistor and manufacturing method thereof |
| US5342801A (en) * | 1993-03-08 | 1994-08-30 | National Semiconductor Corporation | Controllable isotropic plasma etching technique for the suppression of stringers in memory cells |
| JP3675500B2 (en) * | 1994-09-02 | 2005-07-27 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| JPH08148584A (en) | 1994-11-22 | 1996-06-07 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JPH10107163A (en) | 1996-09-27 | 1998-04-24 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacturing method |
| US5973353A (en) * | 1997-12-18 | 1999-10-26 | Advanced Micro Devices, Inc. | Methods and arrangements for forming a tapered floating gate in non-volatile memory semiconductor devices |
-
1998
- 1998-11-10 JP JP10319415A patent/JP2000150678A/en active Pending
-
1999
- 1999-04-06 US US09/286,421 patent/US6228712B1/en not_active Expired - Lifetime
-
2001
- 2001-02-23 US US09/790,700 patent/US6452226B2/en not_active Expired - Lifetime
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