JP2000150654A - Semiconductor device and its wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase in wiring capacity even if a wiring space becomes larger when air void process is applied by placing dummy wiring between signal lines and forming air voids between the signal lines and the dummy wiring. SOLUTION: GDL, GDC and GDR are driving gates. GFL, GFC and GFL are load gates. The driving gates and the load gates are respectively connected by signal lines WL, WC and WR. Dummy lines D1 and D2 in floating state are placed in a position between the lines WL and WC or between the lines WC and WR. Accordingly, large air voids are formed respectively between the lines WL and D1, D1 and WC, WC and D2, and D2 and WL. In this way, effective relative dielectric constant can be reduced and wiring capacity can be also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a wiring method thereof, and more particularly, to a semiconductor device and a wiring method thereof for a CMOS LSI wiring process.

[0002]

2. Description of the Related Art CMOSL of Deep Submicron and Later
In the wiring process of SI, the interlayer insulating film was not buried between the wirings for the purpose of reducing the wiring capacity.
The air void process holds promise. A representative example thereof is, for example, EDL (IEEE Electro
n Devices Letters, Vol. 19, No. 1,
On pages 16-18. The air void process is a process that actively utilizes the fact that the interlayer insulating film is less likely to be buried in a portion where the wiring space is extremely narrow. Since the relative permittivity k of the air void formed between the wirings is 1, for example, a 0.25 μm CMOS
The inter-wiring capacitance is greatly reduced as compared with the case where an interlayer insulating film having a relative dielectric constant k of 3.5 used in the next generation is used.

[0003]

However, the conventional air void process has the following problems. FIG. 8 is a diagram schematically showing a conventional air void process. In the conventional semiconductor device shown in FIG.
1 denotes an interlayer insulating film, 2 denotes a plurality of Al wirings, and 3 denotes an air void between the wirings. FIG. 8A shows the shape of the air void when the wiring space is narrow (wiring space = wiring width), and FIG. 8B shows the air void when the wiring space is medium (wiring space = wiring width × 3). FIG. 4C shows the shape of the air void when the wiring space is large.

As shown in FIG. 8A, when the space between the wirings 2 is narrow (wiring space = wiring width), the ratio of the air voids 3 to the space between the wirings and the size of the space are large. However, as shown in FIG. 8B, when the space between the wirings 2 becomes medium (wiring space = wiring width × 3), the ratio of the air voids 3 between the wirings and the size of the space are reduced. It becomes smaller than the case of (a). Further, as shown in FIG. 8C, when the space between the wirings 2 becomes very large, the air void itself is not finally formed.

[0005] The phenomenon is quantitatively analyzed as follows. Each dimension X characterizing the shape of the air void 3,
Y1 and Y2 are defined as shown in FIGS. 9A shows a case where the space between the wirings 2 is narrow (wiring space = wiring width), and FIG. 9B shows a case where the space between the wirings 2 is medium (wiring space = wiring width ×).
3). Here, X is the width of the air void 3, Y1, Y
2 is the length in the length direction of the air void 3 and the wiring 2
Is the dimension of the part exceeding the length of When the air void 3 becomes smaller, the values of Y1 and Y2 become negative as shown in FIG.

FIG. 10 shows the wiring space dependence of the dimensions X, Y1, and Y2 in the air void process. When calculation is performed based on this shape, a result as shown in FIG. 11 is obtained. That is, FIG. 11 shows the wiring space dependency of the wiring capacitance value in the case of using the interlayer insulating film having the relative dielectric constant k of 3.5 and in the case of the air void process. As can be seen from FIG. 11, according to the air void process, the wiring capacitance value is very small in a portion where the wiring space is narrow, but the wiring capacitance value increases as the wiring space becomes wider, and the wiring space becomes smaller (0.24 μm).
At about 0.75 μm, which is about three times as large as m), the wiring capacitance value becomes uniformly larger than when an interlayer insulating film having a relative dielectric constant k of 3.5 is used. Here, it is assumed that the air void process uses an interlayer insulating film having a relative dielectric constant k of 4.2.

Accordingly, an object of the present invention is to solve such a problem and to prevent the wiring capacitance value from increasing even when the wiring space is widened when an air void process is applied.

[0008]

According to the present invention, to achieve this object, a dummy wiring is provided between wirings serving as signal lines, and an air void is provided between the wirings serving as signal lines and the dummy wirings. It is formed. With such a configuration, a problem in the conventional air void process, an increase in the wiring capacity caused by the small or not formed air voids when the wiring space is large, by installing a dummy wiring between the wiring, This can be prevented by forming air voids.

[0009]

According to a first aspect of the present invention, a dummy wiring is provided between wirings serving as signal lines, and an air void is formed between the wirings serving as signal lines and the dummy wirings. It is. As a result, the problem of the conventional air void process, the increase in wiring capacity caused by the small or no air voids when the wiring space is large, is reduced by installing dummy wirings between wirings and forming air voids. This can be prevented.

According to a second aspect of the present invention, the dummy wiring is a wiring in a floating state.
As a result, the wiring capacitance can be reduced as compared with the case where the potential is fixed, and the increase in the device area can be prevented without restriction on the device layout. According to a third aspect of the present invention, the space between the signal lines is at least equal to the sum of the minimum design rule of the wiring width and twice the minimum design rule of the wiring space.

[0011] This makes it possible to clarify the standard of the method of installing the dummy wiring, and to easily cope with the DA tool. According to a fourth aspect of the present invention, the space between the wirings as signal lines is equal to or more than twice the minimum design rule of the wiring width and three times the minimum design rule of the wiring space,
In this case, two or more dummy wirings are provided.

[0012] This makes it possible to clarify the standard of the method of installing the dummy wiring, and to easily cope with the DA tool. According to a fifth aspect of the present invention, a space between a wiring serving as a signal line and a dummy wiring is made equal to a minimum design rule of a wiring space. Thereby, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be efficiently achieved.

According to the present invention, the space between the signal line wiring and the dummy wiring is a space where the capacitance between the signal line wiring and the dummy wiring is minimized. Things. Thereby, the formation of air voids between the wirings is optimized, so that the reduction of the wiring capacity can be achieved to the maximum.

According to a seventh aspect of the present invention, the air voids make up 50% or more of the volume between the wirings. This makes it possible to reduce the wiring capacitance value as compared with a case where no dummy wiring is provided, and to clarify the criteria for whether to install dummy wiring in the air void process.

According to the present invention, in a semiconductor device in which a first signal line and a second signal line are formed on both sides of a signal line of interest, the arrangement of the signal line of interest is changed. By arranging the floating dummy wiring in the wiring space between the signal line of interest and the first signal line whose arrangement has been changed, the space between the first signal line and the dummy wiring, the signal line of interest and the dummy wiring Are formed in the space between the target signal line and the space between the signal line of interest and the second signal line.

In this case, since air voids can be efficiently formed between the wirings, it is possible to efficiently reduce the wiring capacity, and at the same time, the signal line of interest is transmitted from the first signal line by a signal of crosstalk. Almost no interference. According to a ninth aspect of the present invention, the sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is determined by the minimum design rule of the wiring width and the wiring When the space is equal to or more than three times the minimum design rule of the space, the space between the first signal line and the dummy wiring, the space between the signal line of interest and the dummy wiring, and the signal line The space between the two signal lines is made equal to the minimum design rule of the wiring space.

In this case, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be efficiently achieved, and at the same time, the signal line of interest is transmitted from the first signal line by the signal of crosstalk. Almost no interference. According to a tenth aspect of the present invention, the sum of the wiring space between the target signal line and the first signal line and the wiring space between the target signal line and the second signal line is equal to the minimum design rule of the wiring width and the wiring width. When the space is equal to or more than three times the minimum design rule of the space, a space between the first signal line and the dummy wiring, a space between the signal line of interest and the dummy wiring,
The space between the signal line of interest and the second signal line is defined as a space where the capacitance is minimized.

In this case, since the formation of air voids between the wirings is optimized, the reduction of the wiring capacity can be achieved to the maximum. According to the present invention, in a semiconductor device in which a first signal line and a second signal line are formed on both sides of a signal line of interest, a wiring space between the signal line of interest and the first signal line is provided. In addition to disposing the first dummy wiring in the floating state, the arrangement of the signal line of interest is changed so that the second dummy wiring in the floating state can be arranged in the wiring space between the signal line of interest and the second signal line. By doing so, the space between the first signal line and the first dummy wiring, the space between the signal line of interest and the first dummy wiring, and the space between the signal line of interest and the second dummy wiring And the space between the second dummy wiring and the second signal line are formed with air voids.

In this case, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be efficiently achieved, and at the same time, the signal line of interest is the first signal line 1.
Also, signal interference due to crosstalk from the second signal line is hardly received. The present invention according to claim 12 is:
The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is twice the minimum design rule of the wiring width and the minimum design rule of the wiring space. When the sum is four times or more, the space between the first signal line and the first dummy wiring, the space between the signal line of interest and the first dummy wiring, and the signal line The space between the second dummy wiring and the space between the second dummy wiring and the second signal line are made equal to the minimum design rule of the wiring space.

In this case, since air voids can be efficiently formed between the wirings, it is possible to efficiently reduce the wiring capacity. According to a thirteenth aspect of the present invention, the sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is 2 which is the minimum design rule of the wiring width. The first signal line and the first signal line are connected to each other when the sum is equal to or more than twice the minimum design rule of the wiring space.
, A space between the signal line of interest and the first dummy line, a space between the signal line of interest and the second dummy line, a space between the second dummy line and the second dummy line.
And the space between these signal lines is the space where the capacitance is minimized.

In this case, since the formation of air voids between the wirings is optimized, the reduction of the wiring capacity can be achieved to the maximum. According to a fourteenth aspect of the present invention, in a semiconductor device having a first signal line and a second signal line formed on both sides of a signal line of interest, at least one of a wiring width of the signal line of interest and an arrangement thereof. By changing one of them, air voids are formed in the space between the first signal line and the signal line of interest and in the space between the signal line of interest and the second signal line, respectively. .

In this case, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be achieved efficiently. According to a fifteenth aspect of the present invention, the sum of the wiring space between the target signal line and the first signal line and the wiring space between the target signal line and the second signal line is 2 which is the minimum design rule of the wiring space. The space between the signal line of interest and the first signal line and the space between the signal line of interest and the second signal line are equal to the minimum design rule of the wiring space, respectively. It is.

In this case, since air voids can be efficiently formed between the wirings, the wiring capacity can be efficiently reduced, and at the same time, the space between the signal line of interest and the first signal line can be reduced. The space between the signal line of interest and the second signal line is made equal to the minimum design rule of the wiring space, thereby increasing the wiring width of the signal line of interest, thereby increasing the wiring interlayer capacitance. Since the rate of decrease in the wiring resistance is greater than the rate of increase in the wiring capacitance, when the wiring delay accounts for most of the entire delay, the wiring delay can be greatly reduced and high speed can be achieved.

According to a sixteenth aspect of the present invention, the sum of the wiring space between the target signal line and the first signal line and the wiring space between the target signal line and the second signal line is a minimum design of the wiring space. More than twice the rule, the signal line of interest and the first
And the space between the signal line of interest and the second signal line are spaces where the capacitance is minimized.

In this case, since the formation of air voids between the wirings is optimized, the reduction of the wiring capacity can be achieved to the maximum. According to the present invention, in a semiconductor device in which a first signal line and a second signal line are formed on both sides of a signal line of interest, a wiring space between the signal line of interest and the first signal line is reduced. When the sum of the wiring space of the signal line of interest and the second signal line is twice or more the minimum design rule of the wiring space, the arrangement of the signal line of interest is changed to the first signal line. The space between the signal line of interest and the space between the signal line of interest and the second signal line are respectively defined as the wiring space between the signal line of interest and the first signal line before the layout change, and the space before the layout change. Equal to half the sum of the wiring space between the signal line of interest and the second signal line, and the space between the signal line of interest and the signal line of interest and the signal line of interest and the second signal line. An air void is formed in each of the spaces therebetween.

With this arrangement, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be efficiently achieved, and the signal lines of interest are the first signal lines and the second signal lines. , The probability of receiving signal interference due to crosstalk can be equalized. According to the present invention, an air void is formed so as to make up 50% or more of the volume between wirings.

This makes it possible to reduce the wiring capacitance value as compared with the case where no dummy wiring is provided, and to clarify the criteria for whether or not dummy wiring is provided in the air void process. Hereinafter, a semiconductor device and a wiring method thereof according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of a semiconductor device according to an embodiment of the present invention and a sectional view thereof. In FIG. 1, GDL, GDC, and GDR are drive gates, and GF
L, GFC, and GFR are load gates. Each drive gate GDL, GDC, GDR and each load gate GFL, GF
C and GFR are signal lines WL and W, respectively.
C, connected by WR.

At a position between the wiring WL and the wiring WC, a floating dummy wiring D1 is provided. Further, at a position sandwiched between the wiring WC and the wiring WR,
The floating dummy wiring D2 is provided. Here, the floating state refers to a state in which neither the power supply line nor the ground line is electrically connected. Here, the gate of interest considering the delay time is the drive gate GDC, and the wiring of interest is WC. Also here, CMO
It is assumed that an air void process in which an interlayer insulating film is not buried between wirings is used as a wiring process of the SLSI when a space between the wirings is small.

FIG. 7 shows a circuit diagram of a conventional semiconductor device to be compared with the present invention and a cross-sectional view of the circuit. In this conventional device, the floating dummy wirings D1 and D2 as in the present invention are not provided. According to the present invention, by providing the wirings D1 and D2 in a floating state, the wirings D1 and D2, the wiring D1 and the wiring WC, the wiring WC and the wiring D2, the wiring D2 and the wiring WR
In between, large air voids are formed.
Therefore, the wiring capacitance between the respective wirings has a very small value. The wiring capacitance between the wiring WC and the wiring WL is the wiring capacitance between the wiring WL and the wiring D1, and the wiring capacitance between the wiring D1 and the wiring W.
It becomes a series capacitance with the wiring capacitance between the capacitors C and C. Similarly, the wiring capacitance between the wiring WC and the wiring WR is equal to the wiring WC and the wiring D
2 and a line capacitance between the line D2 and the line WR.

At this time, it is desirable that the wirings D1 and D2 are in a floating state as described above. That is, if the potential is fixed, the wiring capacitance of the wiring WC is equal to the wiring capacitance between the wiring WC and the wiring D1 and the wiring W
This is because the sum of the wiring capacitance between C and the wiring D2 is larger than that in the floating state. Further, fixing the potential imposes restrictions on the layout, which may increase the area.

As described above, the problem with the conventional air void process, that is, the increase in the wiring capacitance caused by the small or no air void when the wiring space is large, is caused by inserting a dummy wiring between the wirings. This can be prevented. That is, by inserting the dummy wiring between the wirings, a large air void can be formed between the wirings, thereby reducing the effective relative permittivity. Moreover, by setting the inserted dummy wiring in a floating state, the wiring capacity can be reduced. At this time, it is preferable that the voids of air make up 50% or more of the volume between the wirings. Otherwise, the effect of improving the wiring capacitance value is increased by increasing the wiring space, and the effect of the present invention by installing the dummy wiring is likely to be reduced.

FIG. 2 shows the dependence of the gate delay on the wiring space. That is, a comparison is made between a conventional case using an interlayer insulating film having a relative dielectric constant of 3.5 uniformly and a case using an air void process. In the air void process, when the wiring space is large (the wiring space is three times or more the wiring width), the conventional normal case, the case where the power supply line is inserted as the dummy wiring based on the present invention, and the present invention Comparison is made between the case where a floating wiring is inserted as the original dummy wiring and the case where a floating wiring is inserted. FIG. 3 is a cross-sectional view of the wiring in each case, and the power supply lines are denoted by VDD1 and VDD2. As can be seen from FIG. 2, when the wiring space is large, by arranging the dummy wiring between the signal wirings, the effective wiring capacitance can be greatly reduced, and the gate delay can be greatly reduced. In particular, by providing a floating dummy wiring, the effective wiring capacitance can be further reduced, and the gate delay can be further reduced.

Next, a specific example will be described in which the method of inserting a dummy wiring according to the present invention is applied to a DA tool. FIG. 4 shows a method of inserting a floating dummy pattern between two signal wirings. In FIG.
1 is a first signal wiring, W2 is a second signal wiring, D and D
Reference numerals 1 and 2 denote dummy wirings, respectively. Also, Lw1
Is the wiring width of the signal wiring W1, Lw2 is the wiring width of the signal wiring W2, Sw is the wiring space between the signal wirings W1 and W2, Ld
Represents the wiring width of the dummy wiring D, Lmin represents the minimum design rule of the wiring width, and Smin represents the dimension of the minimum design rule of the wiring space.

The wiring space Sw between the signal wirings W1 and W2
According to the size of the dummy pattern, the method of inserting the dummy pattern can be basically classified into four patterns shown in FIGS. As shown in FIG. 4A, the wiring space Sw between the signal wirings is just the minimum design rule Lm of the wiring width.
2 and minimum design rule Smin of wiring space
In the case of the sum with the double, that is, Sw = Lmin + 2
If it is Smin, the minimum design rule Lmin
Of the dummy wiring D having a width of the signal wiring W1 and the signal wiring W2.
And place it in the middle. Wiring space Sw between signal wiring
Is smaller than the sum of the minimum design rule Lmin of the wiring width and twice the minimum design rule Smin of the wiring space, the dummy wiring cannot be arranged. Therefore, in this case (A), can the dummy wiring be arranged? It becomes a standard of whether or not.

As shown in FIG. 4B, when the wiring space Sw between signal wirings is equal to or more than the sum of the minimum wiring width design rule Lmin and twice the minimum wiring space design rule Smin, the minimum A dummy wiring D having a width Ld equal to or larger than the design rule Lmin is arranged in the middle between the signal wiring W1 and the signal wiring W2. By arranging the dummy wiring D having a width Ld equal to or more than Lmin, the space between the signal wiring W1 and the dummy wiring D and the space between the dummy wiring D and the signal wiring W2 are each minimized. The design rule Smin is set. Thereby, since an air void can be efficiently formed between the wirings W1, D, and W2, the reduction of the wiring capacity can be efficiently achieved. However, in this case, Lmin + 2Smin
≦ Sw ≦ 2Lmin + 3Smin and Lmin ≦ Ld
It is necessary to satisfy the condition of ≦ 2Lmin + Smin.

As shown in FIG. 4C, the wiring space Sw between the signal wirings is just the minimum design rule L of the wiring width.
twice the minimum and the minimum design rule Sm for the wiring space
In the case of the sum of three times in, that is, Sw = 2L
In the case of min + 3Smin, two dummy wirings D1 and D2 having a width of the minimum design rule Lmin are arranged between the signal wiring W1 and the signal wiring W2. At this time, a space between the signal wiring W1 and the dummy wiring D,
A space between the dummy wiring D1 and the dummy wiring D2,
The space between the dummy wiring D2 and the signal wiring 2 is set to the minimum design rule Smin of the wiring space. This case (C) is a reference for determining whether two dummy wirings can be arranged.

As shown in FIG. 4D, the wiring space Sw between the signal wirings is twice the minimum design rule Lmin of the wiring width and three times the minimum design rule Smin of the wiring space.
If the sum is twice or more, that is, Sw ≧ 2Lmin
+ 3Smin, the minimum design rule Lm
Two dummy wirings D1 and D2 having a width of in are arranged between the signal wiring W1 and the signal wiring W2. At this time, the space between the signal wiring W1 and the dummy wiring D1 and the space between the dummy wiring D2 and the signal wiring W2 are set to the minimum design rule Smin of the wiring space. Therefore, in this case, the space between the dummy wiring D1 and the dummy wiring D2 is larger than the minimum design rule Smin of the wiring space.

In this case, the dummy wiring D1 and the dummy wiring D
2 is the minimum design rule Lmi of the wiring width.
The reason is that the dummy wirings D1 and D2
This is for minimizing the wiring interlayer capacitance between the upper and lower wirings. In the case of FIG. 4D, when the space between the dummy wiring D1 and the dummy wiring D2 is equal to or more than the sum of the minimum design rule Lmin of the wiring width and twice the minimum design rule Smin of the wiring space. There is no particular problem even if a new dummy wiring is inserted. However, the insertion of the new dummy wiring should be performed only when there is a condition in which the insertion of the dummy wiring is more desirable in the process than the increase of the wiring capacitance.

The two signal wirings W shown in FIG.
1, floating dummy patterns D, D between W2
In the insertion of 1, D2, Smin was defined by the minimum design rule of the wiring space. However, depending on the cases (A) to (D), Smin minimizes the capacitance between the signal line wiring and the dummy wiring. Sometimes it is best to define it as a space.

The air voids can be efficiently formed between the wirings W1, W2, D, D1, and D2 by the method described above with reference to FIGS. 4A to 4D, so that the wiring capacity can be reduced efficiently. Can be achieved. FIG. 5 shows a method of inserting a floating dummy pattern in the case where there are signal wirings on both sides of a signal wiring of interest.

In FIG. 5, WC is a signal wiring of interest, WL
Indicates a signal wiring on the left side of the signal line of interest WC, WR indicates a signal line on the right side of the signal line of interest WC, and D, D1, and D2 indicate dummy lines. Lwc is the signal line of interest WC
Lwl is the wiring width of the signal wiring WL, Lwr is the wiring width of the signal wiring WR, Sw1 is the wiring space between the signal wiring WC and the signal wiring WL, Sw2 is the wiring space between the signal wiring WC and the signal wiring WR, Ld and Ld1 are the wiring width of the dummy wiring, Lmin is the minimum design rule of the wiring width, Sm
"in" indicates the dimension of the minimum design rule of the wiring space.

Wiring spaces Sw1 and Sw2 between signal wirings
According to the magnitude of the sum of the above, the method of inserting the dummy pattern can be basically classified into the four patterns shown in FIGS. As shown in FIG. 5A, when the sum of the wiring spaces Sw1 and Sw2 between the signal wirings is exactly the sum of the minimum design rule Lmin of the wiring width and three times the minimum design rule Smin of the wiring space, ie, S
In the case where w1 + Sw2 = Lmin + 3Smin, and when Sw1 and Sw2 are each larger than Smin, the dummy wiring D having the width of the minimum design rule Lmin can be arranged in the wiring space between the target signal line WC and the signal line WL. Thus, the arrangement of the signal line of interest WC is changed, and the dummy wiring D is arranged in the wiring space between the signal line of interest WC and the signal line WL. At this time, the space between the signal line WL and the dummy wiring D, the space between the signal line WC of interest and the dummy wiring D, and the space between the signal line WC of interest and the signal line WR are respectively wiring spaces. Minimum design rule S
min.

At this time, the dummy wiring D is arranged in the wiring space between the target signal line WC and the signal line WR in the same manner as the dummy wiring D is disposed in the wiring space between the target signal line WC and the signal line WL as shown in the figure. Is also good. The two types of arrangement are preferably selected in consideration of which of the signal line WL and the signal line WR receives signal interference due to crosstalk from the signal line WC.

Here, signal interference due to crosstalk will be supplementarily described. Because the potential of the signal line changes transiently,
The signal line of interest WC is affected by the signal line whose potential fluctuates transiently via the capacitance between the wirings. Attention signal line W
When the potential of C is not fluctuating, this attention signal line W
Affected as noise to C. If this noise is large, the logic gate malfunctions. On the other hand, when the potential of the signal line of interest WC fluctuates, it is affected as a delay fluctuation of the signal line of interest. If the potential fluctuations of the signal line WC of interest and the other signal lines WL, WR have the same phase, the wiring capacitance between the signal line WC of interest and the other signal lines WL, WR is apparently small, so that the signal line of interest The gate delay of the WC is small. On the other hand, the signal line WC of interest and another signal line W
If the potential fluctuations of L and WR have different phases, the wiring delay between the signal line of interest WC and the other signal lines WL and WR becomes apparently large, so that the gate delay of the signal line of interest WC becomes large. When the gate delay is increased due to the delay variation, the operating frequency of the actually manufactured chip becomes lower than the operating frequency predicted at the time of design, which poses a serious problem.

As shown in FIG. 5B, the sum of the wiring spaces Sw1 and Sw2 between the signal wirings is the minimum design rule Lmin of the wiring width and the minimum design rule S of the wiring space.
Sw1 and Sw2 when the sum is equal to or more than three times the minimum
Are greater than Smin, the signal line of interest WC
Is changed, and a dummy wiring D having a width Ld larger than the minimum design rule Lmin is arranged in the wiring space between the target signal line WC and the signal line WL. At this time, a space between the signal line WL and the dummy wiring D, a space between the signal line WC of interest and the dummy wiring D, and a signal line W of interest.
The space between C and the signal line WR is the minimum design rule Smin of the wiring space. As a result, air voids can be efficiently formed between the wirings,
It is possible to efficiently reduce the wiring capacitance. However, in this case, Lmin + 3Smin ≦ Sw1 + Sw
2 ≦ 2Lmin + 4Smin and Lmin ≦ Ld ≦ 2
It is necessary to satisfy the condition of Lmin + Smin.

As shown in FIG. 5C, the sum of the wiring spaces Sw1 and Sw2 between the signal wirings is exactly twice the minimum design rule Lmin of the wiring width and four times the minimum design rule Smin of the wiring space. When the sum is obtained, that is, when Sw1 + Sw2 = 2Lmin + 4Smin, and when Sw1 and Sw2 are each greater than Smin, the dummy wiring having the width of the minimum design rule Lmin is provided in the wiring space between the target signal line WC and the signal line WL. The arrangement of the signal line of interest WC is changed so that D1 can be arranged and the dummy wiring D2 having the width of the minimum design rule Lmin can be arranged in the wiring space between the signal line of interest WC and the signal line WR. In addition, the dummy wiring D1 is arranged in the wiring space between the signal line WC of interest and the signal line WL,
A dummy wiring D2 is arranged in a wiring space between the target signal line WC and the signal line WR.

At this time, the space between the signal line WL and the dummy wiring D1, the space between the signal line of interest WC and the dummy wiring D1, the space between the signal line of interest WC and the dummy wiring D2, The space between the signal line WR and the dummy wiring D2 is the minimum design rule Smin of the wiring space. With such a configuration, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be achieved efficiently, and at the same time, the target signal line WC is connected to the signal line WL and the signal line WR. Almost no signal interference due to crosstalk.

As shown in FIG. 5D, the sum of the wiring spaces Sw1 and Sw2 between the signal wirings is the sum of twice the minimum design rule Lmin of the wiring width and four times the minimum design rule Smin of the wiring space. Or more, ie 2
In a case where Lmin + 4Smin ≦ Sw1 + Sw2,
If Sw1 and Sw2 are each greater than Smin,
The dummy wiring D1 having a width Ld1 larger than the minimum design rule Lmin can be arranged in the wiring space between the signal lines WC and WL, and the signal lines WC and W
The arrangement of the signal line of interest WC is changed so that the dummy wiring D2 having the width of the minimum design rule Lmin can be arranged in the wiring space with R. In addition, the dummy wiring D1 is arranged in the wiring space between the signal line WC of interest and the signal line WL, and the dummy wiring D2 is arranged in the wiring space between the signal line WC of interest and the signal line WR.

At this time, a space between the signal line WL and the dummy wiring D1, a space between the signal line of interest WC and the dummy wiring D1, a space between the signal line of interest WC and the dummy wiring D2, The space between the signal line WR and the dummy wiring D2 is the minimum design rule Smin of the wiring space. In the case of (D), in principle, 2Lmin + 4Smin ≦ Sw1 + Sw2 ≦ 3L
min + 5Smin and Lmin ≦ Ld ≦ 2Lmin
It is necessary to satisfy the condition of + Smin.

In the case (D), the target signal line W
If the space between C and the signal line WL is equal to or more than twice the minimum design rule Lmin of the wiring width and three times the minimum design rule Smin of the wiring space, one new dummy wiring is further added. It is better to insert. In the method of inserting the floating dummy pattern in the case where the signal wiring is located on both sides of the target signal wiring in FIG. 5 described above, Smin is defined by the minimum design rule of the wiring space, but in the cases of (A) to (D) Depending on the Smi
In some cases, it is best to define n as the space where the capacitance between the signal line wiring and the dummy wiring is minimized.

FIG. 6 shows a method of arranging the signal wiring of interest when there are signal wirings on both sides of the signal wiring of interest. FIG.
, WC is the signal line of interest, WL is the signal line of interest W
A signal wiring WR on the left side of C and a signal wiring WR on the right side of the target signal wiring WC are shown. Lwc is the wiring width of the target signal wiring WC, Lwl is the wiring width of the signal wiring WL, Lwr is the wiring width of the signal wiring WR, and Lwc * is the target signal wiring W after the change.
The wiring width of C *, Sw1 is the wiring space between the signal wiring WC and the signal wiring WL, and Sw2 is the wiring space of the signal wiring WC and the signal wiring WR.
Sw1 * is the changed wiring space between the signal wiring WC and the signal wiring WL, and Sw2 * is the wiring space W
Wiring space after change between C and signal wiring WR, Smin
Indicates the dimensions of the minimum design rule of the wiring space. The sum of the wiring spaces Sw1 and Sw2 between the signal wirings is not less than twice the minimum design rule Smin of the wiring space and not more than the sum of the minimum design rule Lmin of the wiring width and three times the minimum design rule Smin of the wiring space. It is. That is, 2Smin ≦ Sw1 + Sw2 ≦
Lmin + 3Smin.

In FIG. 6A, it is assumed that the wiring resistance of the signal line WC of interest becomes a problem. Here, the wiring width Lwc * of the changed signal wiring WC * shown in (b) of FIG. 6A is Lwc * = Lwc + Sw1 + Sw2-2Smin.

The space between the signal line of interest WC and the signal line WR and the space between the signal line of interest WC and the signal line WR are each the minimum design rule Smin of the wiring space.
become. Thereby, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be efficiently achieved. Further, by increasing the wiring width of the signal wiring WC from Lwc to Lwc *, the rate of decrease in the wiring resistance becomes larger than the rate of increase in the wiring capacitance caused by the increase in the capacitance between the wirings. In the case where most of the wiring is occupied, the wiring delay can be greatly reduced, and high speed operation can be achieved.

In the case of FIG. 6A, Smi
n is defined by the minimum design rule of the wiring space,
In some cases, it is more optimal to define Smin as a space where the capacitance between the signal line wiring and the dummy wiring is minimized. In FIG. 6B, it is assumed that the signal line of interest WC has the same probability of receiving signal interference due to crosstalk from the signal line WL and the signal line WR.

The changed wiring space Sw1 * between the signal wiring WC and the signal wiring WL, and the signal wiring WC and the signal wiring WR.
Is equal to the wiring space Sw2 * after the change, and Sw1 * = Sw2 * = (Sw1 + Sw2) / 2. With such a configuration, since air voids can be efficiently formed between the wirings, the reduction of the wiring capacity can be achieved efficiently, and at the same time, the target signal line WC is connected to the signal line WL and the signal line WR. The probability of receiving signal interference due to crosstalk can be equalized.

[0057]

As described above, according to the present invention, the increase in the wiring capacity caused by the small or no air void when the wiring space is large, which has been a problem in the conventional air void process, can be reduced between the wirings. This can be prevented by installing a dummy wiring and forming an air void.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention and a cross-sectional view of the circuit.

FIG. 2 is a diagram showing a wiring space dependency of a gate delay in the semiconductor device according to the embodiment of the present invention and a conventional semiconductor device.

FIG. 3 is a circuit sectional view of the semiconductor device plotted in FIG. 2;

FIG. 4 is a diagram showing a method of inserting a floating dummy pattern between two signal wirings according to the present invention.

FIG. 5 is a diagram showing a method of inserting a floating dummy pattern in a case where signal wiring is present on both sides of a signal wiring of interest according to the present invention.

FIG. 6 is a diagram showing a method of arranging a signal wiring of interest when signal wirings are present on both sides of the signal wiring of interest according to the present invention;

FIG. 7 is a circuit diagram of a conventional semiconductor device and a cross-sectional view of the circuit.

FIG. 8 is a view illustrating a conventional air void process.

FIG. 9 is a diagram illustrating dimensions of an air void in a conventional air void process.

FIG. 10 is a diagram showing a wiring space dependency of each dimension in a conventional air void process.

FIG. 11 is a diagram showing a wiring space dependency of a wiring capacitance value in a conventional semiconductor device.

[Explanation of symbols]

 WC Signal wiring of interest WL Signal wiring on the left side of signal wiring of interest WC WR Signal wiring of right side of signal wiring of interest WC D1 First dummy wiring D2 Second dummy wiring Lmin Minimum design rule of wiring width Smin Minimum design rule of wiring space

Claims (18)

[Claims] 1. A semiconductor device wherein dummy wirings are provided between signal wirings and air voids are formed between the signal wirings and the dummy wirings. 2. The semiconductor device according to claim 1, wherein the dummy wiring is a wiring in a floating state. 3. The wiring according to claim 1, wherein a space between the signal lines is at least equal to the sum of the minimum design rule of the wiring width and twice the minimum design rule of the wiring space. Semiconductor device. 4. A space between wirings as signal lines is equal to or more than twice the minimum design rule of wiring width and triple of minimum design rule of wiring space, and two or more dummy wirings are used. The semiconductor device according to claim 1, wherein the semiconductor device is provided. 5. The semiconductor device according to claim 3, wherein a space between the wiring serving as a signal line and the dummy wiring is equal to a minimum design rule of the wiring space. 6. The space between the signal line wiring and the dummy wiring is a space where the capacitance between the signal line wiring and the dummy wiring is minimized. 13. The semiconductor device according to claim 1. 7. The air void is 50% of the volume between wirings.
The semiconductor device according to claim 1, wherein the above is achieved. 8. A first signal line and a second signal line on both sides of a signal line of interest.
In the semiconductor device in which the signal line of interest is formed, the arrangement of the signal line of interest is changed, and the dummy wiring in a floating state is arranged in the wiring space between the signal line of interest and the first signal line whose arrangement has been changed. Thus, air voids are formed in a space between the first signal line and the dummy wiring, a space between the signal line of interest and the dummy wiring, and a space between the signal line of interest and the second signal line, respectively. A wiring method for a semiconductor device. 9. The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is the minimum design rule of the wiring width and the minimum design of the wiring space. When the sum is equal to or more than three times the rule, a space between the first signal line and the dummy wiring, a space between the signal line of interest and the dummy wiring, a signal line of interest and the second signal line 9. The wiring method for a semiconductor device according to claim 8, wherein a space between the two is set equal to a minimum design rule of the wiring space. 10. The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is determined by the minimum design rule of the wiring width and the minimum design of the wiring space. When the sum is equal to or more than three times the rule, a space between the first signal line and the dummy wiring, a space between the signal line of interest and the dummy wiring, a signal line of interest and the second signal line 9. The wiring method for a semiconductor device according to claim 8, wherein the space between the two is a space where the capacitance is minimized. 11. A semiconductor device having a first signal line and a second signal line formed on both sides of a signal line of interest in a floating state in a wiring space between the signal line of interest and the first signal line. By arranging one dummy wiring and changing the arrangement of the signal line of interest so that the second dummy wiring in a floating state can be arranged in the wiring space between the signal line of interest and the second signal line, A space between the first signal line and the first dummy wiring;
A space between the signal line of interest and the first dummy wiring, a space between the signal line of interest and the second dummy wiring,
Forming an air void in each of the dummy wiring and the space between the second signal lines. 12. The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is twice as large as the minimum design rule of the wiring width. A space between the first signal line and the first dummy wiring when the sum is equal to or more than four times the minimum design rule of
A space between the signal line of interest and the first dummy wiring, a space between the signal line of interest and the second dummy wiring,
12. The wiring method for a semiconductor device according to claim 11, wherein a space between the dummy wiring and the second signal line is equal to a minimum design rule of the wiring space. 13. The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is twice as large as the minimum design rule of the wiring width. A space between the first signal line and the first dummy wiring when the sum is equal to or more than four times the minimum design rule of
A space between the signal line of interest and the first dummy wiring, a space between the signal line of interest and the second dummy wiring,
12. The wiring method for a semiconductor device according to claim 11, wherein a space between the dummy wiring and the second signal line is a space having a minimum capacitance. 14. In a semiconductor device in which a first signal line and a second signal line are formed on both sides of a signal line of interest, at least one of a wiring width of the signal line of interest and an arrangement thereof are changed. Thereby forming air voids in a space between the first signal line and the signal line of interest and in a space between the signal line of interest and the second signal line, respectively. Wiring method. 15. The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is at least twice the minimum design rule of the wiring space. The space between the signal line of interest and the first signal line and the space between the signal line of interest and the second signal line are made equal to the minimum design rule of the wiring space, respectively. The method for wiring a semiconductor device according to claim 14. 16. The sum of the wiring space between the signal line of interest and the first signal line and the wiring space between the signal line of interest and the second signal line is at least twice the minimum design rule of the wiring space. The space between the signal line of interest and the first signal line and the space between the signal line of interest and the second signal line are spaces each having a minimum capacitance. Item 15. The wiring method for a semiconductor device according to Item 14. 17. A semiconductor device in which a first signal line and a second signal line are formed on both sides of a signal line of interest, a wiring space between the signal line of interest and the first signal line, and a signal line of interest. When the sum of the wiring space of the first signal line and the second signal line is at least twice the minimum design rule of the wiring space, by changing the arrangement of the signal line of interest, the signal line of interest and the first signal line are changed.
The space between the signal line of interest and the space between the signal line of interest and the second signal line are respectively defined as the wiring space between the signal line of interest and the first signal line before the layout change, and the space before the layout change. It is equal to half the sum of the wiring space of the signal line of interest and the second signal line, and the space between the first signal line and the signal line of interest and the signal line of interest and the second signal line A wiring method for a semiconductor device, wherein an air void is formed in a space between them. 18. An air void is formed so as to cover at least 50% of a volume between wirings.
18. The wiring method for a semiconductor device according to any one of items 17 to 17.