JP2000150598A - Contactor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a contactor which can remarkably improve the degree of freedom for arrangement of probe terminals, can automate probe terminal attaching work, and can improve the inspection accuracy of an object to be inspected by improving the contacting properties of the probe terminals, and to provide a method for manufacturing the contractor. SOLUTION: A contractor which brings a plurality of electrodes for inspection formed on the whole surface of a wafer W and the probe terminals 3 corresponding to the electrodes for inspection into contact with each other when a plurality of IC chips formed on the wafer W are inspected for electric characteristics is provided with a silicon substrate 2, via holes formed on the surface of the substrate 2 for holding the probe terminals 3 inserted into the holes, conductive layers 10 coating the inner peripheral surfaces of the via holes, and a wiring pattern 4 formed conductively in continuity to the layers 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contactor used for inspecting an electrical characteristic of an object to be inspected and a method of manufacturing the same, and more particularly, to an inspection by contacting the inspected object at once. The present invention relates to a contactor and a method for manufacturing the contactor.

[0002]

2. Description of the Related Art An object to be inspected, such as a semiconductor wafer (hereinafter, referred to as a semiconductor wafer)
Simply referred to as "wafer". When an electrical characteristic test is performed on an IC chip such as a memory circuit or a logic circuit formed in a large number of times, a probe card is used as a contactor. The probe card plays a role of relaying the transmission and reception of the test signal between the tester and the IC chip when the probe card comes into contact with the electrode pad of the wafer during the test. This probe card has, for example, a plurality of probe terminals corresponding to a plurality of electrode pads formed on an IC chip, and inspects the IC chip by electrically contacting each probe needle and each electrode pad. Like that. As the probe terminal, for example, a tungsten wire, a pogo pin, or the like is used.

However, recently, as the integration degree of IC chips has increased and the number of electrode pads has increased rapidly, and the arrangement of the electrode pads has become increasingly narrower, the number of probe terminals of the probe card has increased rapidly. The pitch has been narrowed.

[0004]

However, in the case of the conventional probe card, since the probe terminals are manually attached to the substrate, the number of the probe terminals rapidly increases, and the pitch between the probe terminals becomes narrower. When you come,
There has been a problem that the work of accurately positioning the probe terminals in a predetermined position and mounting the work becomes more and more difficult, and the work of manual mounting is almost at its limit, making the manufacture of the contactor itself difficult. In addition, in the case of a tungsten wire, there is a problem that it is difficult to flexibly cope with the layout of the inspection electrodes of the inspection object due to restrictions on the mounting structure. Incidentally, a technique relating to a contactor corresponding to the narrow pitch is disclosed in, for example, Japanese Patent Application Laid-Open Nos. Hei 5-198636, Hei 5-218156 and Hei 10-38.
No. 918 publication.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to remarkably increase the degree of freedom of the arrangement of probe terminals and to automate the operation of mounting the probe terminals. It is an object of the present invention to provide a contactor capable of improving the contact performance of the contactor and improving the inspection accuracy of the inspection object, and a method of manufacturing the contactor.

[0006]

According to a first aspect of the present invention, there is provided a contactor in which a plurality of inspection electrodes formed on the entire surface of an object to be inspected are brought into contact with corresponding probe terminals, respectively. A contactor for inspecting the electrical characteristics of the circuit element formed in the contactor substrate,
Terminal holes formed for inserting the probe terminals into the contactor substrate surface, a conductive film layer covering the inner peripheral surface of these terminal holes, and a conductive film layer And a wiring film layer formed to be conductive.

In the contactor according to a second aspect of the present invention, a plurality of test electrodes formed on the entire surface of the test object and probe terminals corresponding thereto are brought into contact with each other and formed on the test object. A contactor for inspecting electrical characteristics of a circuit element, comprising: a contactor substrate on which the probe terminals are arranged; and a temperature sensor arranged on a position of the contact substrate that does not interfere with the probe terminals. It is characterized by the following.

The contactor according to a third aspect of the present invention is the contactor according to the first or second aspect,
A heat transfer medium is provided at a position on the substrate surface that does not interfere with the probe terminals.

A contactor according to a fourth aspect of the present invention is the contactor according to any one of the first to third aspects, wherein the contactor is formed so as to be elastically compressively deformable in the axial direction. It is.

According to a fifth aspect of the present invention, in the method for manufacturing a contactor, a plurality of test electrodes formed on the test object are brought into contact with corresponding probe terminals to form the test electrodes on the test object. Providing a plurality of terminal holes on the surface of the contactor substrate, providing a conductive layer on the inner peripheral surface of each terminal hole, and providing a conductive layer for each of the contactors. A step of providing a wiring film layer connected to the film layer on the substrate; and a step of press-fitting a probe terminal into each of the terminal holes.

According to a sixth aspect of the present invention, in the method of manufacturing a contactor according to the fifth aspect, the terminal hole is provided by etching.

Hereinafter, the present invention will be described with reference to the embodiments shown in FIGS. The contactor 1 of the present embodiment, as shown in FIGS. 1 and 2, for example, inspects a large number of IC chips formed on the entire surface of a wafer W to be inspected mounted on a main chuck 50 of a probe device. A plurality of (for example, 16 or 32) IC chips are sequentially switched by switching means such as a multiplexer to inspect all the IC chips. The main chuck 50 moves in the X, Y, Z, and θ directions via a positioning mechanism driven under the control of a control device (not shown) to position the wafer W and the contactor 1. Vacuum evacuation passages 51 are formed in the main chuck 50 at a plurality of locations on the surface thereof, and the wafer W is vacuum-adsorbed on the surface of the wafer chuck 50 by evacuation by a vacuum evacuation device (not shown). A coolant channel 52 is formed in the main chuck 50, and a coolant such as ethylene glycol is circulated to the coolant channel 52 to cool the wafer W.

A heating wire 53 is further incorporated in the wafer chuck 50. The heat generated during the power-on test of the wafer W is used to measure the temperature of the surface of the wafer W using a temperature sensor described later. The flow rate of the refrigerant based on the measured values,
The temperature is controlled to maintain a preset temperature. At the same time, the temperature of the generated heat of the wafer W and the waste heat capacity of the coolant are balanced, and then heated by a heating wire incorporated in the wafer chuck 50, and the temperature of the wafer chuck 50 is set based on a preset temperature. Is finely controlled.

Further, above the main chuck 50, a pressing body 70 for pressing the contactor 1 against the signal extracting board 60 is provided.
Is arranged, the contactor 1 is electrically connected to the signal extraction board 60 via the pressing body 70, and the inspection result is transmitted to the tester side. In addition, the pressing body 70 has a built-in cooling jacket to cool the contactor 1 under inspection and thereby cool the wafer W.

Thus, the contactor 1 has the structure shown in FIGS.
As shown in FIG. 3, a silicon substrate 2 formed with a larger diameter than the wafer W, probe terminals 3 provided on the surface of the silicon substrate 2 in correspondence with all the inspection electrode pads of the wafer W, and It has a probe terminal 3 and connection terminals 5 connected to each other via a wiring pattern 4. As shown in FIG. 2, the probe terminals 3 are arranged in a matrix within the wafer-corresponding region 1A of the silicon substrate 2 (the region indicated by a dashed line in FIG. 2), and each connection terminal 5 is located outside the wafer-corresponding region 1A. They are arranged in a ring shape in the outer peripheral edge region 1B. Further, a ring-shaped seal member 6 is fixed between the probe terminal 3 and the connection terminal 5 of the silicon substrate 2, and the seal member 6 is brought into close contact with the surface of the main chuck 50 at the time of inspection as shown in FIG. The gap between the wafer and the wafer W is shielded from the outside. The wafer corresponding region 1A heat transfer medium 7 is more disposed, also does not interfere with the plurality of temperature sensors 8 Gapu b <br/> over blanking pin 3 and the pattern wiring 4 is provided between each heat transfer medium 7 The temperature of the wafer W under inspection is detected via each temperature sensor 8 and the main chuck 50 is detected based on the detection result.
Temperature is controlled. The arrangement of the heat transfer medium 7 and the temperature sensor 8 is not particularly limited. For example, in the case of an IC chip designed so that the terminal pads are arranged around the IC chip, the heat transfer medium 7 and the heat sensor 8 can be arranged at the center of the IC chip. Further, as the heat transfer medium 7, a large number of extremely small ones such as thermal vias can be arranged.

The plurality of probe terminals 3 include an input pin for inputting an inspection signal to the wafer W and an output pin for outputting an inspection result signal from the wafer W. Some of the connection terminals 5 are in contact with the electrode pads 61 of the signal extraction board 60 to extract the test result signal from the contactor 1 to the signal extraction board 60, and are not in contact with the electrode pads 61 of the signal extraction board 60 and have a temperature. There are pins or the like for extracting a temperature measurement signal from the sensor 8 to the signal extraction board 60.

As shown in FIG. 3A, a wiring pattern 4 made of, for example, aluminum or copper is formed on the surface of the silicon substrate 2, and a via hole 9 is formed at an end of the wiring pattern 4. ing. The wiring pattern 4 is formed not only on the surface of the silicon substrate 2 but also on the silicon substrate 2.
It is also formed over a plurality of layers. A conductive film 10 is formed on the entire inner peripheral surface of the via hole 9 by the same metal as the wiring pattern 4, and the conductive film 10 is connected to the wiring pattern 4. The probe terminal 3 is inserted into the via hole 9 in the wafer area 2A, and the connection terminal 5 is inserted into the via hole 9 in the outer peripheral area 2B. The via hole 9 is formed, for example, as a circular hole having a depth of several tens of μm and a diameter of several tens of μm, and the probe terminal 3 or the connection terminal 5 protrudes from the surface of the silicon substrate 2 by, for example, several tens of μm.

Since the probe terminal 3 or the connection terminal 5 inserted in the via hole 9 is the same, the probe terminal 3 will be described as an example with reference to FIG. The probe terminal 3 has, for example, a prism shape with a substantially square cross section as shown in FIG. 3B, and has truncated quadrangular pyramids 3A and 3B at both upper and lower ends, and is made of a conductive material such as tungsten, beryllium-copper alloy or the like. It is formed of a conductive metal. Although the base end side of the probe terminal 3 is slightly, the corner portion is a via hole 9.
The base end portion is press-fitted into the via hole 9, and the conductive film 10 on the inner peripheral surface of the via hole 9 is formed.
And it is in conductive contact. Grooves 3C are alternately formed on the surfaces facing each other at the tip end side of the probe terminal 3, and the deepest portion of each groove 3C reaches a position deeper than the axis. Therefore, when an overdrive is applied to the probe terminal 3, the probe terminal 3 is elastically compressed and deformed in the axial direction so that the width of the groove 3C of the probe terminal 3 becomes narrow. Are electrically conducted, and conversely, when the probe terminal 3 separates from the wafer W, the tip portion returns to the original state.

Incidentally, process technology and micro machine technology can be applied to the manufacture of the contactor 1. For example, after forming the wiring pattern 4 a plurality of times by CVD, a via hole 9 is formed at the end of each wiring pattern 4 by etching. Then, CV
By D, a conductive film 40 is formed on the inner peripheral surface of each via hole 9. On the other hand, a probe terminal member 30 in which a plurality of probe terminals 3 are connected as shown in FIG. When the probe terminals 3 are mounted in the via holes 9 of the silicon substrate 2, the probe terminals 3 are pushed one by one from the probe terminal member 30 in the direction of the arrow as shown by the arrow in FIG. The probe terminals 3 are pressed into the via holes 9. At this time, since the truncated square pyramid portion 3A is formed at the base end of the probe terminal 3 and is tapered, the truncated square pyramid portion 3A can be smoothly guided into the via hole 9, and the tip of the probe terminal 3 can be extended from the base end. Even if the closer corner protrudes from the via hole 9, the corner at the base end of the probe terminal 3 is plastically deformed, and the base end can be easily pressed into the via hole 9.

Further, the contactor 1 of the present embodiment has a structure shown in FIG.
As shown in (1), a test signal generation circuit 12, a clock signal generation circuit 13, a driver / judgment circuit 14, an expected value signal generation circuit 15, and a disable map (DISABLE) 16 are provided. It is like that. That is, the contactor 1 contacts the wafer W at a time, the IC chips on the wafer W and the tester (not shown) become conductive, and a predetermined number of IC chips and the corresponding current measurement circuit on the tester side. Are connected via the probe terminal 3. In this state, the contactor 1 generates a predetermined test signal from the test signal generation circuit 12 according to a predetermined program, and
3, a clock signal is generated, the driver / judgment circuit 14 operates in accordance with the clock signal, and sequentially transmits test signals to predetermined IC chips on the wafer W via the probe terminals 3. A test result signal is transmitted from each IC chip via the probe terminal 3 to the driver / judgment circuit 14. The driver / judgment circuit 14 compares the test result signal with the expected value signal, judges the quality of the IC chip, and transmits the judgment signal to the tester side. The driver / judgment circuit 14 has an input / output switching circuit such as a tri-state or MOS-SW. When a current exceeding a preset current value flows, the IC chip is regarded as defective and placed in a high impedance state. The power supply is disconnected so that no electrical influence is exerted on other IC chips. The disable map (DISABLE) 16 maps and stores the IC chip from which the power is disconnected.

Next, the operation will be described. First, when the wafer W is placed on the wafer chuck 50, the wafer W is vacuum-adsorbed on the main chuck 50 by evacuation from the evacuation path 51, and the wafer W is cooled via the refrigerant circulating through the refrigerant channel 52. I do. On the other hand, the pressing body 70 is driven to press the contactor 1 against the signal extraction board 60, and the connection terminal 5 is connected to the electrode pad 61 of the signal extraction board 60.
Next, after the wafer chuck 50 is driven to position the wafer W and the contactor 1 via the positioning mechanism,
When the wafer chuck 50 moves up, all the probe terminals 3 come into contact with the inspection electrode pads of the wafer W at once after the sealing member 6 comes into close contact with the surface of the wafer chuck 50 outside the wafer W. Further, when the wafer chuck 50 is overdriven, the tip of the probe terminal 4 is compressed and deformed in the axial direction through the plurality of upper and lower grooves 3C, and a stylus force acts on the wafer W. At this time, even if there is a height difference between the electrode pads of the wafer, the probe terminals 3 are elastically deformed according to the height of the respective electrode pads to absorb the respective height differences, and are electrically connected to the inspection electrode pads. Contact. At this time, even if the wafer chuck 50 tries to rise excessively, the heat transfer medium 7 functions as a stopper to prevent the probe terminals 3 from being damaged.

After the inspection contactor physically contacts the wafer W, power is supplied to all the IC chips on the wafer W. A current measuring circuit corresponding to each IC chip is connected to a signal supply source (tester) side at a power supply terminal connected to a power supply terminal to each IC chip. It is determined to be defective, and the power supply end of the IC chip is disconnected via the switch circuit. And good IC
While power is supplied to all the chips, a test signal is sequentially transmitted to, for example, 32 IC chips while switching channels under the control of the multiplexer, and all the IC chips are inspected. That is, when the test signal generation circuit 12 generates the test signals of the 32 IC chips and transmits them to the driver circuit 14, the clock signal generation circuit 13 generates the clock signal and transmits it to the driver circuit 14. Is applied to the wafer W via the input probe terminal 3 and the output probe terminal 3
Transmits a test result signal to the determination circuit 16.

At the same time, the expected value signal corresponding to the test signal is transmitted from the expected value signal generating circuit 15 to the judging circuit 16. The determination circuit 16 compares the expected value signal with the test result signal to determine the quality of the IC chip. The signal indicating the determination result is transmitted to the tester via the signal extraction board 60. Further, at this time, the wafer W is cooled by the cooling function of the wafer chuck 50 and the cooling jacket of the pressing body 70, thereby preventing a temperature rise due to heat generation of the wafer W. In addition, since the inspection temperature of the wafer W is constantly measured by the temperature sensor 8, when the inspection temperature rises above a predetermined temperature, the temperature in the coolant channel 52 of the wafer chuck 50 is determined based on the detection value of the temperature sensor 8. The temperature of the wafer W is lowered to a predetermined temperature by increasing the circulation flow rate of the coolant.

According to the present embodiment as described above,
When a plurality of inspection electrode pads formed on the entire surface of the wafer W and the corresponding probe terminals 3 are brought into contact with each other to perform electrical characteristic inspection of many IC chips, the silicon substrate 2 and the surface of the silicon substrate 2 Each probe terminal 3
A via hole 9 formed for inserting each,
The conductive film layer 1 covering the inner peripheral surface of these via holes 9
0, and the wiring pattern 4 formed so as to be electrically conductive with the conductive film layer 10, so that a via hole for the probe terminal 3 can be formed in accordance with the arrangement of the inspection electrode pads on the wafer W using a process technique. 9 can be provided, and the probe terminals 3 are inserted into the via holes 9. Therefore, even when the pitch of the probe terminals 3 is reduced, the probe terminals 3 are automatically mounted in the via holes 9 using a micro machine or the like. can do. Further, since the probe terminal 3 itself is compressed and deformed in the axial direction, it is possible to obtain a good contact characteristic by absorbing a height difference of the inspection electrode pad due to the warpage of the wafer W or the like, thereby performing a highly accurate inspection. be able to.

Further, since the contactor 1 of the present embodiment has the temperature sensor 8, the inspection temperature can be measured directly and accurately. Also, this contactor 1 has a wafer W
Since the heat transfer medium 7 has a heat transfer medium 7 for releasing heat to the contactor 1 side by contacting the wafer W, even if the wafer W generates heat, the heat can be quickly released and an excessive temperature rise of the wafer W can be prevented. The probe terminal 3 can be prevented from being damaged by preventing the chuck 50 from rising excessively.

The present invention is not limited to the above embodiment. For example, the substrate may be a ceramic substrate or a polyimide substrate other than the silicon substrate.
Further, not only a wiring layer but also a substrate on which active elements are formed can be used. Further, the probe terminal 3 can be appropriately designed and changed as needed as long as it has a structure that can be compressed in the axial direction. For example, the side surface may have a wavy shape. Also, the probe terminal 3 of the contactor 1
The number of inspections is not limited to those provided for all the inspection electrode pads of the wafer W, and the inspection of the wafer W is performed in a plurality of times while contacting a part of the inspection electrode pads and feeding the wafer W by index. May be performed.

[0027]

According to the first to sixth aspects of the present invention, the degree of freedom in the arrangement of the probe terminals can be greatly increased, and the operation of mounting the probe terminals can be automated. In addition, it is possible to provide a contactor capable of improving the contact property of a probe terminal and improving the inspection accuracy of an object to be inspected, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a contactor according to the present invention, showing a state in which it is in contact with a wafer.

FIG. 2 is a plan view showing a relationship between a contactor and a wafer shown in FIG.

3A is a cross-sectional view showing, in an enlarged manner, a mounting state of a probe terminal of the contactor shown in FIG. 1, and FIG.
It is -B sectional drawing.

FIG. 4 is an explanatory view showing a method of attaching a probe terminal to a silicon substrate when manufacturing the contactor shown in FIG.

FIG. 5 is a block diagram showing a configuration of a contactor shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Contactor 2 Silicon substrate 3 Probe terminal 4 Wiring pattern (wiring film layer) 7 Heat transfer medium 8 Temperature sensor 9 Via hole (terminal hole) 10 Conductive layer W Wafer (test object)

Claims (6)

[Claims] 1. A contactor for contacting a plurality of test electrodes formed on the entire surface of an object to be inspected with probe terminals corresponding to the electrodes, and inspecting electrical characteristics of circuit elements formed on the object to be inspected. A contactor substrate, a terminal hole formed for inserting each of the probe terminals on the surface of the contactor substrate, and a conductive film layer covering an inner peripheral surface of the terminal hole, A contactor comprising: a conductive film layer; and a wiring film layer formed to be conductive. 2. A contactor for contacting a plurality of test electrodes formed on the entire surface of an object to be inspected with corresponding probe terminals, and inspecting electrical characteristics of circuit elements formed on the object to be inspected. A contactor substrate on which the probe terminals are arranged, and a temperature sensor arranged at a position on the contact substrate that does not interfere with the probe terminals. 3. The contactor according to claim 1, wherein a heat transfer medium is provided at a position on the surface of the substrate that does not interfere with the probe terminals. 4. The probe terminal according to claim 1, wherein said probe terminal is formed so as to be elastically compressively deformable in an axial direction.
The contactor according to claim 3. 5. A method in which a plurality of test electrodes formed on a test object are brought into contact with corresponding probe terminals,
In the method of manufacturing a contactor for inspecting electrical characteristics of a circuit element formed on an object to be inspected, a step of providing a plurality of terminal holes on a surface of a contactor substrate, and a conductive film on an inner peripheral surface of each terminal hole A method for manufacturing a contactor, comprising the steps of: providing a layer and providing a wiring film layer connected to each conductive film layer on the substrate; and press-fitting a probe terminal into each of the terminal holes. 6. The method according to claim 5, wherein the terminal holes are provided by etching.