JP2000150549A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JP2000150549A JP2000150549A JP32014198A JP32014198A JP2000150549A JP 2000150549 A JP2000150549 A JP 2000150549A JP 32014198 A JP32014198 A JP 32014198A JP 32014198 A JP32014198 A JP 32014198A JP 2000150549 A JP2000150549 A JP 2000150549A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- wiring board
- semiconductor device
- resin
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にチップサイズに相当する大きさに実装す
るチップ・サイズ・パッケージ（以下、ＣＳＰという）
と呼ばれる方法で半導体装置を実装する製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a chip size package (hereinafter referred to as a CSP) mounted to a size corresponding to a chip size.
The present invention relates to a manufacturing method for mounting a semiconductor device by a method referred to as a method for mounting a semiconductor device.
【０００２】[0002]
【従来の技術】ＣＳＰ法による実装体の一例を図１に示
す。半導体装置が形成されたチップ２の電極面と配線基
板４の間がバンプ６により接合され、チップ２と配線基
板４とのすき間にチップ電極面を保護するための樹脂８
が充填されている。2. Description of the Related Art FIG. 1 shows an example of a package according to the CSP method. An electrode surface of the chip 2 on which the semiconductor device is formed and the wiring substrate 4 are joined by bumps 6, and a resin 8 for protecting the chip electrode surface in a gap between the chip 2 and the wiring substrate 4.
Is filled.
【０００３】このようなＣＳＰ実装体の製造方法の一例
を図２に示す。 （Ａ）半導体ウエハに複数個の半導体装置を形成し、そ
の半導体装置の接続パットにバンプ６を形成した後、ウ
エハを個々のチップ２に切り離す。その後、チップ２と
配線基板４の電極との間をバンプ６により接合する。 （Ｂ）チップ２と配線基板４のすき間に樹脂を充填する
ために、基板４の周辺部に樹脂を塗布してダム８ａを形
成する。 （Ｃ）その後、チップ２と配線基板４のすき間に樹脂８
を注入した後、硬化させる。FIG. 2 shows an example of a method for manufacturing such a CSP package. (A) A plurality of semiconductor devices are formed on a semiconductor wafer, bumps 6 are formed on connection pads of the semiconductor device, and the wafer is cut into individual chips 2. After that, the chip 2 and the electrode of the wiring board 4 are joined by the bump 6. (B) In order to fill the gap between the chip 2 and the wiring board 4 with the resin, the resin is applied to the periphery of the board 4 to form the dam 8a. (C) Then, the resin 8 is provided between the chip 2 and the wiring board 4.
After injecting, is cured.
【０００４】[0004]
【発明が解決しようとする課題】図２に示したＣＳＰ実
装方法では、半導体ウエハをチップごとに分割した後に
配線基板４と接合しているため、組立て工数が多くなり
コスト高になる問題がある。また、チップ２と配線基板
４のすき間に樹脂を注入するために、図２（Ｂ）に示さ
れるように配線基板４の周辺部にダム８ａを形成するた
めの領域が必要になる。そのため、配線基板４のサイズ
をチップ２のサイズよりも大きくしなければならず、こ
のことから実装体の大きさがチップサイズよりも大きく
なる欠点もある。In the CSP mounting method shown in FIG. 2, since the semiconductor wafer is divided into chips and then joined to the wiring board 4, there is a problem that the number of assembling steps is increased and the cost is increased. . In addition, in order to inject the resin into the gap between the chip 2 and the wiring board 4, an area for forming the dam 8a is required around the wiring board 4 as shown in FIG. 2B. Therefore, the size of the wiring board 4 must be larger than the size of the chip 2, which has a disadvantage that the size of the mounting body is larger than the chip size.
【０００５】そこで、これらの問題点を解決する１つの
方法として、チップの電極面上に弾性樹脂層を介して金
属配線とパッケージ電極を直接設ける構造が提案されて
いる（特開平９−３２１１８１号公報参照）。しかし、
その提案された方法では、水分等の侵入に対する信頼性
に問題がある。In order to solve these problems, a structure has been proposed in which metal wiring and package electrodes are directly provided on an electrode surface of a chip via an elastic resin layer (Japanese Patent Laid-Open No. 9-32181). Gazette). But,
The proposed method has a problem in reliability against penetration of moisture and the like.
【０００６】そこで、本発明はＣＳＰ法において、信頼
性を維持し、実装体のサイズをチップサイズと同一と
し、かつコストも抑えることのできる方法を提供するこ
とを目的とするものである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a CSP method capable of maintaining reliability, making the size of a package the same as the chip size, and reducing costs.
【０００７】[0007]
【課題を解決するための手段】本発明の製造方法は、複
数チップ分の半導体装置が形成された半導体ウエハで、
個々のチップに切断される前の状態のものに対し、少な
くともそのウエハと同じ大きさをもち、表面には前記半
導体装置の電極と接続される電極が形成され、裏面には
表面側の電極と電気的につながった外部接続用電極が形
成された配線基板を、その表面側を前記ウエハの半導体
装置が形成された面に対向させて重ね、バンプ接合法に
より接合する工程と、接合された状態の前記ウエハと配
線基板間のすき間に封止用樹脂を充填し硬化させる工程
と、接合され隙間に樹脂が充填された前記ウエハと配線
基板との接合体を個々のチップに切断する工程とを備え
ている。According to the manufacturing method of the present invention, a semiconductor wafer on which semiconductor devices for a plurality of chips are formed is provided.
For the state before being cut into individual chips, electrodes having at least the same size as the wafer, electrodes connected to the electrodes of the semiconductor device are formed on the front surface, and electrodes on the front surface are formed on the back surface. A step of laminating a wiring board on which an electrically connected external connection electrode is formed with its front surface side facing the surface of the wafer on which the semiconductor device is formed, and bonding the wiring board by a bump bonding method; Filling a sealing resin in a gap between the wafer and the wiring board and curing the same, and cutting a bonded body of the wafer and the wiring board, which are joined and filled with the resin in the gap, into individual chips. Have.
【０００８】[0008]
【発明の実施の形態】バンプ接合では、チップに形成さ
れた半導体装置の接続用バッドにバンプを形成するが、
そのバンプは金ワイヤーボンディング法による金ボール
を用いるスタンドバンプ方式や、メッキ方式による金バ
ンプや半田バンプ、さらには従来から行なわれているバ
ンプであればいずれの方法により形成してもよい。その
うち、メッキ方式によるバンプが経済的である。DESCRIPTION OF THE PREFERRED EMBODIMENTS In bump bonding, bumps are formed on connection pads of a semiconductor device formed on a chip.
The bump may be formed by a stand bump method using a gold ball by a gold wire bonding method, a gold bump or a solder bump by a plating method, or any conventional bump. Among them, the bump by the plating method is economical.
【０００９】配線基板としてはガラスエポキシ基板、ポ
リイミド基板、セラミック基板などをベース基板とした
多層配線基板を使用することができる。これらの多層配
線基板は半導体装置の実装用に使用されている既知のも
のである。その中でも、熱膨張係数がシリコン基板にも
っとも近いセラミック基板をベース基板としたものが好
ましい。それは、シリコンのチップと配線基板とを直接
接合するので、温度変化に伴う熱ストレスを小さく抑え
るためには、チップと配線基板との熱膨張率の差が小さ
い方が好ましいからである。As the wiring substrate, a multilayer wiring substrate using a glass epoxy substrate, a polyimide substrate, a ceramic substrate or the like as a base substrate can be used. These multilayer wiring boards are known ones used for mounting semiconductor devices. Among them, a substrate using a ceramic substrate having a thermal expansion coefficient closest to a silicon substrate as a base substrate is preferable. This is because, since the silicon chip and the wiring substrate are directly joined, it is preferable that the difference in the coefficient of thermal expansion between the chip and the wiring substrate is small in order to suppress the thermal stress caused by the temperature change.
【００１０】接合されたウエハと配線基板とのすき間に
充填する樹脂の材質は、特に限定されるものではない
が、封止用樹脂として一般的に使用されているエポキシ
系熱硬化性樹脂が適当である。配線基板の裏面側の外部
接続用電極には、プリント配線基板に搭載するための接
続用バンプを形成するが、そのバンプはウエハと配線基
板の接合体を個々のチップに切断する工程の前に形成す
ることもできるし、又は後で形成することもできる。The material of the resin to be filled in the gap between the bonded wafer and the wiring board is not particularly limited, but an epoxy thermosetting resin generally used as a sealing resin is suitable. It is. On the external connection electrode on the back side of the wiring board, connection bumps for mounting on the printed wiring board are formed, and the bumps are formed before the step of cutting the bonded body of the wafer and the wiring board into individual chips. It can be formed or can be formed later.
【００１１】ウエハと配線基板間のすき間に封止用樹脂
を充填する工程では、予め配線基板に１個又は複数個の
貫通孔を開けておき、その貫通孔を通してノズルから樹
脂を吐出して注入するのが好ましい。この方法によれ
ぱ、ウエハと配線基板間のすき間全体に短時間で樹脂を
充填できるようになる。さらに、その貫通孔から樹脂を
注入する工程では、ウエハと配線基板の接合体の周囲の
雰囲気を大気圧よりも低い減圧状態にしておくことが好
ましい。減圧は真空に近い方がよい。周囲の雰囲気を減
圧にすることにより、樹脂注入の際に問題となる空気の
巻込みによるボイドの発生を防止することができる。In the step of filling the gap between the wafer and the wiring board with the sealing resin, one or a plurality of through holes are previously formed in the wiring board, and the resin is discharged from the nozzle through the through holes and injected. Is preferred. According to this method, the entire gap between the wafer and the wiring board can be filled with the resin in a short time. Further, in the step of injecting the resin from the through-hole, it is preferable that the atmosphere around the joined body of the wafer and the wiring substrate is set to a reduced pressure lower than the atmospheric pressure. The pressure reduction is preferably close to vacuum. By reducing the pressure of the surrounding atmosphere, it is possible to prevent the occurrence of voids due to entrainment of air, which is a problem during resin injection.
【００１２】[0012]
【実施例】図３は半導体装置が形成されたシリコンウエ
ハ１０と、それと同じ大きさでウエハ１０に接合される
多層配線基板１４を対向させた状態を表わしたものであ
る。ウエハ１０には複数個のチップ用の半導体装置が形
成され、その半導体装置の接続用パッド上にはバンプ接
合を行なうためのバンプ１２が形成されている。FIG. 3 shows a state in which a silicon wafer 10 on which a semiconductor device is formed and a multilayer wiring board 14 of the same size and bonded to the wafer 10 are opposed to each other. A plurality of semiconductor devices for chips are formed on the wafer 10, and bumps 12 for performing bump bonding are formed on connection pads of the semiconductor devices.
【００１３】一方、多層配線基板１４の表面側にはウエ
ハ１０の半導体装置に対応した複数の領域のそれぞれに
バンプ１２と接合される電極１６が形成されている。多
層配線基板１４の裏面側には外部接続用電極１８が形成
されており、外部接続用電極１８は多層配線基板１４の
内部配線を通して表面側の電極１６と電気的に接続され
ている。多層配線基板１４はセラミック基板をベース基
板として電極が形成されたものである。On the other hand, on the surface side of the multilayer wiring board 14, electrodes 16 to be bonded to the bumps 12 are formed in a plurality of regions of the wafer 10 corresponding to the semiconductor devices. An external connection electrode 18 is formed on the back surface of the multilayer wiring board 14, and the external connection electrode 18 is electrically connected to the front electrode 16 through the internal wiring of the multilayer wiring board 14. The multilayer wiring board 14 is one in which electrodes are formed using a ceramic substrate as a base substrate.
【００１４】バンプ１２は金ボールでも半田バンプでも
よいが、ここではメッキ法により形成された金バンプを
使用する。その金バンプを図４に示す。半導体装置が形
成されたウエハ１０のシリコン基板上に接続用パッド２
０が形成され、そのパッド２０の接続部を除く基板表面
がパッシベーション膜２２で被覆されている。パッド２
０の露出部にはチタン膜２４を介してバリアメタルのパ
ラジウム膜２６が形成され、その上に金バンプ１２が形
成されている。The bumps 12 may be gold balls or solder bumps. Here, gold bumps formed by plating are used. The gold bump is shown in FIG. The connection pad 2 is formed on the silicon substrate of the wafer 10 on which the semiconductor device is formed.
0 is formed, and the surface of the substrate excluding the connection portion of the pad 20 is covered with the passivation film 22. Pad 2
The palladium film 26 of the barrier metal is formed on the exposed portion of the “0” via the titanium film 24, and the gold bump 12 is formed thereon.
【００１５】メッキ法により金バンプを形成する方法は
周知のものであるが、簡単に示すと次のようになる。パ
ッド２０及びパッシベーション膜２２を形成した後、チ
タン膜２４とパラジウム膜２６をスパッタリング法によ
り順に形成して積層し、写真製版とエッチングによりパ
ラジウム膜２６を図４の形状にパターン化する。次に、
バンプ１２を形成する領域に開口をもつレジストパター
ンを写真製版により形成し、そのレジストパターンをマ
スクとしてパラジウム膜２６上に金メッキを施す。その
後、レジストを除去し、パラジウム膜２６から露出して
いるチタン膜２４をエッチングにより除去すれば、図４
の金バンプとなる。Although a method of forming a gold bump by a plating method is well known, a brief description will be given below. After the pads 20 and the passivation film 22 are formed, a titanium film 24 and a palladium film 26 are sequentially formed and laminated by a sputtering method, and the palladium film 26 is patterned into the shape shown in FIG. 4 by photolithography and etching. next,
A resist pattern having an opening in a region where the bump 12 is to be formed is formed by photolithography, and gold plating is performed on the palladium film 26 using the resist pattern as a mask. Thereafter, the resist is removed, and the titanium film 24 exposed from the palladium film 26 is removed by etching.
Gold bump.
【００１６】ウエハ１０と多層配線基板１４の接合後に
両者のすき間に樹脂を注入するために、図５（Ｂ）に示
されるように、多層配線基板１４には４つの貫通孔３４
が開けられている。図５（Ａ）はウエハ１０の表面を示
したものであり、ウエハ１０の表面には複数のチップ領
域３０が格子状に配列されて、それぞれの領域に半導体
装置が形成され、バンプ１２が形成されているが、多層
配線基板１４の孔３４に対応した位置のチップ領域３６
には半導体装置は形成されていない。多層配線基板１４
の表面には、半導体装置が形成されているチップ領域３
０に対応して格子状に配置された各領域に接続用電極１
６が形成されている。図３に戻って説明すると、ウエハ
１０と多層配線基板１４を図のように対向させ、熱圧着
によりバンプ１２と電極１６間を接合させる。As shown in FIG. 5B, four through holes 34 are formed in the multilayer wiring board 14 in order to inject resin into the gap between the wafer 10 and the multilayer wiring board 14 after the bonding.
Is open. FIG. 5A shows the surface of the wafer 10. A plurality of chip regions 30 are arranged in a grid on the surface of the wafer 10, and a semiconductor device is formed in each region, and the bumps 12 are formed. However, a chip region 36 at a position corresponding to the hole 34 of the multilayer wiring board 14 is provided.
No semiconductor device is formed. Multilayer wiring board 14
The chip region 3 where the semiconductor device is formed
In each of the regions arranged in a grid corresponding to 0, the connection electrodes 1
6 are formed. Returning to FIG. 3, the wafer 10 and the multilayer wiring board 14 are opposed to each other as shown in the figure, and the bumps 12 and the electrodes 16 are joined by thermocompression bonding.
【００１７】その後、多層配線基板１４の貫通孔３４か
らノズルによりエポキシ樹脂をウエハ１０と多層配線基
板１４のすき間に注入し、加熱して硬化させる。ノズル
からエポキシ樹脂を注入する際、ウエハ１０と多層配線
基板１４の接合体の周囲を大気圧よりも減圧状態にして
おくことにより、樹脂を注入する際に樹脂へのエアーの
巻込みを防いでボイド発生を防止することができる。雰
囲気を減圧にすることにより樹脂がウエハ１０と多層配
線基板１４のすき間を通って外部に排出させるのを防ぐ
ために、その隙間の周辺部に図２（Ｂ）に示されるダム
８ａのような障壁を設けておいてもよい。Thereafter, epoxy resin is injected into the gap between the wafer 10 and the multilayer wiring board 14 through a through hole 34 of the multilayer wiring board 14 by a nozzle, and is heated and cured. When the epoxy resin is injected from the nozzle, the periphery of the joined body of the wafer 10 and the multilayer wiring board 14 is kept at a pressure lower than the atmospheric pressure, thereby preventing air from being caught in the resin when the resin is injected. Void formation can be prevented. In order to prevent the resin from being discharged to the outside through the gap between the wafer 10 and the multilayer wiring board 14 by reducing the atmosphere, a barrier such as a dam 8a shown in FIG. May be provided.
【００１８】ウエハ１０と多層配線基板１４のすき間に
樹脂を注入し硬化させた後、多層配線基板１４の裏面側
の外部接続用電極１８上にバンプ４０（図６参照）を形
成する。バンプ４０は、金ワイヤボンディングによる金
ボールや半田バンプなど、従来の実装体で用いられてい
るバンプを使用することができる。After a resin is injected into the gap between the wafer 10 and the multilayer wiring board 14 and cured, a bump 40 (see FIG. 6) is formed on the external connection electrode 18 on the back side of the multilayer wiring board 14. As the bump 40, a bump used in a conventional mounting body such as a gold ball or a solder bump by gold wire bonding can be used.
【００１９】その後、ダイシング技術など既知の手法に
より、ウエハ１０と多層配線基板１４の接合体を図３の
鎖線の位置で個々のチップに切断すると、図６に示され
るようにＣＳＰ実装された半導体装置が得られる。図６
で、記号１９はウエハ１０と多層配線基板１４との隙間
に充填され硬化したエポキシ樹脂である。バンプ４０を
形成する工程は、ウエハ１０と多層配線基板１４の接合
体を個々のチップに切り離した後に行なってもよい。Then, when the joined body of the wafer 10 and the multilayer wiring board 14 is cut into individual chips at the positions indicated by the dashed lines in FIG. 3 by a known technique such as dicing technology, the semiconductor mounted by CSP as shown in FIG. A device is obtained. FIG.
The symbol 19 is an epoxy resin filled and cured in the gap between the wafer 10 and the multilayer wiring board 14. The step of forming the bumps 40 may be performed after the bonded body of the wafer 10 and the multilayer wiring board 14 is separated into individual chips.
【００２０】[0020]
【発明の効果】本発明では、複数チップ分の半導体装置
が形成された半導体ウエハを、個々のチップに切断され
る前の状態で配線基板にバンプ接合法により接合し、ウ
エハと配線基板間のすき間に封止用樹脂を充填し硬化さ
せた後、ウエハと配線基板との接合体を個々のチップに
切断するようにしたので、半導体チップと同じサイズの
ＣＳＰ実装体を得ることができ、またウエハと多層配線
基板を接合した後に個々のチップごとに切り離すので、
製造工数が少なく低コストに実現することができる。さ
らに、チップの電極形成面を多層配線基板で被い、その
すき間に封止用の樹脂を充填しているので、水分の侵入
などに対する信頼性が高い。According to the present invention, a semiconductor wafer on which semiconductor devices for a plurality of chips are formed is bonded to a wiring substrate by a bump bonding method in a state before being cut into individual chips. After filling and hardening the sealing resin in the gap, the joined body of the wafer and the wiring board is cut into individual chips, so that a CSP mounted body of the same size as the semiconductor chip can be obtained. Since the wafer and the multilayer wiring board are joined and then separated into individual chips,
The number of manufacturing steps is small and the cost can be reduced. Further, since the electrode forming surface of the chip is covered with the multilayer wiring board and the gap is filled with a sealing resin, the reliability against intrusion of moisture and the like is high.
【図１】従来のＣＳＰ法による実装体の一例を示す断面
図である。FIG. 1 is a cross-sectional view showing an example of a mounting body according to a conventional CSP method.
【図２】同従来のＣＳＰ実装体を製造する方法を示す工
程断面図である。FIG. 2 is a process sectional view showing a method for manufacturing the conventional CSP package.
【図３】一実施例において、シリコンウエハと多層配線
基板を対向させた状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state in which a silicon wafer and a multilayer wiring board are opposed to each other in one embodiment.
【図４】同実施例における金バンプを示す断面図であ
る。FIG. 4 is a sectional view showing a gold bump in the embodiment.
【図５】同実施例において、樹脂注入用の孔を開けた多
層配線基板（Ｂ）と、それに対応するウエハの表面
（Ａ）を示す平面図である。FIG. 5 is a plan view showing a multilayer wiring board (B) having holes for resin injection and a corresponding wafer surface (A) in the example.
【図６】同実施例において製造されるＣＳＰ実装された
半導体装置を示す断面図である。FIG. 6 is a cross-sectional view showing a CSP-mounted semiconductor device manufactured in the same embodiment.
１０ ウエハ １２ バンプ １４ 多層配線基板 １６ 電極 １８ 外部接続用電極 １９ エポキシ樹脂 DESCRIPTION OF SYMBOLS 10 Wafer 12 Bump 14 Multilayer wiring board 16 Electrode 18 External connection electrode 19 Epoxy resin
Claims (5)
半導体ウエハで、個々のチップに切断される前の状態の
ものに対し、少なくともそのウエハと同じ大きさをも
ち、表面には前記半導体装置の電極と接続される電極が
形成され、裏面には表面側の電極と電気的につながった
外部接続用電極が形成された配線基板を、その表面側を
前記ウエハの半導体装置が形成された面に対向させて重
ね、バンプ接合法により接合する工程と、 接合された状態の前記ウエハと配線基板間のすき間に封
止用樹脂を充填し硬化させる工程と、 接合され隙間に樹脂が充填された前記ウエハと配線基板
との接合体を個々のチップに切断する工程とを備えたこ
とを特徴とする半導体装置の製造方法。1. A semiconductor wafer on which semiconductor devices for a plurality of chips are formed, which has a size at least as large as that of a semiconductor wafer before being cut into individual chips, and a surface of the semiconductor device on a surface thereof. A wiring board on which an electrode to be connected to an electrode is formed and an external connection electrode electrically connected to an electrode on the front side is formed on the back side, and the front side is a surface on which the semiconductor device of the wafer is formed. A step of bonding by a bump bonding method, a step of filling and sealing a sealing resin in a gap between the bonded wafer and the wiring board, and a step of bonding and filling the gap with the resin. Cutting the joined body of the wafer and the wiring board into individual chips.
基板とする多層配線基板である請求項１に記載の半導体
装置の製造方法。2. The method according to claim 1, wherein the wiring substrate is a multilayer wiring substrate using a ceramic substrate as a base substrate.
切断する工程の前又は後に、前記配線基板の裏面側の外
部接続用電極にバンプを形成する工程を備えている請求
項１又は２に記載の半導体装置の製造方法。3. The method according to claim 1, further comprising, before or after the step of cutting the wafer and the wiring board into individual chips, forming a bump on an external connection electrode on the back side of the wiring board. The manufacturing method of the semiconductor device described in the above.
用樹脂を充填する工程では、前記配線基板に１個又は複
数個の貫通孔を開けておき、その貫通孔を通してノズル
から樹脂を吐出して注入する請求項１，２又は３に記載
の半導体装置の製造方法。4. In the step of filling a sealing resin between the wafer and the wiring board, one or more through holes are formed in the wiring board, and the resin is discharged from a nozzle through the through holes. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is implanted.
は、前記ウエハと配線基板の接合体の周囲の雰囲気を大
気圧よりも低い減圧状態にしておく請求項４に記載の半
導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of injecting a resin through the through hole, an atmosphere around a bonded body of the wafer and the wiring substrate is set to a reduced pressure lower than an atmospheric pressure. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32014198A JP2000150549A (en) | 1998-11-11 | 1998-11-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32014198A JP2000150549A (en) | 1998-11-11 | 1998-11-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000150549A true JP2000150549A (en) | 2000-05-30 |
Family
ID=18118176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32014198A Pending JP2000150549A (en) | 1998-11-11 | 1998-11-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000150549A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1420441A1 (en) * | 2002-10-30 | 2004-05-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2006059943A (en) * | 2004-08-19 | 2006-03-02 | North:Kk | Integrated circuit device and manufacturing method |
-
1998
- 1998-11-11 JP JP32014198A patent/JP2000150549A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1420441A1 (en) * | 2002-10-30 | 2004-05-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US7132756B2 (en) | 2002-10-30 | 2006-11-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US7390692B2 (en) | 2002-10-30 | 2008-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
| CN100442481C (en) * | 2002-10-30 | 2008-12-10 | 松下电器产业株式会社 | Semiconductor device and its mfg. method |
| JP2006059943A (en) * | 2004-08-19 | 2006-03-02 | North:Kk | Integrated circuit device and manufacturing method |
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