JP2000149835A - Matrix type display device and display panel using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display panel suppressing deterioration in maximum luminance in spite of increase in the number of lines of electron emission elements, widening a pulse width of a pulse driving the display panel, and lowering a clock frequency. SOLUTION: Electron emission elements 200 in two lines adjacent to a single line wire 101 are connected to the line wire 101. To a single column wire 102a or 102b, the electron emission elements 200 are connected every other line, while the electron emission elements 200 are connected alternately to the adjacent column wires 102a, 102b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device in which cold cathode type electron-emitting devices are arranged in a matrix and a display panel used for the same.

[0002]

2. Description of the Related Art As a flat type image display device, a matrix type display device using a combination of a cold cathode type electron emitting element and a phosphor has been known. This means that signals driven by row and column driving circuits are applied to electron-emitting devices arranged in a matrix through wiring in the row and column directions, and the emitted electrons excite the phosphor to excite the phosphor. By emitting light, a desired image is displayed.

As a cold-cathode type electron-emitting device, for example, a surface conduction type electron-emitting device utilizing a phenomenon in which an electron is emitted by flowing a current through a thin film formed on a panel is known. In addition, a metal layer, an insulating layer, and a metal layer are superposed on a panel, and a voltage is applied to the lower metal layer and the upper metal layer to cause the upper metal layer to emit electrons. Body / metal type electron-emitting devices are also known.

FIG. 5 is a diagram showing a general wiring configuration of a display panel using a surface conduction electron-emitting device. In FIG. 5, a display panel 10 includes a row wiring 11 and a column wiring 12.
And a surface conduction electron-emitting device (hereinafter, “emission device”) 200 connected to the row wiring 11 and the column wiring 12. The row wiring 11 and one element electrode 202a of the emission element 200 are connected by a conductor 103a, and the column wiring 12 and the emission element 2
00 is connected to the other element electrode 202b by a conductor 103b.

[0005] To drive any release element 200 in the display panel 10 (i row and j-th column) is the row wiring 11 _i of the row scanning by applying a scanning voltage -Vs, the voltage in the other row Do not apply. In synchronization with this, the pulse width modulated data voltage Vd corresponding to the image data to the column lines 12 _j
Is applied. At this time, each emission element 200 in the i-th row has
The voltage (Vd + Vs) is applied, and the voltage V is applied to the other rows.
d is applied. The emission element 200 has a threshold value Vth for emitting electrons, and emits almost no electrons unless the applied voltage becomes equal to or higher than the threshold value Vth.
Both the voltage Vd and the voltage Vs are set to be equal to or lower than the threshold Vth, and the voltage (Vd + Vs) is set to be equal to or higher than the threshold Vth.

With this arrangement, the voltage (Vd + V) is applied only during the period of the pulse width corresponding to the image data of the i-th row being scanned.
When s) is applied, the emission element 200 emits electrons and emits light from a phosphor (not shown). The gradation of an image displayed on the display panel 10 is represented by the pulse width of a pulse applied to the column wiring 12.

FIG. 6 is a waveform diagram showing an example of a driving waveform of the display panel 10 shown in FIG. FIG. 6 shows an operation when displaying the j-th column as an example, and shows a scanning pulse applied to the row wiring 11 and a data pulse applied to the column wiring 12. Here, the number of bits of the video signal is 8 bits, perfect black is represented as 0, and perfect white is represented as 255, i-th row and j-th column is 128, i + 1-th row and j-th column is 255,
The case where i + 2 row and j column is 64 and i + 3 row and j column is 0 are shown. One horizontal scanning period is constituted by 255 unit times. Assuming that the unit time is represented by T, gradation expression is performed by changing the pulse width of the data pulse applied to the column wiring 12 from 0T to 255T.

As shown in FIG. 6 (E), the data pulse applied to the column wiring 12 has a voltage Vd for a period of 128T when scanning the i-th row, and for a period of 255T (ie, the entire period) when scanning the i + 1-th row. The voltage is Vd. At the time of scanning i + 2 rows, the voltage is Vd during the period of 64T, and at the time of scanning i + 3 rows, it is 0V during the period of 255T. The unit time T is 1
It may be 1/255 of the horizontal scanning period or less.

FIG. 7 is a block diagram showing a configuration of a matrix type display device having the display panel 10 shown in FIG. 5 and realizing the driving method shown in FIG. In FIG. 7, a video signal input to a terminal 1 is written to a shift register 2. After one row of data is written in the shift register 2, the data is latched by the latch circuit 3 and input to the pulse width modulation (PWM) circuit 4. PW
M circuit 4 inputs the data pulse corresponding to the size of the data to the column lines 12 ₁ to 12 _N of the display panel 10.

[0010] The synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift register 2 and a latch clock to the latch circuit 3. The timing control circuit 8 also supplies a pulse of one line width to the shift register 9. The shift register 9 is sequentially input from the first row as the scan pulse to the row wirings 11 ₁ to 11 _M of the display panel 10 of the pulse.

[0011]

In the matrix type display device having the conventional display panel 10 described above, when the number of rows of the row wiring 11 is M, one field time is Tv.
Then, the pulse width of the scanning pulse that can be applied to each emission element 200 during one field is Tv / M. That is, in order to increase the number of rows of the emission elements 200, the maximum brightness decreases as the number of rows of the row wiring 11 increases. Further, as the number of rows of the row wiring 11 increases, the unit time T (=
Tv / M / 255) becomes shorter, and the clock frequency of the PWM circuit 4 must be increased.

As a solution to this problem, as disclosed in Japanese Patent Application Laid-Open No. 8-212944, a display panel 1 is disclosed.
There is a method of dividing the 0 column wiring 12 into two vertically and dividing the driving block into two. According to this method, the maximum pulse width that can be applied to each emission element 200 during one field can be set to 2 / M of one field. However, even in this method, the pulse width is twice as large as that of the conventional method, and there is a limit in performing higher-density display.

The present invention has been made in view of such a problem, and it is possible to suppress a decrease in maximum luminance even when the number of rows of electron-emitting devices constituting a display panel is increased. It is an object of the present invention to provide a matrix type display device which can increase the pulse width of a pulse to be generated and lower the clock frequency, and a display panel used for the same.

[0014]

According to the present invention, in order to solve the above-mentioned problems of the prior art, (A) a plurality of electron-emitting devices (200) having a plurality of rows and a plurality of columns are formed in a matrix. In the matrix type display device provided with the display panel (1000), two adjacent rows of the electron-emitting devices are connected to one row wiring (101) as one display wiring, and one column is connected to one row wiring (101). Wiring (102
a or 102b) is connected to every other row of the electron-emitting devices, and the devices to which adjacent column wirings are connected are different between the odd-numbered and even-numbered electron-emitting devices. (B) providing a matrix type display device characterized in that:
A plurality of electron-emitting devices (20
(0) is formed in a matrix.
In the matrix type display device provided with 0), as the display panel, two rows of adjacent elements in the electron-emitting device are connected to one row wiring (101).
Every other row of the electron-emitting devices is connected to one column wiring (102a or 102b), and the elements connected to adjacent column wirings are odd-numbered elements and even-numbered elements of the electron-emitting elements. A column driving circuit (4a, 4b) for simultaneously supplying two adjacent rows of image data in the electron-emitting device to column wirings of the display panel, and using the column driving circuit; And a row drive circuit (9) for supplying a scanning pulse to a row wiring connected to two adjacent rows of the electron-emitting devices in synchronization with the image data supplied by the device. (C) A display panel (1000) in which a plurality of electron-emitting devices (200) in a plurality of rows and a plurality of columns are formed in a matrix. There are, to connect the two lines of adjacent elements in the electron emitting device with respect to one row line (101), one column wiring (102a or 102b)
And every other row of the electron-emitting devices is connected to each other, and the devices connected to adjacent column wirings are different from each other in the odd-numbered and even-numbered rows of the electron-emitting devices. And a display panel characterized by the following.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a matrix type display device of the present invention and a display panel used for the same will be described with reference to the accompanying drawings. FIG. 1 is a diagram showing one embodiment of a display panel used in a matrix type display device of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the matrix type display device of the present invention, and FIG. FIG. 4 is a block diagram showing one embodiment of the display device, and FIG. 4 is a block diagram showing another embodiment of the matrix display device of the present invention. In FIGS. 1, 3, and 4, the same parts as those in FIGS. 5 and 7 are denoted by the same reference numerals.

In FIG. 1, a display panel 1000 includes a row wiring 101, column wirings 102a and 102b, and a row wiring 1
01 and a surface conduction electron-emitting device (hereinafter, emission device) 200 connected to the column wiring 102a or 102b. The row wirings 101 are arranged every other row in the row direction of the emission elements 200, that is, one row wiring 101 is arranged for every two rows of the emission elements 200. Also, column wiring 1
02a and 102b are twice as large as the arrangement of the emission elements 200 in the column direction. Note that the column wirings 102a, 102
The column b may be collectively referred to as a column wiring 102.

In this example, in the odd-numbered emission elements 200, the row wiring 101 located below the emission elements 200
And one element electrode 202a of the emission element 200 are connected by a conductor 103a, and a column wiring 102a located on the right side of the emission element 200 and the other element electrode 20a of the emission element 200 are connected.
2b are connected by a conducting wire 103b. In the emission elements 200 of the even-numbered rows, the row wiring 101 located above the emission elements 200 and one element electrode 2 of the emission elements 200
02a are connected by a conductor 103c, and the emission element 200
The column wiring 102b located on the left side of the column and the other element electrode 202b of the emission element 200 are connected by a conductor 103d.

As described above, in the display panel 1000, one row of the row wiring 101 is connected to the emission elements 200 of two rows, and the column wiring 102a connected to the emission elements 200 of the odd rows.
And the column wiring 102b connected to the emission elements 200 in the even rows.
Are alternately arranged in the column direction. In other words, the emission elements 200 connected to the adjacent column wirings 102a and 102b are different between the odd-row elements and the even-row elements.

FIG. 2 is a waveform diagram showing an example of a driving waveform of the display panel 1000 shown in FIG. FIG. 2 shows an operation when displaying the j-th column as an example, and shows a scanning pulse applied to the row wiring 101 and a data pulse applied to the column wirings 102a and 102b. Here, the number of bits of the video signal is 8 bits, perfect black is represented as 0, perfect white as 255, i-th row and j-th column are 128, i
+1 row j column is 255, i + 2 row j column is 64, i + 3 row j
The column shows the case of 0. Here, i is an odd number.

Since the row wiring 101 for the two emission elements 200 in the i-th row and the j-th column and the i + 1-th row and the j-th column is common, both of the scan pulses have the waveforms shown in FIG. However, the column wiring 102 for the two emission elements 200 in the i-th row and the j-th column and the i + 1-th row and the j-th column are separated, and the pulse width modulated data pulse for the emission element 200 in the i-th row and the j-th column is about half of the scanning period. 128T, and the pulse width modulated data pulse for the emission element 200 in the (i + 1) -th row and the j-th column is 255T in the entire scanning period.

When the scanning period of the i-th row and the (i + 1) -th row ends, i
The operation shifts to the scanning period of the +2 line and the i + 3 line. i + 2 row and i
The row wiring 101 is common to the +3 rows, and the scanning pulse has the waveform shown in FIG. Again column wiring 10
2 is separated, the data pulse for the i + 2 row j column emission element 200 is 64T as shown in FIG. 2C, and the data pulse for the i + 3 row j column emission element 200 is shown in FIG. ) As shown in FIG.

FIG. 3 is a block diagram showing an embodiment of a matrix type display device having the display panel 1000 shown in FIG. 1 and realizing the driving method shown in FIG. In the configuration of FIG. 3, different from FIG.
b, the latch circuit 3 is 3a, 3b, the PWM circuit 4 is 4a,
As shown in FIG. 4b, two circuits are provided. In FIG. 3, a video signal input to a terminal 1 is written to cascaded shift registers 2a and 2b. The image data for one row is parallelized by the shift register 2a, and its output is input to the shift register 2b.
The image data for a row becomes parallel.

The outputs of the shift registers 2a and 2b are respectively
Latched by the latch circuits 3a and 3b, and
Image data is input to the roads 4a and 4b. PWM circuit 4
a and 4b have pulse widths according to the size of the image data.
The data pulse to the column wiring 102a of the display panel 1000.
₁~ 102a_N, 102b₁~ 102b_NAt the same time
You. The output of the PWM circuit 4a and the output of the PWM circuit 4b are
They are connected alternately for each column of the column wiring 102. Column wiring 1
02 is connected to the odd-numbered emission elements 200.
2a₁~ 102a_NConnected to the emission elements 200 in the even rows.
102b ₁~ 102b_NAre alternating. Strange
Data pulse supplied to several rows of emission elements 200
The width modulation is performed by the PWM circuit 4b by the emission elements 200 in the even rows.
The pulse width modulation of the supplied data pulse is performed by the PWM circuit 4a.
Is responsible.

The synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift registers 2a and 2b, and supplies a latch clock to the latch circuits 3a and 3b. The timing control circuit 8 further includes a shift register 9
Is supplied with a pulse having one line width. The shift register 9 synchronizes the pulse with the data pulse output from the PWM circuits 4a and 4b, and
Scan pulses are sequentially input to _{1 to} 101 _{M / 2} from the first row. Since the row wiring 101 is common to the two rows of the emission elements 200, the scan pulse is shifted every two rows of the emission elements 200.

In such a configuration, the emission element 200
If the number of rows is M, the number of row wirings 101 is M / 2, so that one horizontal scanning period can take up to one field time T
v / M. That is, the pulse width can be doubled as compared with the case where the conventional display panel 10 is used. Therefore, the emission luminance can be doubled. Further, the unit time T of the pulse width modulation by the PWM circuits 4a and 4b is Tv × 2 / M / 255.
The clock frequency of the WM circuits 4a and 4b can be reduced. Further, in an application that does not require much light emission luminance, the voltage applied to the emission element 200 can be reduced, so that the breakdown voltage of the emission element 200 can be reduced.

FIG. 4 is a block diagram showing another embodiment of the matrix type display device having the display panel 1000 shown in FIG. 1, in which the display panel 1000 is driven by being divided into upper and lower parts. . The display panel 1000 thus divided is referred to as a display panel 2000.
The specific configuration of the display panel 2000 is the same as that of the display panel 1000 shown in FIG.

In the configuration of FIG. 4, unlike FIG. 3, the video signal input to the terminal 1 is divided by the division processing circuit 5 to drive the upper block of the display panel 2000; And a circuit for driving the lower block. Display panel 2000
Is driven by shift registers 2a and 2b, latch circuits 3a and 3b, PWM circuits 4a and 4b, and a shift register 9a, and a display panel 2000
Are driven by shift registers 2c and 2d, latch circuits 3c and 3d, PWM circuits 4c and 4d, and a shift register 9b.

Of the row wirings 101 of the display panel 2000,
Row wirings 101 _{1 to} 101 _{M / 4} are upper blocks, and row wirings 101 _{M / 4 + 1 to} 101 _{M / 2} are lower blocks. Column lines 102a ₁ ~102a _N column wiring 102b ₁ ~102b _N of the display panel 2000 is the upper block, the column wiring 1
02c _{1 to} 102c _N and column wirings 102d _{1 to} 102d _N are lower blocks.

According to this configuration, the number of rows of the emission elements 200 in one block of the display panel 2000 is half of the number M of rows of the emission elements 200 of the entire display panel 2000. Tv × 4 / M. Further, since the unit time T of the pulse width modulation by the PWM circuits 4a to 4d is Tv × 4 / M / 255, the clock frequency of the PWM circuits 4a to 4d can be further reduced. The pulse width is 2 in the configuration of FIG.
7 times that of the conventional example shown in FIG. The matrix type display device having the display panel 2000 can be driven with the same pulse width as the conventional example even if the number of rows of the emission elements 200 is increased up to four times that of the conventional example. It is possible to provide a simple display device.

The present invention is not limited to the above-described embodiment, and can be modified without departing from the gist of the present invention. Although not shown, the display panel 100
The arrangement of the 0,2000 conductors 103a to 103d is shown in FIG.
May be arranged symmetrically. In addition, the emission element 20
0 is not limited to a surface conduction electron-emitting device, but may be a metal / insulator /
Other electron-emitting devices such as a metal-type electron-emitting device may be used, and are generally applicable to cold-cathode-type electron-emitting devices. Further, the signal supplied to the column wirings 102 of the display panels 1000 and 2000 is not limited to the pulse width modulated signal, but may be an amplitude modulated signal or the like. In FIG. 4, the display panel 100
Although the display panel 2000 in which 0 is divided into upper and lower parts is used,
It may be divided into three or more.

[0031]

As described in detail above, the matrix type display device of the present invention and the display panel used for the same are of the type described below.
Two adjacent rows of the electron-emitting devices are connected to one row wiring, and every other row of the electron-emitting elements are connected to one column wiring. Since the elements to be connected are different between the odd-numbered elements and the even-numbered elements in the electron-emitting devices, the decrease in the maximum brightness can be suppressed even if the number of the electron-emitting devices constituting the display panel is increased. Further, the pulse width of the pulse for driving the display panel can be widened and the clock frequency can be lowered.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a display panel of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the matrix display device of the present invention.

FIG. 3 is a block diagram showing one embodiment of a matrix type display device of the present invention.

FIG. 4 is a block diagram showing another embodiment of the matrix type display device of the present invention.

FIG. 5 is a diagram illustrating an example of a conventional display panel.

FIG. 6 is a waveform chart for explaining the operation of a conventional matrix type display device.

FIG. 7 is a block diagram illustrating an example of a conventional matrix type display device.

[Explanation of symbols]

1, 7 terminal 2a, 2b, 2c, 2d shift register 3a, 3b, 3c, 3d latch circuit 4a, 4b, 4c, 4d pulse width modulation circuit (column drive circuit) 5 division processing circuit 8 timing control circuit 9, 9a, 9b shift register (row driving circuit) 101 row wiring 102a, 102b column wiring 200 surface conduction electron-emitting device 1000, 2000 display panel

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 641 G09G 3/20 641A 3/22 3/22 D 3/30 301 3/30 301 H01J 29 / 04 H01J 29/04 F-term (reference) 5C031 DD09 DD17 DD20 5C036 EE01 EE03 EF01 EF06 EF09 EG12 EG29 EG48 EH08 EH26 5C080 AA08 AA18 BB06 DD01 EE29 FF12 FF13 GG12 JJ02 JJ04 A04A01 A04 DBA

Claims (4)

[Claims] 1. A matrix-type display device comprising a display panel in which a plurality of electron-emitting devices in a plurality of rows and a plurality of columns are formed in a matrix, wherein the display panel comprises: Two adjacent rows of elements in the electron-emitting device are connected to each other, and every other row of the electron-emitting elements is connected to one column wiring, and the element to which each adjacent column wiring is connected is the electron-emitting element. A matrix-type display device, wherein the elements in odd-numbered rows and the elements in even-numbered rows are different from each other. 2. A matrix-type display device comprising a display panel in which a plurality of electron-emitting devices in a plurality of rows and a plurality of columns are formed in a matrix, wherein the display panel comprises: Two adjacent rows of elements in the electron-emitting device are connected to each other, and every other row of the electron-emitting elements is connected to one column wiring, and the element to which each adjacent column wiring is connected is the electron-emitting element. A column drive circuit that uses different elements in the odd-numbered rows and the even-numbered rows of the elements, and simultaneously supplies image data of two adjacent rows in the electron-emitting devices to column wirings of the display panel; Supplying a scanning pulse to a row wiring connected to adjacent two rows of the electron-emitting devices in synchronization with the image data supplied by the column driving circuit. Matrix display device characterized by being configured to provide a drive circuit. 3. The display device according to claim 2, wherein said column wiring is divided into a plurality of parts, said display panel is divided into a plurality of blocks, and said column drive circuit and said row drive circuit are provided in each of said plurality of blocks. Item 3. A matrix type display device according to item 2. 4. A display panel in which a plurality of electron-emitting devices in a plurality of rows and a plurality of columns are formed in a matrix, wherein two rows of adjacent elements in the electron-emitting devices are connected to one row wiring. Connecting one row of the electron-emitting devices to every other row of the electron-emitting devices, and connecting adjacent column wires to the odd-numbered and the even-numbered devices of the electron-emitting devices. And a display panel characterized by being different from each other.