JP2000148953A - Memory card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a flash memory, etc., of multiple bit configuration a basic element and to reduce test cost of a memory card performing an input-output operation of data in one-bit unit. SOLUTION: This memory card MC which makes a flash memory FMEM that inputs and outputs data, e.g. in 8-bit unit its basic element and performs an input-output operation of data according to a clock signal CLK in 1-bit unit through a data input-output terminal DAT is provided with a data input and output circuit IO that includes a template register storing template data inputted in the 1-bit unit through the terminal DAT in the 8-bit unit in a prescribed test mode and a data comparator circuit which compares and collates output data DO outputted from the memory FMEM in the 8-bit unit in the test mode with template data stored by the template register and outputs the results from the terminal DAT. It is also provided with a data inverting circuit which also uses an input register as a template register and is also for inverting template data stored by the input register bit by bit and writing it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card.
The present invention relates to a memory card of the "Media Card" (multimedia card) type or memory stick type, and a technique particularly effective for reducing the test cost.

[0002]

2. Description of the Related Art A memory array, in which memory cells of a two-layer gate structure are arranged in a lattice, is a basic constituent element. There is memory. In addition, there is a so-called MMC type or memory stick type memory card which mounts one or a plurality of such flash memories and is used for a digital still camera, a mobile phone device or the like. In these memory cards, the interface is simplified, and the stored data is
The data is input or output in one bit unit via one data terminal.

[0003] Regarding a memory stick type memory card, for example, "Nikkei Electronics, August 18, 1998 issue (No. 696)" issued by Nikkei McGraw-Hill Company, Ltd.
Page 13 to page 14.

[0004]

Prior to the present invention, the present inventors engaged in the development of an MMC type memory card equipped with one flash memory and a control unit for controlling the flash memory. I noticed the following problems: That is, this memory card has one data terminal, and inputs and outputs data in 1-bit units via this data terminal. However, with this memory card,
Since the data input / output operation in 1-bit units follows the test process as it is, it takes a relatively long time to write / read various test pattern data in 1-bit units. Causes an increase in test cost.

An object of the present invention is to reduce the test cost of a memory card which uses a flash memory or the like as a basic element and performs data input / output operation in 1-bit units.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, for example, a flash memory that inputs and outputs data in 8-bit units is used as its basic element,
For example, a memory card that performs data input / output operation in accordance with a clock signal in units of 1 bit, a template register that holds template data input in units of 1 bit in a predetermined test mode in units of 8 bits, A data input / output circuit including a data comparison circuit that compares data output from the flash memory or the like in units of 8 bits with template data held by a template register and outputs the result from one data terminal is provided. In addition, an input register is also used as the template register, and a data inverting circuit for inverting and writing the template data held by the input register bit by bit is provided.

According to the above means, it is possible to efficiently generate various test data bit-inverted based on the template data and efficiently input the test data to a flash memory or the like in units of 8 bits. The test data output in 8-bit units is compared with the template data in one cycle, and the result can be output in 1-bit units. As a result, it is possible to efficiently generate, write, read, and compare and compare the test data with the flash memory or the like, thereby reducing the test cost of the memory card.

[0009]

FIG. 1 is a block diagram showing one embodiment of a memory card MC to which the present invention is applied. FIGS. 2A and 2B show the external structure of an embodiment in which the control unit CTLU of the memory card MC of FIG. 1 is formed in a different package from the flash memory FMEM or in the same package. The figures are each shown. First, the configuration and operation of the memory card MC of this embodiment and an outline of the external structure will be described with reference to these drawings.

In the following description except for the part related to FIG. 2B, the control unit CTLU is formed in a package different from the flash memory FMEM. The circuit elements constituting each block of the control unit CTLU and the flash memory FMEM are not particularly limited, but known MOSFETs (metal oxide semiconductor type field effect transistors. Each of them is formed on a semiconductor substrate surface, such as single crystal silicon, by an integrated circuit manufacturing technique (collectively, effect transistors). Further, FIG. 2 is a plan view of the memory card MC as viewed from the upper surface thereof. In the following description regarding the external structure, the top, bottom, left, and right are represented by the positional relationship of FIG.

In FIG. 1, the memory card MC of this embodiment includes, but is not limited to, one flash memory FMEM and a control unit CTLU for controlling the same. These flash memories F
The MEM and control unit CTLU are shown in FIG.
As illustrated in (a), they are independently formed as an IC package ICP1 or ICP2, are mounted on a single board having a connector CN at the left end thereof, and are electrically coupled to each other. Control unit CTL
The board with U and flash memory FMEM
The whole except the connector electrode portion is protected by a predetermined plastic material.

Incidentally, the control unit CTLU of the memory card MC can be formed on the same semiconductor substrate surface as the flash memory FMEM. In this case, as illustrated in FIG. 2B, the memory card MC is further reduced in size as compared with a case where the control unit CTLU is formed in a separate package.

In this embodiment, the memory card MC
Is used as a storage element of a mobile phone, although not particularly limited. At the left end of the port on which the control unit CTLU and the flash memory FMEM are mounted, as described above, a connector CN for electrically connecting the memory card MC to the mobile phone is provided. Although not particularly limited, is composed of six electrodes C2 to C7 and another electrode C1 not shown, that is, a total of seven electrodes C1 to C7.

Among the electrodes C1 to C7 constituting the connector CN, the electrode C1 is provided in preparation for a future interface expansion and is in an open state. The electrode C5 is provided as a clock input terminal CLK for inputting a clock signal CLK, and the electrode C2 is used as a command input terminal CMD for inputting a command and an address to the memory card MC and outputting a response. Is done. Further, the electrode C7 is provided as n data terminals, that is, only one data terminal, that is, a data input / output terminal DAT, and the electrodes C4 and C3 and C6 are provided as a power supply voltage supply terminal VDD and ground potential supply terminals VSS1 and VSS2, respectively. You.

On the other hand, the control unit CTLU
Although not particularly limited, it includes a memory controller MCTL, an address register counter AC, a multiplexer MX, a data input / output circuit IO, and an internal voltage generation circuit VG.

The memory controller MCTL of the control unit CTLU is a controller of a so-called program control system, and has a clock signal CL inputted from the main control circuit of the portable telephone device via the electrodes C5 and C2.
K and the command CMD and the ready / busy signal R / BB input from the flash memory FMEM (here, for a so-called inverted signal or the like which is selectively set to a low level when it is enabled, B is added to the end of its name. Based on the above, the operation mode to be executed by the memory card MC is determined, and each unit of the control unit CTLU is controlled and controlled. In addition, a serial clock signal SC for the flash memory FMEM is generated based on the clock signal CLK, and a chip enable signal CEB, a write enable signal WEB, an output enable signal OEB, and a command data enable are set according to the operation mode of the memory card MC. Signal CDE
B and the reset signal RESB are selectively formed,
Supply.

On the other hand, the address register counter AC of the control unit CTLU holds the address signal AD supplied as part of the command CMD and extracted by the memory controller MCTL, and counts up the address signal AD in accordance with an internal control signal (not shown). ,
An address signal ADC is generated. Further, the data input / output circuit IO sequentially takes in data serially input in 1-bit units via the electrode C7, and outputs the input data DI, that is, DI0 to DI7, in multiplexers in 8-bit units.
X, and also takes in parallel output data DO, that is, DO0 to DO7, transmitted in 8-bit units from the flash memory FMEM via the multiplexer MX, and outputs them in 1-bit units via the electrode C7.

Next, the multiplexer MX of the control unit CTLU includes a command CM supplied from the memory controller MCTL and an address register counter A.
C, the input signal DI supplied from the data input / output circuit IO or the input signal DI supplied from the data input / output circuit IO.
0 to DI7 are combined under predetermined conditions, transmitted to the flash memory FMEM via the data input / output terminals IO0 to IO7, and read data output from the flash memory FMEM via the data input / output terminals IO0 to IO7 is output. The data is transmitted to the data input / output circuit IO as data DO, that is, DO0 to DO7. Further, the internal voltage generation circuit VG transmits the power supply voltage VDD and the ground potentials VSS1 and VSS2 supplied via the electrodes C4, C3 and C6 to each unit including the flash memory FMEM, and based on the power supply voltage VDD. Generates various necessary internal voltages and supplies them to each unit.

The specific configuration of the flash memory FMEM of the memory card MC and the data input / output circuit IO of the control unit CTLU and the memory card MC
The specific operation and the like in the test mode will be described later in detail.

FIG. 3 is a block diagram showing one embodiment of the flash memory FMEM included in the memory card MC of FIG. The configuration and operation of the flash memory FMEM included in the memory card MC will be described with reference to FIG.

Referring to FIG. 3, a flash memory FMEM of this embodiment has a memory array MARY arranged so as to occupy most of the surface of a semiconductor substrate as its basic component. The memory array MARY includes a predetermined number of word lines arranged in parallel in the horizontal direction in the figure, and a predetermined number of bit lines arranged in parallel in the vertical direction in the figure. At the intersections of these word lines and bit lines, a large number of two-layer gate structure type memory cells having a floating gate and a control gate are arranged in a lattice.

The word lines forming the memory array MARY are connected to the X address decoder XD on the left side, and the bit lines are connected to the sense amplifier register SRG below the word lines. The X address decoder XD is supplied with, for example, a 14-bit internal X address signal from the X address buffer XB, and a write pulse WP from the memory control circuit MC. Further, the X address buffer XB has m data input / output terminals I, that is, eight data input / output terminals I
For example, a 14-bit X address signal, that is, a sector address signal is supplied from O0 to IO7 through the first output terminal of the input / output multiplexer MXF in two start cycles in a time-division manner, and the memory control is performed. Circuit M
C supplies internal control signals XL1 and XL2.

The X address buffer XB takes in, for example, an 8-bit lower sector address signal SA1 supplied from the data input / output terminals IO0 to IO7 via the input / output multiplexer MXF according to the internal control signal XL1, and
The bit upper sector address signal SA2 is taken in according to the internal control signal XL2. Then, while holding these sector address signals SA1 and SA2, an internal X address signal of a total of 14 bits composed of a non-inverted signal and an inverted signal is formed based on the signal, and the X address decoder XD
To supply. Further, X address decoder XD decodes the internal X address signal supplied from X address buffer XB, and sets the corresponding word line of memory array MARY to a predetermined selection or non-selection level.

Next, the sense amplifier register SRG is
The memory array includes a predetermined number of sense amplifiers, write amplifiers and data registers provided corresponding to each bit line of the memory array MARY. Of these, one input / output node of each sense amplifier and write amplifier is connected to the memory array MARY.
, And the other input / output node is connected to one input / output node of the corresponding data register. The other input / output node of each data register is selectively connected to the output terminal of the data input buffer IB or the input terminal of the data output buffer OB in 8-bit units via a Y gate circuit YG. The input terminal of the data input buffer IB and the output terminal of the data output buffer OB are connected to the input / output multiplexer MX.
F is coupled to one of the output and input terminals, respectively.
The other input / output terminal of input / output multiplexer MXF is coupled to data input / output terminals IO0-IO7.

The Y gate circuit YG is supplied with a bit line selection signal of a predetermined bit from the Y address decoder YD. The Y address decoder YD is supplied with an internal Y address signal of a predetermined bit from the Y address counter YC, and the Y address counter YC has a memory control circuit M
The internal clock signal YCC is supplied from C. The data input buffer IB is supplied with an input control signal IC from the memory control circuit MC, and the data output buffer OB is supplied with an output control signal OC.

When the flash memory FMEM is set to the selected state, the Y address counter YC performs a stepping operation in accordance with the internal clock signal YCC, and outputs a predetermined bit of the internal Y value.
Address signals are sequentially formed to form a Y address decoder YD.
To supply. Further, the Y address decoder YD decodes the internal Y address signal supplied from the Y address counter YC and selectively sets a corresponding bit of the bit line selection signal to a high level. The Y gate circuit YG receives the high level of the bit line selection signal, selects eight corresponding data registers of the sense amplifier register SRG, and selectively connects the data input buffer IB or the data output buffer OB. And

On the other hand, when the flash memory FMEM is set to the selected state in the write mode, the data input buffer IB stores write data input in 8-bit units from the data input / output terminals IO0 to IO7 via the input / output multiplexer MXF. , Sequentially in accordance with the input control signal IC, and sequentially transmitted to eight designated data registers of the sense amplifier register SRG via the Y gate circuit YG. When the flash memory FMEM is set to the selected state in the read mode, the data output buffer OB is output in 8-bit units from the specified eight data registers of the sense amplifier register SRG via the Y gate circuit YG. The read data is output to the output control signal OC.
, And sequentially output from the input / output multiplexer MXF via the data input / output terminals IO0 to IO7.

Thus, the data input / output terminals IO0-I
The write data serially input in units of 8 bits via O7 is sequentially taken into the data register of the sense amplifier register SRG, and then is written to a predetermined number of memory cells coupled to the selected word line of the memory array MARY. Written all at once. Further, read data read out from a predetermined number of memory cells coupled to a selected word line of the memory array MARY in word line units, that is, in sector units, is simultaneously amplified by a sense amplifier of a sense amplifier register SRG, and is read in parallel to the data register. After that, the data is sequentially transmitted to the data output buffer OB in 8-bit units, and the data input / output terminals IO0 to IO0 are input.
Serially output from IO7.

The flash memory FMEM further includes a control buffer CB, a memory control circuit MC, and an internal voltage generation circuit VGF. The control buffer CB receives a serial clock signal SC, a chip enable signal CEB, and a write enable signal WE from the control unit CTLU via external terminals SC, CEB, WEB, OEB, CDEB and RESB.
B, an output enable signal OEB, a command enable signal CDEB, and a reset signal RESB are supplied, respectively, and a ready / busy signal R / BB as an output signal thereof is provided.
Is connected to the control unit C via the external terminal R / BB.
Output to TLU. Various internal signals corresponding to the activation control signals are supplied from the control buffer CB to the memory control circuit MC, and the internal voltage generation circuit VGF is supplied with the power supply voltage VDD via the external terminals VDD and VSS.
And the ground potential VSS.

The control buffer CB of the flash memory FMEM receives the serial clock signal SC, chip enable signal CEB, write enable signal WEB, output enable signal OEB, command enable signal CDEB and reset signal RESB supplied from the control unit CTLU. In addition to transmitting to the memory control circuit MC, the ready / busy signal R / BB output from the memory control circuit MC is transmitted to the control unit CTLU.

On the other hand, the memory control circuit MC includes a serial clock signal SC, a chip enable signal CEB, a write enable signal WEB, an output enable signal OEB, and a command enable signal CDE supplied from the control unit CTLU via the control buffer CB.
B and the reset signal RESB, the above various internal control signals are selectively formed, and the flash memory F
Supply to each part of MEM. In a write mode which is performed in sector units and takes a relatively long time, the ready / busy signal R / BB is set to a low level at the end of the write operation and the verify operation for confirming the write operation, and a series of corresponding operations are performed. The control unit CTLU is notified of the end.

The internal voltage generation circuit VGF generates various internal voltages necessary for a write operation, an erase operation, a read operation and the like based on a power supply voltage VDD and a ground potential VSS supplied from the control unit CTLU. To supply.

FIG. 4 is a block diagram showing one embodiment of the data input / output circuit IO included in the memory card MC of FIG. FIG. 5 is a circuit diagram showing one embodiment of the input register IREG and the data inversion circuit DINV included in the data input / output circuit IO of FIG. FIG. 6 is a circuit diagram of an embodiment of the output register OREG and the output buffer OBUF included in the data input / output circuit IO of FIG. 4, and FIG.
A circuit diagram of one embodiment of the MP is shown. With reference to these figures, the specific configuration and operation of the data input / output circuit IO included in the memory card MC and the features thereof will be described. In FIG. 5, the unit input register UIREG
0 and the unit data inversion circuit UDINV0, the unit input registers UIREG0 to UIREG7 and the unit data inversion circuits UDINV0 to UDINV7 will be described. In FIG.
G0-OUREG7 and unit output buffer UOBU
F0 to UOBUF7 will be described.

In FIG. 4, the data input / output circuit IO of this embodiment is not particularly limited, but the input register IRE
G, a data inversion circuit DINV, an output register OREG,
Output buffer OBUF and data comparison circuit DCMP
Consists of Of these, write data including test template data is input to the input register IREG via the data input / output terminal DAT in 1-bit units, and 8-bit input latch signals IL0 to IL7 are supplied from the memory controller MCTL. Is done. The data inverting circuit DINV is supplied with internal signals I0 to I7 as output signals from the input register IREG, and also receives internal control signals VT and P from the memory controller MCTL.
T is supplied. The output signal of the data inversion circuit DINV is input to the multiplexer M as input data DI0 to DI7.
X.

On the other hand, the output register OREG has 8-bit output data DO0 to DO7 from the multiplexer MX.
And an output latch signal OL is supplied from the memory controller MCTL. Also, the output buffer OBUF
Supplied from the output register OREG, that is, the internal signals O0 to O7, and the memory controller MC
Output control signals OC0 to OC7 are supplied from TL. Further, one input terminal of the data comparison circuit DCMP is
The output data DO0 to DO7 from the multiplexer MX
Are supplied to the other input terminal, and input data DI0 to DI7 are supplied from the data inversion circuit DINV.
The read data, which is the output signal of the output buffer OBUF, and the test output signal, which is the output signal of the data comparison circuit DCMP, are output in 1-bit units via the data input / output terminal DAT.

Here, as shown in FIG. 5, the input register IREG of the data input / output circuit IO includes eight unit input registers UIREG0 to UIREG7, each of which is connected to the unit input register U.
As represented by IREG0, two inverters V1 and V3 composed of clocked inverters and a normal CMO
Inverter V2 composed of S (complementary MOS) inverter
And

The input terminal of the inverter V1 of each unit input register of the input register IREG is connected to a data input / output terminal D.
The output terminal of the inverter V2 is commonly coupled to the input terminal of the inverter V2 and the output terminal of the inverter V3. In addition, the inverter V2 of each input register
And the input terminal of the inverter V3 are commonly coupled, and the potentials at these commonly coupled nodes are set as the internal signals I0 to I7 as the data inverting circuit D7.
It is supplied to the corresponding unit circuit of INV. The non-inverting control terminal of the inverter V1 and the inverting control terminal of the inverter V3 have corresponding input latch signals IL0 to IL7.
Are supplied respectively.

Needless to say, the unit input register UIR
Inverter V1 forming EG0 to IREREG7 selectively enters a transmission state in response to the high level of corresponding input latch signal IL0 to IL7. The inverter V3 of each unit input register is connected to the corresponding input latch signal IL0.
ＩＬIL7 are selectively transmitted when receiving the low level of IL7, and are latched together with the inverter V2.

From these, the data input / output terminal DA
The write data or test template data serially input in 1-bit units via T is input to the corresponding unit input register of the input register IREG by alternately setting the input latch signals IL0 to IL7 to high level. UIREG0 to UIREG7 selectively take in and hold it. These data are transmitted to the data inversion circuit DINV in 8-bit units as internal signals I0 to I7,
Bit inversion is selectively performed.

On the other hand, the data inverting circuit DINV includes eight unit data inverting circuits UDINV0 to UDINV7. Each of these unit data inverting circuits includes a clocked inverter as represented by the unit data inverting circuit UDINV0. Two inverters V4 and V6
And one inverter V5 composed of a normal CMOS inverter. Of these, the input terminals of the inverters V4 and V5 of each unit data inverting circuit are connected to the input register I.
REG corresponding unit input registers UIREG0 to UIREG
Internal signals I0 to I7, which are output signals, are supplied from REG7, and the input terminals of inverter V6 are respectively coupled to the output terminals of corresponding inverter V5. The output terminals of the inverters V4 and V6 are commonly coupled, and the potential at these commonly coupled nodes is supplied to the multiplexer MX as the input data DI0 to DI7. The internal control signal VT is commonly supplied to the non-inverting control terminal of the inverter V4 of each unit data inverting circuit, and the internal control signal PT is commonly supplied to the non-inverting control terminal of the inverter V6.

Needless to say, the unit data inversion circuit UD
The inverter V4 constituting INV0 to UDINV7 is
The internal control signal VT is set to the high level to be in a transmission state all at once, and the inverter V6 is simultaneously set to the transmission state by the internal control signal PT being set to the high level. Thus, when the internal control signal VT is at a high level, the internal signals I0 to I7, which are output signals of the input register IREG, correspond to the corresponding unit input registers UIREG0 to UIREG.
The input data DI0 to DI7 are respectively inverted by the inverter V4 of the REG7, and when the internal control signal PT is set to the high level, the data is transmitted without being inverted at the original logic level via the inverters V5 and V6. The input data becomes DI0 to DI7.

Next, as shown in FIG. 6, the output register OREG of the data input / output circuit IO includes eight unit output registers UOREG0 to UOREG7, each of which is a unit output register UOREG.
As represented by REG0, it includes two inverters V7 and V9 formed of clocked inverters and one inverter V8 formed of a normal CMOS inverter.

Unit output registers UOREG0 to UORE
The corresponding output data DO0 to DO7 are supplied from the multiplexer MX to the input terminal of the inverter V7 of G7, and the output terminals are commonly coupled to the input terminal of the corresponding inverter V8 and the output terminal of the inverter V9, respectively. In addition, the inverter V of each unit output register
8 and the input terminal of the inverter V9 are respectively commonly coupled, and the potentials at these commonly coupled nodes are the corresponding unit output buffers UOBUF0 to UOBUF of the output buffer OBUF as the internal signals O0 to O7.
The signals are supplied to the OBUF 7 respectively. The non-inversion control terminal of the inverter V7 and the inversion control terminal of the inverter V9 have
The output latch signal OL is supplied in common.

Needless to say, the unit output register UOR
Inverters V7 of EG0 to UOREG7 selectively enter a transmission state in response to the high level of output latch signal OL, and inverter V9 selectively enters a transmission state in response to the low level.

As a result, the read data, that is, the output data DO0 to DO7 output in units of 8 bits via the multiplexer MX receives the high level of the output latch signal OL, and the corresponding unit input registers UIREG0 to UIREG7 of the output register OREG. Is selectively captured and retained. These data are stored in internal signals O0 to O
7 is transmitted to the output buffer OBUF in 8-bit units.

On the other hand, the output buffer OBUF includes eight unit output buffers UOBUF0 to UOBUF7. Each of these unit output buffers is a single unit composed of a normal CMOS inverter as represented by the unit output buffer UOBUF0. Inverter VA (where 10
The serial number of the element exceeding the number is expressed by an alphabet. Hereinafter the same) and one inverter VB composed of a clocked inverter.

Inverter VA constituting unit output buffers UOBUF0 to UOBUF7 of output buffer OBUF
Are supplied from the corresponding unit output registers UOREG0 to UOREG7 of the output register OREG, and the input terminals of the inverter VB are respectively coupled to the output terminals of the corresponding inverter VA. Is done. The output terminal of inverter VB is commonly coupled to data input / output terminal DAT. The corresponding output control signals OC0 to OC7 are supplied to the non-inverting control terminals of the inverter VB.

Needless to say, the inverter VB of each unit output buffer has a corresponding output control signal OC0 to OC7.
Is set to the high level, the transmission state is alternatively set.
As a result, the internal signals O0 to O7, which are output signals of the output register OREG, are set to the high level by selectively setting the output control signals OC0 to OC7 to the data input / output terminal DA.
From T, one bit is output alternatively.

Next, as shown in FIG. 7, the data comparison circuit DCMP of the data input / output circuit IO includes eight exclusive OR circuits EXO1 to EXO8 and one OR (OR).
It includes a gate OG1 and a buffer B1. One of the input terminals of the exclusive OR circuits EXO1 to EXO8 is supplied with the corresponding input data DI0 to DI7 from the input register IREG, and the other input terminal is provided with the corresponding input data of the output register OREG. Output signals of unit output registers UOREG0 to UOREG7, that is, internal signals O0 to O7 are supplied, respectively. The output signals of the exclusive OR circuits EXO1 to EXO8 are OR gates OG1
Are supplied to the first to eighth input terminals, respectively. The output signal of the OR gate OG1 is output from the buffer B1 via the data input / output terminal DAT. The non-inverting control terminal of the buffer B1 has a memory controller MCT
The output control signal TOC is supplied from L.

Needless to say, the exclusive OR circuit EXO
1 to EXO8 are input data DI0 to DI7.
Are set to the low level when the logical level of the corresponding bit of the internal signal O0 to O7 is the same as the logical level of the corresponding bit of the internal signal O0 to O7, and set to the high level when they do not match. When the output signals of the exclusive OR circuits EXO1 to EXO8 are all at a low level, in other words, all the corresponding bits of the input data DI0 to DI7 and the corresponding bits of the internal signals O0 to O7 match. At a low level, and when any of them is at a high level, in other words, the input data DI0 to DI7 and the internal signal O0
When .O7 does not match any of the bits, it is selectively set to the high level. Further, the buffer B1 is selectively set to the transmission state in response to the high level of the output control signal TOC, inverts the output signal of the OR gate OG1, and outputs the inverted signal from the data input / output terminal DAT.

As a result, the data comparison circuit DCMP
In a predetermined test mode, input data DI0 to DI
7, template data held by the input register IREG and selectively bit-inverted by the data inverting circuit DINV, and read data output from the internal signals O0 to O7, that is, the flash memory FMEM in 8-bit units and held by the output register OREG And outputs a high-level test output signal from the data input / output terminal DAT when both data match, and outputs a low-level test output signal when the data does not match. It works to output from.

FIG. 8 shows a signal waveform diagram of one embodiment when normal data or template data is input to the memory card MC of FIG. FIG. 9 is a signal waveform diagram of one embodiment at the time of writing the template data to the memory in the test mode of the memory card MC of FIG.
FIG. 10 shows a signal waveform diagram of an embodiment at the time of memory reading in the test mode. With reference to these figures, the operation of the memory card MC of this embodiment in the test mode when template data is input, written and read will be specifically described.

The memory card MC of this embodiment is
Prior to the input operation of the normal data or the template data, a command, an address and a response are exchanged via the command input terminal CMD with the main control circuit of the portable telephone device. Shown. In FIG. 10, it is assumed that an error has occurred in the read data RD4 of the flash memory FMEM, and processing waveforms related thereto are shown.
In each signal waveform diagram, each signal has the power supply voltage VDD at its high level and the ground potential VSS at its low level.

In FIG. 8, the memory card MC which has completed the exchange of the command, address and response with the main control circuit of the portable telephone device has a data input / output terminal DAT in units of 1 bit, for example, 8 bits. The normal write data or template data, that is, input data ID0 to ID7 are serially input. Although the input data ID0 to ID7 are not particularly limited, their logical levels are changed in synchronization with the rising edge of the clock signal CLK, and the logical levels are sufficiently determined at the falling edge of the clock signal CLK. Is done.

The memory controller M of the memory card MC
In the CTL, in response to the falling edge of the clock signal CLK, the input latch signals IL0 to IL7 are sequentially temporarily set to the high level for a predetermined period. In the input register IREG of the memory card MC, first, the first input data ID0 is taken into the unit input register UIREG0 in response to the rising edge of the input latch signal IL0,
Will be retained. In response to the rising edge of the second input latch signal IL1, the input data ID1 is taken into the unit input register UIREG1, and in response to the rising edges of the input latch signals IL2 to IL7, the remaining input data ID2 to ID7 are unit input. Register UIRE
G2 to IREREG7 sequentially take in and hold.

Thus, the input data ID serially input in units of 1 bit via the data input / output terminal DAT
0 to ID7 correspond to the unit input registers UIREG0 to UIREG0 of the input register IREG in a serial-parallel conversion form.
Captured by UIREG7, flash memory FMEM
Wait for a write operation on.

Next, referring to FIG.
The MEM is selectively selected by setting the chip enable signal CEB to the low level, and waits for input of a write command via the data input / output terminals IO0 to IO7. In the first cycle cy1, a write command WC from the control unit CTLU to the flash memory FMEM is applied to the data input / output terminals IO0 to IO7.
M is input, and write destination sector addresses SA1 and SA2 are input in the next cycles cy2 and cy3.
At this time, the write enable signal WEB is output in the cycle c.
The low level is repeatedly changed from the low level to the high level so that the middle point of y1 to cy3 rises, and the command data enable signal CDEB is temporarily set to the low level so as to include the middle point of the cycle cy1 to which the write command WCM is input. You.

The memory control circuit MC of the flash memory FMEM receives the write command WCM in the cycle cy1.
Of the sector address S in cycles cy2 and cy3.
In response to the inputs of A1 and SA2, a sector in which a write operation is to be performed, that is, a word line is recognized, and a selection operation thereof is started. During this time, the serial clock signal SC is fixed at a low level.

The memory controller MCTL of the control unit CTLU sets the command data enable signal CDEB to the low level again at a predetermined timing when the operation of selecting the word line in the memory array MARY of the flash memory FMEM is completed, and also controls the data inversion circuit DINV. The internal control signals PT and VT are sequentially and alternately set to the high level for one cycle period. Also,
The serial clock signal SC is repeatedly set to a high level in order to set the intermediate point between the cycles cy4 to cyq to a rising level,
The write enable signal WEB is changed to the low level only once so that the middle point of the cycle cyr, which is one cycle later, is set as the rising.

Thus, in cycles cy4 to cyq, the input register IR of the control unit CTLU is
Non-inverted data TDT and inverted data TDB of template data TD from EG via data inverting circuit DINV
Are alternately supplied as input data DI0 to DI7 to the multiplexer MX and transmitted to the data input / output terminals IO0 to IO7 of the flash memory FMEM. In the cycle cyr, a write start command SCM is output from the memory controller MCTL of the control unit CTLU and transmitted to the data input / output terminals IO0 to IO7.

As described above, the memory card MC of this embodiment is
In, the template data required for the function test is held by the input register IREG and used repeatedly, and is input to the flash memory FMEM in units of 8 bits, thereby speeding up the input operation of the test write data. The template data is bit-inverted selectively by a data inversion circuit DINV provided in the control unit CTLU to become inverted data TDB, and a test pattern effective for a functional test is automatically generated. , Internal control signal P
It is selectively changed by setting T and VT to a high level in an appropriate combination. As a result, the memory card M
The function test of C can be performed efficiently and effectively, thereby reducing the test cost of the memory card MC.

The non-inverted data TDT and inverted data TDB of the template data TD of the data input / output terminals IO0 to IO7 in the cycles cy4 to cyq are supplied from the input / output multiplexer MXF of the flash memory FMEM via the data input buffer IB and the Y gate circuit YG. Then, the data is sequentially taken into and held by the corresponding eight data registers of the sense amplifier register SARG. Then, when the write start command SCM is input in the cycle cyr immediately after the inverted data TDB of the cycle cyq is taken into the sense amplifier register SRG, the ready / busy signal R / BB becomes low by the memory control circuit MC of the flash memory FMEM. And q for the selected sector
Writing of 3-byte test data is started.

As is well known, flash memory FMEM
Requires a relatively long time of, for example, about 1 ms (millisecond), during which time the memory controller MCTL of the control unit CTLU is used.
Receive a low level of the ready / busy signal R / BB and enter a waiting state. Also, the memory controller MC
When the ready / busy signal R / BB is returned to the high level, the TL identifies that the write operation for the specified sector is completed, and repeats the write operation for the remaining sectors. When the operation of writing the test data to all the sectors to be tested is completed, the operation shifts to the next test read operation.

As shown in FIG. 10, the test read operation of the flash memory FMEM is performed after the chip enable signal CEB is set to low level,
The process is started when a read command RCM is input to the data input / output terminals IO0 to IO7 of the MEM. At this time, the write enable signal WEB is temporarily set to the low level for three cycles as in the case of the write operation, and the command data enable signal CDEB is temporarily set to the low level for one cycle.

The data input / output terminals IO0 to IO7 of the flash memory FMEM have a sector address SA for designating a read sector following the read command RCM.
1 and SA2 are input from the control unit CTLU. After the sector address SA2 is input,
The data input / output terminals IO0 to IO7 are set to a high impedance state Hz, but unspecified data is output when the output enable signal OEB is set to a low level.
Eventually, when the read operation of the flash memory FMEM becomes possible, the read data RD0 to
RD7 and the like are sequentially output according to the serial clock signal SC. Note that the read data RD0 to RD7 and the like are the non-inverted data T of the previously written template data TD.
Needless to say, it corresponds to DT or inverted data TDB.

Read data RD output from flash memory FMEM to data input / output terminals IO0 to IO7
After passing through the multiplexer MX of the control unit CTLU, the output registers OREG of the data input / output circuit IO become output data DO0 to DO7.
Is transmitted to The memory controller MCTL repeatedly sets the output latch signal OL to a high level at an intermediate point of a cycle in which the read data RD0 to RD7 and the like are input, and at a point slightly after the first rise of the output latch signal OL, The signal TOC is set to a high level. Further, in each cycle period of the output latch signal OL, the internal control signals PT and VT (not shown) are alternately set to the high level in the same combination as at the time of writing.

The multiplexer MX of the control unit CTLU to the output register O of the data input / output circuit IO
The output data DO0 to DO7 transmitted to the REG, that is, the read data RD0 to RD7 and the like are output from the output latch signal OL.
Is received by the output register OREG and transmitted as internal signals O0 to O7 to one input terminal of the data comparison circuit DCMP. The other input terminal of the data comparison circuit DCMP has an internal control signal P
From the data inversion circuit DINV receiving T and VT, non-inverted data TDT and inverted data TDB of the template data TD held by the input register IREG are alternately input. Data input / output terminal D of memory card MC
AT is changed from the high impedance state Hz to the high level output state when the output control signal TOC is set to the high level.

Here, the data comparison circuit DCMP sequentially compares the corresponding 8 bits of the read data RD0 to RD7 and the non-inverted data TDT or TDB of the template data TD input from the data inversion circuit DINV. When the logical levels of both data coincide with all the bits, the output signal OG1out of the OR gate OG1 becomes low level.
A high level is output to T. When the logic level of any bit is different and the two data do not match, the output signal OG1out of the OR gate OG1 changes to a high level, and in response to this, a low level is output to the data input / output terminal DAT.

As described above, the memory card MC of this embodiment is
Thus, despite the fact that only one data terminal is provided for data input / output, the read data RD0 to RD7 in the test mode are compared and collated with the template data TD or its inverted data in 8-bit units, It is output as a 1-bit test output signal from the data input / output terminal DAT. As a result, the time required for the function test of the memory card MC is reduced to one-eighth as compared with the conventional case where the comparison operation of the read data is performed in 1-bit units, and the test cost of the memory card MC is correspondingly reduced. Will be.

The operation and effect obtained from the above embodiment are as follows. That is, (1) For example, a flash memory or the like that inputs and outputs data in units of 8 bits is used as a basic element, and a memory card that performs input and output operations of data in accordance with a clock signal in units of 1 bit is stored in a predetermined test mode. A template register that holds template data input in units of bits in units of 8 bits; and a template register that holds data output in units of 8 bits from a flash memory or the like in the test mode.
By providing a data input / output circuit including a data comparison circuit for comparing and collating on a bit basis and outputting the result from one data terminal and a data inversion circuit for inverting and writing template data bit by bit, Test data of various patterns, bit-inverted based on template data, can be efficiently generated and efficiently input to a flash memory or the like in 8-bit units, and output from the flash memory or the like in 8-bit units. The effect is obtained that the test data can be compared with the template data in one cycle and the result can be output in 1-bit units.

(2) In the above item (1), by using the input register for holding ordinary write data as the template register, the above-mentioned effects can be obtained while reducing the number of required elements of the memory card. it can. (3) According to the above items (1) and (2), the operation of generating, writing, reading, and comparing and comparing test data for a flash memory or the like can be made more efficient, thereby reducing the test cost of the memory card. Can be

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the memory card MC can include an arbitrary number of flash memories FMEM, and the control unit CTLU can be provided in the flash memory FMEM as described above. The memory card MC can input / output data in an arbitrary number n, that is, for example, in units of 2 bits or 3 bits smaller than the bit configuration of the flash memory. The connector CN provided on the memory card MC can have an arbitrary number of electrodes, and the use of each electrode can be arbitrarily set. The block configuration of the memory card MC and its control unit CTLU can take various embodiments without being restricted by the present embodiment, and the interface between the memory card MC and the control unit CTLU and the flash memory FMEM, The same applies to the polarity of the power supply voltage and the like.

In FIG. 2, the shape of the memory card MC, the arrangement of the IC packages (ICP1 and ICP2), and the arrangement of the connector CN can take various embodiments. Also,
In this embodiment, the flash memory FMEM and the control unit CTLU are mounted on a board in the form of a package. However, these integrated circuits may be mounted on the board in a so-called bare chip form, for example, as a chip.

In FIG. 3, the memory array MARY is
Any number of redundant elements can be included, and the memory array MARY as well as its immediate periphery can be divided into any number of memory mats. Flash memory FME
M corresponding to the bit configuration of M is, for example, 4 or 16;
It can be set arbitrarily. Further, the block configuration of the flash memory FMEM, the names and combinations of the activation control signals, and the like can adopt various embodiments without being limited by the present embodiment.

In FIG. 4, the control unit CT
The block configuration of the data input / output circuit IO of the LU may be variously conceived. The input register IREG, the data inversion circuit DINV, and the output register O shown in FIGS.
The same applies to the specific configurations of the REG, the output buffer OBUF, and the data comparison circuit DCMP. 8 to 10, the specific level and time relationship of each signal is an example, and various embodiments can be adopted without being limited by these examples.

In the above description, the case where the invention made by the present inventor is mainly applied to an MMC type memory card using a flash memory as a basic element, which is a background field of application, has been described. For example, the present invention can be applied to a memory stick type memory card, and various semiconductor memories such as an EEPROM (electrically erasable / rewritable read only memory) and a dynamic RAM (random access memory) are used as basic elements. The present invention can also be applied to a memory card that performs the operation. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a memory card that uses a semiconductor memory that performs data input / output operation in units of at least predetermined bits as its basic element and performs data input / output operation in units of fewer bits.

[0077]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for example, a flash memory or the like that inputs and outputs data in units of 8 bits is used as its basic element, and a memory card that performs input and output operations of data in accordance with a clock signal in units of 1 bit, A template register for holding the template data input in 8 bit units;
In this test mode, data output from a flash memory or the like in 8-bit units is compared and collated with template data held by a template register, and a data input / output circuit including a data comparison circuit for outputting the result from one data terminal Provide a circuit. In addition, the input register is also used as the template register,
The data input / output circuit is provided with a data inverting circuit for inverting and writing the write data or template data held by the input register for each bit.

This makes it possible to efficiently generate various kinds of test data that are bit-inverted based on the template data and efficiently input them to the flash memory or the like in 8-bit units.
The test data output in bit units can be compared and collated with the template data in one cycle, and the result can be output in 1 bit units. As a result, it is possible to efficiently generate, write, read, and compare and compare the test data with the flash memory or the like, thereby reducing the test cost of the memory card.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card to which the present invention is applied.

FIG. 2 is an external structural view showing one embodiment of the memory card of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a flash memory included in the memory card of FIG. 1;

FIG. 4 is a block diagram showing one embodiment of a data input / output circuit included in a control unit of the memory card of FIG. 1;

FIG. 5 is a circuit diagram showing one embodiment of an input register and a data inversion circuit included in the data input / output circuit of FIG. 4;

FIG. 6 is a circuit diagram showing one embodiment of an output register and an output buffer included in the data input / output circuit of FIG. 4;

FIG. 7 is a circuit diagram showing one embodiment of a data comparison circuit included in the data input / output circuit of FIG. 4;

FIG. 8 is a signal waveform diagram showing one embodiment of the memory card of FIG. 1 when normal data or template data is input.

FIG. 9 is a signal waveform diagram showing an embodiment at the time of writing template data to the memory of the memory card of FIG. 1;

FIG. 10 is a signal waveform diagram showing one embodiment during a memory read test of the memory card of FIG. 1;

[Explanation of symbols]

MC: Memory card, CN: Connector, C1 to C7
... Connector electrode, CTLU ... Control unit, MCTL ... Memory controller, AC ... Address register counter, MX ... Mux, IO ...
... Data input / output circuit, VG ... Internal voltage generation circuit, FM
EM: Flash memory. CLK ... clock signal or its input terminal (similarly, the name of the signal etc. and its input terminal or output terminal or input / output terminal), CMD ...
… Command or response, DAT …… input / output data,
VDD: power supply voltage, VSS, VSS1 to VSS2 ...
Ground potential, CM command, AD address, DI
…… Input data, DO …… Output data, SC …… Serial clock signal, CEB …… Chip enable signal, W
EB: Write enable signal, OEB: Output enable signal, CDEB: Command data enable signal, RESB: Reset signal, R / BB: Ready busy signal, IO0 to IO7: Input / output data. ICP
1 to ICP2: IC (integrated circuit) package. MAR
Y: memory array, XD: X address decoder, X
B: X address buffer, SRG: sense amplifier register, YG: Y gate circuit, YD: Y address decoder, YC: Y address counter, IB: data input buffer, OB: data output buffer, MXF
... I / O multiplexer, CB... Control buffer, MC... Memory control circuit, VGF... Internal voltage generation circuit. IREG: input register, DINV: data inverting circuit, OREG: output register, OBUF:
Output buffer, DCMP ... Data comparison circuit. UIRE
G0 to UIREG7: Unit input register, UDINV
0 to UDINV7 ... unit data inverting circuit. UOREG
0 to OUREG7 Unit output register, UOBUF0
~ UOBUF7 ... Unit output buffer. V1 to VB ...
Inverters, EXO0 to EXO8... Exclusive OR circuit, OG1... OR gate, B1. T0 to T7: cycle, ID0 to ID7: input data. TDT: non-inverted template data, TDB
... Inversion template data, cy1 to cyr... Cycle, WCM... Write command, SA1 to SA2.
Sector address, SCM... Write start command. RC
M: read command, RD0 to RD7: read data.

Claims (5)

[Claims] 1. A semiconductor memory capable of inputting or outputting data in units of m bits, n data terminals to which data is input or output in units of n bits where m> n, and a predetermined test mode A template register for holding the template data input in units of n bits in units of m bits, and a template for holding data output in units of m bits from the semiconductor memory in the test mode in the template register. Compare the data with the data, and compare the result with the n data terminals or one of them
A memory card, comprising: a data comparison circuit for outputting data from a memory card. 2. The memory card according to claim 1, wherein m is 8, and n is 1. 3. The input device according to claim 1, wherein the memory card holds the write data input in the n-bit unit in the m-bit unit in a normal write mode and transmits the write data to the semiconductor memory. A memory card comprising a register, wherein the input register is also used as the template register. 4. The data according to claim 1, wherein the memory card inverts the template data held by the template register for each bit and transmits the inverted data to the semiconductor memory or the data comparison circuit. A memory card comprising an inversion circuit. 5. The memory card according to claim 1, wherein the semiconductor memory is a flash memory capable of simultaneously erasing data in units of predetermined bits. .