JP2000148120A - Color display circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disturbance of display caused by a change in pallet data and instant improper color display, and execute color change by smooth pallet change, in a color display circuit equipped with a memory for a pallet, for executing color display in finite colors specified by the pallet data written on the memory. SOLUTION: Plural memories for a pallet 24a, 24b are prepared, and at least one 24a of them is made to stand by for rewriting pallet data 37 and is not used as a pallet during the standing time. When a change of the pallet data 37 is necessary, the pallet data 37 are written on the memory 24a, and afterwards the memory 24a is switched for reading out the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a color display circuit having a pallet memory and displaying a finite color defined by pallet data written in the memory.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for more realistic color display, and color expression using 24 bits or more bits for color display has been generally performed. However, in order to increase the number of colors that can be displayed, it is necessary to increase the number of bytes required for each display pixel, and if the resolution is increased by further increasing the number of dots in one screen, the video memory needs to be increased. The memory capacity is significantly increased.

On the other hand, paying attention to the fact that the number of colors displayed simultaneously is limited, color information necessary for each screen is provided as palette data, and color display is performed by referring to the palette data. A pallet type color display circuit that can reduce the memory capacity per dot in a video memory to 1 byte is also used.

[0004]

However, in the conventional color display circuit of the pallet type, when the pallet is changed, display irregularities such as flickering on the screen and unexpected colors are displayed. It is known to

The present inventor has studied such inconveniences and has obtained the following findings. That is, the program to be used is complicated and the resolution is increased, and the data to be processed by one CPU is greatly increased. As a result, all data rewriting in the palette is not completed during one retrace period, and Even if the display is started, the rewriting of the palette is continued. During the data rewriting, the display data is cut off from the pallet, and data irrelevant to the data to be displayed is output from the pallet memory, and is sent to the display device as it is, resulting in an incorrect display.

The present invention has been made on the basis of such knowledge, and is provided with a plurality of pallet memories, and by switching between the memories, the display is disturbed due to the change of the pallets and the instantaneous incorrect color is changed. An object of the present invention is to provide a color display circuit which can eliminate a display and can perform a color change by a smooth palette change.

[0007]

A color display circuit according to the present invention comprises a pallet memory 24 as shown in FIG. 1, and pallet data 37 written in the pallet memory 24.
It performs color display of a finite color defined by.

The present invention further includes a plurality of pallet memories 24a, 24b,... For displaying colors of the display data 22, and in the pallet memory 24, at least one pallet data 37 for writing at least one pallet data 37; At least one color display 24b is set, and the pallet data 37 necessary for display is written in the pallet memory 24a set for writing before the pallet data 37 used for color display is changed. Then, the pallet memory 24a in which the pallet data 37 is written is switched for color display.

The timing of switching from writing to color display in the pallet memory 24 is performed in accordance with the output timing of various synchronization signals such as a vertical synchronization signal, a horizontal synchronization signal, and a dot clock. Can be. It is also possible to use two pallet memories 24 as described above, and to alternately use them for writing pallet data 37 and for displaying colors.

[0010]

As described above, according to the present invention, a plurality of pallet memories 24 are prepared, at least one of which is on standby for rewriting pallet data 37, and is not used as a pallet during the standby. When it is necessary to change the data 37, the pallet data 37 is written into the memory, and then the memory is switched for reading the data. Color display can be eliminated, and color change can be performed by smooth palette change.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example in which a color display circuit according to the present invention is applied to a personal computer application device using a CRT as a display will be described. Of course, the present invention can be carried out in substantially the same manner for general-purpose or special-purpose personal computer devices. In this embodiment, an example has been described in which the main part of the circuit configuration is realized by hardware, but a part of the circuit configuration may be configured by software.

A personal computer application device embodying the present invention has a bus line 1 as schematically shown in FIG.
An image to be displayed on the display 14 is connected to the CPU 12 and the memory 13 via the display unit 1 and is expanded in a bitmap format on the video memory 16 by the image drive circuit 15 and then subjected to necessary data processing. 14 is sent.

The display 14 is of an analog type using a CRT as a display device. The entire display screen 17 is expressed as a set of 480 rows and 640 columns of dots as shown in FIG. As shown in (a), a memory area for all the dots corresponding to the video memory 16 is secured, and the display data 2 that defines the color for each dot is secured.
2 is stored. It is needless to say that the number of display dots can be arbitrarily increased or decreased.

Further, as exemplified in FIGS. 4B and 5, the upper left corner of the display screen 17 is set as the origin, and scanning is performed in the column direction while synchronizing with the dot clock 18 to display an image for one row. One frame is formed by scanning in the row direction while synchronizing with the horizontal synchronizing signal 19, and each frame is displayed while synchronizing with the vertical synchronizing signal 20.

According to the present invention, in the above-described configuration, the drawing processor 21 extracts display data 22 for each dot from the video memory 16 in accordance with a synchronization signal, and further outputs a predetermined color by the color display circuit 10. The configuration for adding information has the feature.

As shown schematically in FIG. 1, the color display circuit 10 converts color data 23 into 24 bits (3 bits).
(Byte), so that color expression corresponding to full color can be performed.
A storage area for color data 23 for 256 colors that can be represented by an 8-bit (1 byte) address is provided above.

On the other hand, the display data 22 for each dot stored in the video memory 16 does not directly specify the color data 23 but stores the address of the pallet memory 24 so that the display data 22 can be specified by the address. The color data 23 to be output is indirectly specified, and the memory capacity and bus width required for the video memory 16 can be reduced to one third.

As specifically shown in FIG. 3, the color display circuit 10 according to the present invention includes first and second sets of color palettes 26 used for color display. The first color palette 24a and the second color palette 24b are switched between writing the palette data 37 and converting the color data 23 in conjunction with the inversion timing of the palette conversion signal 28. Hereinafter, the specific configuration and operation of the color display circuit 10 shown in FIG. 3 will be described in more detail with reference to the waveform diagram of FIG.

The first color pallet 26a and the second color pallet 26b have substantially the same structure, and a pallet memory 24 and a switch for switching between writing the pallet data 37 in the pallet memory 24 and using it for color display. And a unit 29.

When the pallet conversion signal 28 sent from the signal generator 27 is at the "0" level, the first color pallet 26a is put on standby for writing the pallet data 37, and the second color pallet 26b is 2
3, while the pallet conversion signal 28
Is switched to "1", the functions of both are switched instantaneously.

Here, when the reset signal 30 is input to the signal generator 27 at the time of starting the apparatus, the pallet conversion signal 28 is reset to "0" level and further "1" which has passed through the inverter circuit 31. Level inversion signal 32
Together with the first and second color palettes 26a and 26
The operation of b is set in the following predetermined state.

As the pallet memory 24, for example, a general-purpose DRAM is used, and the output permission terminal OE of the second pallet memory 24b is supplied with a pallet conversion signal 2 of "0" level.
By inputting an inverted signal 32 of "1" level to the output permission terminal OE of the first pallet memory 24a while inputting "8" to enable reading of data,
Data output is prohibited and the apparatus is put into a standby state for writing data.

In this state, the second pallet memory 24
The display data 22 as shown in FIG.
Is input, "B2" of the color data 23 specified by the address "b" of the second pallet memory 24 expressed by the display data 22 retrieved from the video memory 16 in response to the synchronization signal is Output from data terminal D. The color data 23 is further selectively taken out by a multiplexer 33, and then converted into an analog video signal 35 by a D / A converter 34.
Sent to

On the other hand, the first pallet memory 24a
In a state where the pallet data 37 is set to the data terminal D and the write address corresponding to the pallet data 37 is set to the address terminal A, the pallet data is written to the write enable terminal WE at time t1 in FIG. When the write signal 36 is applied, the pallet data 37 input to the data terminal D is written to a predetermined area in the first pallet memory 24a specified by the address data 25 input to the address terminal A.

Therefore, in this embodiment, the multiplexer 3 is connected to the input side of the address terminal A of the pallet memory 24.
8 and the address and pallet data 37 included in the display data 22 in conjunction with the inversion of the pallet conversion signal 28.
The address data 25 for writing can be selectively switched.

An analog switch 39 is provided on the input side of the data terminal D in the pallet memory 24, and the pallet data 37 is linked with the inversion of the pallet conversion signal 28.
ON / OFF of the input to the data terminal D is regulated.

Further, a change in the pallet write signal 36 and the pallet conversion signal 28 is detected by the AND circuit 40, and when both are completed, the write enable terminal WE of the pallet memory 24 is set to "L". The data is actually written into the memory 24 for use.

When the writing of the pallet data 37 to the first pallet memory 24a is completed at time t2, the pallet switching signal 41 is output at time t3 to the signal generating unit 2.
7 is input.

The signal generation section 27 detects the input timing of the pallet switching signal 41 with the first flip-flop 42, the conversion timing of the pallet with the second flip-flop 43, and the pallet conversion signal 2 with the third flip-flop 44.
8 is generated.

The first flip-flop 42 is of the D type, and always inputs a "1" signal to the data terminal D.
The pallet switching signal 41 is input to the clock terminal. Therefore, the output signal 46 maintained at the “0” level by the input of the reset signal 30 becomes the time t.
3 in synchronization with the input of the pallet switching signal 41 to the "1" level.

As the second flip-flop 43, a D-type flip-flop is used. The data terminal D of the second flip-flop 43 is connected to one or both of the vertical synchronizing signal 19 and the horizontal synchronizing signal 20 via the AND circuit 45 and the first terminal. Flip-flop 4
2 is input.

Therefore, at the time t3, the output signal 46 of the first flip-flop 42 becomes "1", and at the time t4, the data terminal D of the second flip-flop 43 becomes linked with the synchronizing signal becoming "1". It becomes "1".

Here, the dot clock 18 is configured to be input to the clock terminal of the second flip-flop 43, and the second flip-flop 43 operates in synchronization with the input of one dot clock 18 at time t 5. The output signal 47 of the flip-flop 43 becomes "1" level. At the same time, the inverted output 48 of the second flip-flop 43 is
To the reset terminal R of the first flip-flop 42 to reset the output signal 46 of the first flip-flop 42 to the “0” level.

The third flip-flop 44 is of the JK type, and both the JK terminals are maintained at “1” level.
The output terminal of the second flip-flop 43 is connected to the clock terminal. Accordingly, the pallet conversion signal 28 output from the third flip-flop 44 is also inverted to “1” in conjunction with the output signal 47 of the second flip-flop 43 becoming “1” at the time t5, so that At the same time, the roles of the first pallet memory 24a and the second pallet memory 24b are instantaneously switched.

Thereafter, as shown by the dashed line in FIG. 1, when the same display data 22 is, for example, "b", the color data 23 specified by that data is stored in the second palette memory 24b. "B2" is changed from "B2" to "B1" which is color data on the first palette memory 24a.

At time t5, the output signal 46 of the first flip-flop 42 returns to "0" level, so that the D terminal input of the second flip-flop 43 also becomes "0".
At time t6 when the next dot clock 18 is input, the output signal 47 of the second flip-flop 43 is also “0”.
The series of pallet switching operations ends.

In the above-described embodiment, an example has been described in which the pallet memory 24 is switched in response to the flyback period, which is the time when the horizontal synchronizing signal 19 or the vertical synchronizing signal 20 is generated. However, by constantly applying the “1” signal instead of such a synchronization signal, the color pallet 26 can be displayed at an arbitrary dot clock 18 during image display.
Can be switched.

Further, by increasing the number of the color pallets 26 to three or more and switching them as required, a more varied color display can be easily performed without causing display disturbance.

Although an example has been described in which data processing is performed by providing the processor 21 dedicated to rendering, the general-purpose CPU 12 may be used to perform various data processing operations such as reading and writing data from and to the pallet memory 24. It is possible.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram schematically showing the configuration of the present invention.

FIG. 2 is a block diagram showing an example in which the present invention is applied to a personal computer application device.

FIG. 3 is an electric circuit diagram illustrating an example of a color display circuit.

FIG. 4 is an explanatory diagram showing a relationship between a video memory and a scanning position on a display screen.

FIG. 5 is a waveform chart showing a relationship between a synchronization signal and display data.

FIG. 6 is a waveform chart showing an operation procedure of the color display circuit.

[Explanation of symbols]

 Reference Signs List 10 color display circuit 11 bus line 12 CPU 13 memory 14 display 15 image drive circuit 16 video memory 17 display screen 18 dot clock 19 horizontal synchronization signal 20 vertical synchronization signal 21 drawing processor 22 display data 23 color data 24 pallet memory 25 pallet Memory address data 26 Color pallet 27 Signal generator 28 Palette conversion signal 29 Switching unit 30 Reset signal 31 Inverter circuit 32 Inversion signal 33 Multiplexer 34 D / A converter 35 Video signal 36 Pallet write signal 37 Pallet data 38 Switching unit Multiplexer 39 Analog switch 40 AND circuit of switching unit 41 Palette switching signal 42 First flip-flop 43 Second flip-flop 44 Third flip-flop 45 Signal Output signal 48 inverted output 49 OR circuit from the output signal 47 first 2FF from the AND circuit 46 first 1FF raw portion

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C006 AA21 AF85 BB11 BF01 5C080 AA06 AA10 BB05 CC03 DD06 EE29 EE30 JJ01 JJ02 JJ03 JJ04 5C082 AA01 BA34 BA35 BB15 BB51 CA12 DA71 MM10

Claims (3)

[Claims] A circuit for displaying a finite color defined by palette data written in the palette memory, wherein a plurality of palette memories are provided for displaying color of display data. In the pallet memory, at least one pallet data write and at least one color display are set, and before the pallet data to be used is changed, the pallet memory is set to the pallet memory. A color display circuit characterized in that, after writing palette data necessary for display, the palette memory in which the palette data is written is switched for color display. 2. The color display circuit according to claim 1, wherein the switching from the writing of the pallet memory to the display of the color is performed according to the output timing of the synchronization signal. 3. The color display circuit according to claim 1, wherein there are two palette memories, and both are alternately used for writing palette data and for displaying colors.