JP2000146513A - Laser length-measuring apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a circuit delay time constant regardless of the frequency change of an interference signal, by providing a delay adjusting means which measures the frequency of the interference signal, and changes the delay time of the interference signal by a specified correcting table, etc. SOLUTION: A laser length-measuring apparatus using heterodyne interference is provided with a delay adjusting means 52 composed of a variable delay circuit 11, a frequency measuring circuit 12, and a storage circuit 13. When an interference light 100 is inputted to a photodetector 1, an interference signal 102 is outputted to the delay circuit 11 from a comparator 4, delayed according to a set value outputted to its control terminal from the storage circuit 13, and processed in a circuit in a latter stage as an output signal 104 from the delay circuit 11. The output of the delay circuit 11 is inputted also to the measuring circuit 12, and a frequency measured result is address-inputted to the storage circuit 13. A set value to be inputted to the control terminal of the delay circuit 11 is adjusted, by a correcting table of a specified characteristic stored beforehand in the storage circuit 13 for example.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laser length measuring apparatus using heterodyne interference, and more particularly to a laser length measuring apparatus capable of reducing variation in circuit delay time due to a change in the frequency of an interference signal.

[0002]

2. Description of the Related Art A conventional laser length measuring apparatus using heterodyne interference uses laser beams of two frequencies, and attaches a laser beam of one frequency to a reference mirror and a laser beam of the other frequency to an object to be measured. The light is reflected by the mirrors and interferes.

When the DUT moves, the frequency of the interference light when the DUT moves changes compared to the frequency of the interference light when the DUT stops due to the Doppler effect.

Therefore, by using the frequency of the difference between the two frequencies as a reference signal and detecting the phase difference between this reference signal and the interference light when the device under test moves, the position of the device under test from its initial state is detected. The change, in other words, the position of the measured object can be measured.

FIG. 5 is a block diagram showing an example of such a conventional laser length measuring apparatus. In FIG. 5, 1 is a photodetector using a photodiode or the like, 2 and 5 are amplifiers, 3 and 6 are filter circuits, 4 and 7 are comparators, 8 is a PLL circuit, 9 is a cycle measuring circuit, 10 is an integrating circuit. , 10
Reference numeral 0 denotes an interference light, reference numeral 101 denotes a reference signal obtained by converting the difference between the two frequencies into a voltage signal, reference numeral 102 denotes an interference signal, and reference numeral 103 denotes a clock signal. Also, 1-4 are receivers 50,
5 to 10 constitute the phase measurement circuit 51, respectively.

[0006] The interference light 100 enters the photodetector 1, and the output of the photodetector 1 is connected to the amplifier 2. The output of the amplifier 2 is connected to the comparator 4 via the filter circuit 3, and the output of the comparator 4 is connected to the period measurement circuit 9 as the interference signal 102.

On the other hand, the reference signal 101 is connected to the amplifier 5, and the output of the amplifier 5 is output via the filter circuit 6 to the comparator 7.
Connected to. The output of the comparator 7 is connected to a PLL circuit 8, and the output of the PLL circuit 8 is connected as a clock signal 103 to a period measurement circuit 9. The output of the cycle measuring circuit 9 is connected to the integrating circuit 10.

Here, the operation of the conventional example shown in FIG. 5 will be briefly described. The interference light 100 is converted into an electric signal by the photodetector 1 and then amplified by the amplifier 2 as appropriate. The output of the amplifier 2 is input to the comparator 4 via the filter circuit 3 and output as an interference signal 102 which is a binary digital signal.

Similarly, the reference signal 101 is appropriately amplified by the amplifier 5, and the output of the amplifier 5 is input to the comparator 7 via the filter circuit 6, binarized and converted into a digital signal. Multiplied by the clock signal 10
It is output as 3.

The period measuring circuit 9 counts the period of the interference signal 102 output from the receiver 50 based on the clock signal 103 and, based on the counted value, the reference signal 101.
Is subtracted from the count value corresponding to the period, and a phase difference is obtained and output. Then, the integrating circuit 10 sequentially integrates the phase differences obtained by the period measuring circuit 9.

Since this phase difference means the distance that the device under test moves in one cycle of the reference signal, the relative distance from the initial state of the device under test is calculated by sequentially integrating the moving distances in one cycle. It becomes possible to obtain the position.

As a result, the position of the object to be measured can be obtained by measuring the period of the interference signal 102, obtaining the phase difference from the obtained period, and integrating it.

[0013]

However, in the conventional example shown in FIG. 5, the power "P" of the interference light incident on the photodetector 1 is P = P0 {1 + A.sin2π (f + 2V / λ) T} (1) Here, “P0” is a DC component, “A” is a ratio of an AC component, “f” is a frequency of a difference between two frequencies,
λ ”is the light wavelength (the two frequencies are close and therefore approximated by the same light wavelength), and“ V ”is the moving speed of the measured object.

From equation (1), the frequency of the interference signal 102 is “
f + 2V / λ ”, the frequency of the interference signal 102 changes within the range of“ f ± 2Vmax / λ ”, where the maximum moving speed of the device under test is“ Vmax ”.
For this reason, in order to improve the S / N, the filter circuit 3 preferably uses this frequency range as a pass band, and the attenuation is as large as possible in other frequency ranges.

In order to attenuate noise outside the pass band, for example, a filter having a steep characteristic such as Chebyshev characteristic may be used as the filter circuit 3, but the circuit delay time due to the input frequency in this pass band is large. There was an issue that said it would be different. Therefore, an object of the present invention is to realize a laser length measuring device capable of keeping a circuit delay time constant irrespective of a frequency change of an interference signal.

[0016]

In order to achieve the above object, according to a first aspect of the present invention, a laser length measuring apparatus using heterodyne interference detects an interference light and detects an interference signal. A phase measurement circuit that measures the position of the device under test by detecting and integrating the phase difference between the interference signal and the reference signal, and a delay time of the interference signal based on the frequency of the interference signal. And the delay adjusting means for adjusting the delay time to keep the delay time constant irrespective of the change in the frequency of the interference signal makes it possible to make the circuit delay time constant regardless of the change in the frequency of the interference signal.

According to a second aspect of the present invention, in the laser measuring device according to the first aspect of the present invention, the interference signal is adjusted by adjusting a delay time of the interference signal based on a frequency of an output signal of the delay adjusting means. Circuit delay time can be made constant regardless of the frequency change.

According to a third aspect of the present invention, in the laser measuring apparatus according to the first and second aspects, the delay adjusting means measures the frequency of the interference signal or the output signal of the delay adjusting means. A frequency measuring circuit, an output of the frequency measuring circuit is connected as an address signal, a storage circuit storing the delay time correction table, and the delay time of the interference signal is changed based on an output value from the storage circuit. And a variable delay circuit for changing the circuit delay time based on the frequency of the interference signal.

According to a fourth aspect of the present invention, in the laser length measuring apparatus according to the first and second aspects, the delay adjusting means measures the frequency of the interference signal or the output signal of the delay adjusting means. A frequency measuring circuit to calculate the delay time by a correction formula based on the output of the frequency measuring circuit, and a variable means for changing the delay time of the interference signal based on an output value from the calculating means. With the delay circuit, the circuit delay time can be changed based on the frequency of the interference signal. In addition, the correction operation for correcting the correction time becomes easy.

According to a fifth aspect of the present invention, in the laser measuring device according to the third and fourth aspects, the frequency measuring circuit includes a clock generating means for generating a periodic signal having a constant period, and By being comprised of a signal or a counting means for counting the fixed interval based on an output signal of the delay adjusting means, it becomes possible to measure the frequency of the interference signal.

According to a sixth aspect of the present invention, in the laser measuring device according to the fifth aspect, the counting means includes a counter circuit which is incremented based on the interference signal or the output signal of the delay adjusting means, A latch circuit for latching and outputting the output of the counter circuit;
By including a flip-flop circuit that causes the latch circuit to perform a latch operation in synchronization with the periodic signal and resets the counter circuit, the frequency of the interference signal can be measured.

According to a seventh aspect of the present invention, in the laser measuring apparatus according to the fifth aspect, the clock generating means includes a plurality of cascade-connected flip-flop circuits for dividing a reference clock signal, and An AND circuit that generates the periodic signal having a constant cycle by calculating the logical product of the outputs of the plurality of flip-flop circuits can generate a periodic signal having a constant cycle.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of a laser length measuring apparatus according to the present invention.

In FIG. 1, 1 to 10, 50, 51 and 1
Reference numerals 00 to 103 denote the same reference numerals as in FIG. 5, 11 denotes a variable delay circuit to which a digital signal is input as a control signal, 12 denotes a frequency measurement circuit, 13 denotes a storage circuit, and 104 denotes an output signal. 11 to 13 are delay adjusting means 52
Is composed.

The interference light 100 enters the photodetector 1, and the output of the photodetector 1 is connected to the amplifier 2. An output of the amplifier 2 is connected to a comparator 4 via a filter circuit 3, and an interference signal 102 output from the comparator 4 is connected to a variable delay circuit 11.

The output signal 104, which is the output of the variable delay circuit 11, is connected to the period measuring circuit 9 and to the frequency measuring circuit 12, and the digital output of the frequency measuring circuit 12 is connected to the storage circuit 13. Further, the digital output of the storage circuit 13 is connected to the control terminal of the variable delay circuit 11.

On the other hand, the reference signal 101 is connected to the amplifier 5, and the output of the amplifier 5 is supplied to the comparator 7 via the filter circuit 6.
Connected to. The output of the comparator 7 is connected to the PLL circuit 8, and the clock signal 103, which is the output of the PLL circuit 8, is connected to the period measuring circuit 9. The output of the cycle measuring circuit 9 is connected to the integrating circuit 10.

The operation of the embodiment shown in FIG. 1 will now be described with reference to FIGS. However, description of the same parts as in the conventional example shown in FIG. 5 is omitted. FIG. 2 shows a filter circuit 3
FIG. 3 is a characteristic curve diagram showing an example of the characteristics of the correction table.

The interference signal 102 output from the comparator 4 is delayed by the variable delay circuit 11 according to the set value input to the control terminal and output as an output signal 104.
The output signal 104 of the variable delay circuit 11 is input to the subsequent cycle measuring circuit 9 and processed as described above.

On the other hand, the output of the variable delay circuit 11 is also input to the frequency measurement circuit 12, which measures the frequency of the output signal 104 and outputs the result as an address input to the storage circuit 13. The storage circuit 13 previously stores a correction table for correcting the delay time for the frequency of the output signal 104, in other words, a correction table for the inverse characteristic of the frequency versus the delay time.

For example, as shown in FIG.
In the case where the delay times “τ1” and “τ2” respectively occur in the case of the input signal frequencies “f1” and “f2”, if the delay time of the frequency “f2” is used as a reference, as shown in FIG. When the frequency is “f2”, the delay time by the variable delay circuit 11 is “0”, and when the frequency is “f1”, the delay time by the variable delay circuit 11 is “τ2−τ”.
1 ".

Therefore, if the frequency of the interference signal 102 is "f"
In the case of "2", only the delay time in the filter circuit 3 is accumulated, and the total delay time becomes "τ2".
02 is “f1”, the delay time “τ1” in the filter circuit 3 is replaced by the delay time “τ2” in the variable delay circuit 11.
−τ1 ”is added, so that the total delay time is“ τ1 +
(Τ2−τ1) = τ2 ″, and the delay time can be made constant (τ2) regardless of the frequency of the interference signal 102.

FIG. 4 is a circuit diagram showing a specific example of the frequency measuring circuit 12. As shown in FIG. In FIG. 4, 13 and 102 are denoted by the same reference numerals as in FIG. 1, 14, 21, 22, 23 and 24 are D-type flip-flop circuits (hereinafter simply referred to as flip-flop circuits), 15 is a delay element, 16 and 25 are AND circuits, 17 and 18 are counter circuits, 19
And 20, a latch circuit; and 105, a reference clock signal. 14 to 20 are counting means 53;
Reference numeral 5 denotes each of the clock generating means 54.

The interference signal 102 is output from the flip-flop circuit 1
4 and an input terminal of the delay element 15, and an output of the delay element 15 is connected to a clock input terminal of the counter circuit 17. The carry output of the counter circuit 17 is connected to the clock input terminal of the counter circuit 18.

The negative logic output of the flip-flop circuit 14 is connected to one input terminal of the AND circuit 16 and the clear terminal of the counter circuits 17 and 18, respectively, and the positive logic output of the flip-flop circuit 14 is connected to the latch circuits 19 and 20. Connected to clock input terminal.

Each output terminal of the counter circuit 17 is connected to an input terminal of the latch circuit 19, and each output terminal of the counter circuit 18 is connected to an input terminal of the latch circuit 20, respectively. Further, the output terminals of the latch circuits 19 and 20 are connected to the address input terminals of the storage circuit 13, respectively.

On the other hand, the reference clock signal 105 is connected to the clock input terminal of the flip-flop circuit 21, and the negative logic output of the flip-flop circuit 21 is connected to the input terminal of the flip-flop circuit 21. The positive logic output of the flip-flop circuit 21 is
And the first input terminal of the AND circuit 25.

The negative logic output of the flip-flop circuit 22 is connected to the input terminal of the flip-flop circuit 22, and the positive logic output of the flip-flop circuit 22 is connected to the clock input terminal of the flip-flop circuit 23 and the second input terminal of the AND circuit 25.
Is connected to the input terminal.

Similarly, the negative logic output of the flip-flop circuit 23 is connected to the input terminal of the flip-flop circuit 23, and the positive logic output of the flip-flop circuit 23 is connected to the clock input terminal of the flip-flop circuit 24 and the AND circuit 2.
5 is connected to the third input terminal.

Further, the negative logic output of the flip-flop circuit 24 is connected to the input terminal of the flip-flop circuit 24, and the positive logic output of the flip-flop circuit 24 is connected to the fourth input terminal of the AND circuit 25. Finally, the output of the AND circuit 25 is connected to the input terminal of the flip-flop circuit 14 and the other input terminal of the AND circuit 16.

Here, the operation of the frequency measuring circuit shown in FIG. 4 will be described. The reference clock signal 105 is a four-stage flip-flop circuit 21 to 2
4 to 16 and the flip-flop circuits 21 to 21
The output of the AND circuit 25 changes from "0" to "1" when all of the 24 positive logic outputs become "1". That is,
The counter circuits 17 and 18 are incremented by the interference signal 102 only during a period obtained by dividing the reference clock signal 105 by 16.

When the logical product circuit 25 becomes "1", the positive logic output of the flip-flop circuit 14 becomes "1" in synchronization with the interference signal 102, and the value counted by the counter circuits 17 and 18 becomes the latch circuit 19 and 20, the flip-flop circuit 14 and the counter circuits 17 and 18 are reset, and the latch circuits 19 and 2 are reset.
The value latched at 0 is used as an address input by the storage circuit 13.
Is output to The delay element 15 is an element for adjusting timing.

That is, the counting means 53 outputs the interference signal 1
02 is input to the storage circuit 13 in which a correction table of the inverse characteristic of the frequency versus the delay time is stored as an address input as the address input, so that the correction value for the measured frequency can be changed from the storage circuit 13. The circuit delay time caused by the frequency fluctuation of the interference signal 102 output to the delay circuit 11 (not shown) can be made constant.

As a result, the frequency of the interference signal is measured by the frequency measuring circuit 12 and the delay adjusting means 52 for controlling the delay time of the variable delay circuit 11 by the correction table stored in the storage circuit 13 is provided. It is possible to make the circuit delay time constant irrespective of the signal frequency change.

In order to simplify the description of the operation of the embodiment shown in FIG. 1, simple delay characteristic examples and correction table examples are shown in FIGS. 2 and 3, but actual delay characteristics and correction tables are not shown in FIG. However, the present invention is not limited to the examples of FIGS.

In the embodiment shown in FIG.
, The frequency of the output signal 104 of the variable delay circuit 11 is measured.
The measurement may be performed in step 2.

Further, as the variable delay circuit 11, an element to which a digital signal is input as a control signal is illustrated, but an element to which an analog signal is input as a control signal may be used.

FIG. 4 shows an example of a specific circuit of the counting means 53 and the clock generating means 54.
Of course, it is not limited to these. For example, the counting means 53 is configured by using two 4-bit counter circuits and two 4-bit latch circuits. One counter circuit of 8 bits or more and one latch circuit of 8 bits or more are used.
You may comprise by individual.

In the embodiment shown in FIG.
Although the delay time of the variable delay circuit 11 is determined by the correction table stored in the storage circuit 13, the calculation using the correction formula may be performed using an arithmetic unit such as an arithmetic circuit or a control circuit instead of the storage circuit 13. In this case, highly accurate correction can be performed without using a large correction table. Also,
When the correction time is to be corrected, it is sufficient only to correct the correction formula, so that the correction work is facilitated.

[0050]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first and second aspects of the present invention, by providing the delay adjusting means for measuring the frequency of the interference signal and changing the delay time of the interference signal using the correction table, the circuit delay can be made regardless of the frequency change of the interference signal. It is possible to make the time constant.

According to the third aspect of the present invention, the frequency of the interference signal is measured by the frequency measurement circuit, and the delay time of the variable delay circuit is controlled by the correction table stored in the storage circuit. , The circuit delay time can be changed based on the frequency.

According to the fourth aspect of the present invention, the frequency of the interference signal is measured by the frequency measuring circuit, and the delay time of the variable delay circuit is controlled by the calculating means, and the delay time is calculated by the correction formula based on the frequency. This makes it possible to change the circuit delay time based on the frequency of the interference signal. In addition, the correction operation for correcting the correction time becomes easy.

According to the fifth aspect of the present invention, the frequency of the interference signal is measured by generating a periodic signal having a fixed period by the clock generation means and counting a predetermined interval by the counting means based on the interference signal. Becomes possible.

According to the present invention, the counter circuit is incremented based on the interference signal, the output of the counter circuit is latched by the latch circuit, and the latch operation and the counter circuit are reset by the flip-flop circuit. It is possible to measure the frequency of the interference signal.

According to the invention of claim 7, the clock signal is divided by the plurality of flip-flop circuits connected in cascade, and the logical product of the outputs of the plurality of flip-flop circuits is obtained, so that the period of the constant cycle is obtained. A signal can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a laser length measuring apparatus according to the present invention.

FIG. 2 is a characteristic curve diagram illustrating an example of a delay characteristic of a filter circuit.

FIG. 3 is a characteristic curve diagram showing a characteristic example of a correction table.

FIG. 4 is a circuit diagram showing a specific example of a frequency measurement circuit.

FIG. 5 is a configuration block diagram showing an example of a conventional laser length measuring device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Photodetector 2, 5 Amplifier 3, 6 Filter circuit 4, 7 Comparator 8 PLL circuit 9 Period measurement circuit 10 Integration circuit 11 Variable delay circuit 12 Frequency measurement circuit 13 Storage circuit 14, 21, 22, 23, 24 D type Flip-flop circuit 15 Delay element 16, 25 Logical product circuit 17, 18 Counter circuit 19, 20 Latch circuit 50 Receiver 51 Phase measurement circuit 52 Delay adjustment means 53 Counting means 54 Clock generation means 100 Interference light 101 Reference signal 102 Interference signal 103 Clock Signal 104 Output signal 105 Reference clock signal

Claims (7)

[Claims] 1. A laser length measuring apparatus using heterodyne interference, comprising: a receiver for detecting an interference light and outputting an interference signal; and measuring and measuring a phase difference between the interference signal and a reference signal by integrating them. A phase measuring circuit for measuring a position of an object; and a delay adjusting means for adjusting a delay time of the interference signal based on a frequency of the interference signal to thereby keep the delay time constant regardless of a frequency change of the interference signal. Laser length measuring device characterized by the above-mentioned. 2. The laser length measuring apparatus according to claim 1, wherein a delay time of said interference signal is adjusted based on a frequency of an output signal of said delay adjusting means. 3. A delay measuring circuit for measuring a frequency of the interference signal or an output signal of the delay adjusting unit, an output of the frequency measuring circuit being connected as an address signal, and a correction table for the delay time. 3. The laser according to claim 1, further comprising: a storage circuit in which the delay time of the interference signal is changed based on an output value from the storage circuit. 4. Length measuring device. 4. A frequency measuring circuit for measuring a frequency of the interference signal or an output signal of the delay adjusting means, and the delay time is calculated by a correction formula based on an output of the frequency measuring circuit. 3. The laser length measuring device according to claim 1, further comprising: a calculating means for outputting; and a variable delay circuit for changing the delay time of the interference signal based on an output value from the calculating means. apparatus. 5. The frequency measuring circuit comprises: clock generating means for generating a periodic signal having a constant cycle; and counting means for counting the constant interval based on the interference signal or the output signal of the delay adjusting means. 5. The laser length measuring device according to claim 3, wherein: 6. A counter circuit, wherein said counting means is incremented based on said interference signal or an output signal of said delay adjusting means, a latch circuit for latching and outputting an output of said counter circuit, and synchronizing with said periodic signal. 6. The laser length measuring apparatus according to claim 5, further comprising a flip-flop circuit for causing the latch circuit to perform a latch operation and resetting the counter circuit. 7. The periodic signal having a constant period by taking a logical product of a plurality of cascade-connected flip-flop circuits for dividing a reference clock signal and an output of the plurality of flip-flop circuits. 6. A laser length measuring apparatus according to claim 5, further comprising: a logical product circuit for generating the following.