JP2000138686A - Control path band warrant system in high speed router - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed transfer by reserving a path for a control flow so as to maintain a cut-through path even in the case of excess traffic. SOLUTION: An output side of an asynchronous transfer mode ATM switch section 20 of a high speed router discriminates packets being output objects in the unit of virtual channel VC, a control packet is stored in a priority buffer 21a so as to give priority to a control path through which the control packet passes according to the discrimination result and outputted with priority thereby reserving a communication band of the control path. Thus, even on the occurrence of excess traffic, lack of communication of the control packet is avoided so as to maintain a cut-through path and to attain high speed transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an IETF (Intern
RFC (Request For Comments) at the al Engineering Task Force: Internet Special Technical Investigation Committee
The present invention relates to a control method for guaranteeing a communication band of a control packet for performing high-speed transfer in a high-speed router shown in 2129.

[0002]

2. Description of the Related Art With the spread of the Internet in recent years, the Internet infrastructure has been steadily expanding. An important technology here is a device that connects a plurality of logical networks. In a packet relay device such as a bridge or a router, routing processing for each packet destination is performed in the data link layer for communication on the same subnet (logical network) and in the network layer for communication between different subnets (logical networks). To transfer.
The transfer of a packet by such a routing process in the network layer is called hop-by-hop transfer.

[0003] In this hop-by-hop transfer method, IP
Extraction of the header information of the next, then the destination to send the IP and (next
HOP) is determined by software processing (CPU). Therefore, the processing speed in this part becomes slow,
In recent years, with the speeding up and increase of communication traffic, in a network via a plurality of devices, this point has become a bottleneck, and the throughput cannot be increased.

Therefore, the processing of the data link layer of the IP packet is omitted, and the ATM (As
Asynchronous Transfer Mode: A label switch switch type router (cell switch router: CSR) that realizes high-speed IP forwarding processing by switch exchange has been proposed.

In this label switch system, communication such as ftp or http having a relatively long session time, or cutoff transfer of IP packet data to a network belonging to the same network using a network address as an information base (Layer 1 level (ATM)) This is effective in improving the throughput, and the processing speed can be remarkably increased as compared with the conventional method.

A high-speed router using such a label switch system includes an IP processing device (also called a controller) at a stage subsequent to the ATM switch, and sets a path for cut-through transfer to the ATM switch by the IP processing device. , High-speed transfer at the layer 1 level is realized.

By the way, in this kind of high-speed router,
Conventionally, packets on a control path for performing high-speed transfer and packets on a data transfer path have been transferred without distinction. Further, in the IP processing device (also referred to as a controller), a control packet and a data packet sent from the ATM switch unit are stored in the memory for managing the traffic (communication amount) of the packet without distinction. .

[0008]

As described above, in the conventional high-speed router, since the control packet and the data packet are sequentially transferred without discrimination, the transfer amount of the data packet is limited by the communication bandwidth. When the number exceeds the limit, there is a problem that the control packet is interrupted and the cut-through path cannot be maintained.

In addition, since the control packet and the data packet are stored in the memory in the controller without distinction, when the data packet increases, the memory is occupied by the data packet and the control packet can be secured. There is a problem that the cut-through path cannot be maintained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a high-speed router that secures a path for a control flow and maintains a cut-through path to enable high-speed transfer even during excessive traffic. An object of the present invention is to provide a control path bandwidth guarantee method.

[0011]

A first method of the present invention is as follows.
At the output side of the ATM switch, the packet to be output is determined in VC units, and the control packet is stored in a priority buffer according to the determination result so that the control path through which the control packet passes has priority. In this way, the communication band of the control path is ensured by outputting the data in a controlled manner.

According to a second method of the present invention, an ATM cell transferred from an ATM switch to a controller is assembled into an IP packet, and a control packet or a data packet is determined based on the IP packet. By discriminating and discriminating between the control packet and the data packet in the packet processing memory according to the discrimination result, the communication band of the control path through which the control packet passes is secured.

By using the first and second schemes alone or in combination, it is possible to cause a control packet for performing cut-through transfer to reach the controller without loss. As a result, even during traffic congestion, it is possible to secure the communication band of the control path and control the generation / disconnection of the cut-through path.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining a cut-through method in a high-speed router according to one embodiment of the present invention. The high-speed router of the present invention is a label switch type relay device using an ATM switch,
It comprises a controller unit 10 for performing cut-through control and the like and an ATM switch unit 20 for performing packet transfer. This high-speed router is a cell switch router (CSR)
And is shown in RFC2129 in IETF.

The ATM switch unit 20 has a 53-byte A
Exchange is performed on the basis of a packet called a TM cell.
A 53-byte ATM cell includes a 5-byte header (also called a label) and 48-byte information (user information).

In the header of the ATM cell, control information such as a destination and routing information are set. That is, several virtual paths (VPs) are set in the ATM network, and several virtual channels (VCs) for actually transmitting data are set for each virtual path. For this reason, first, in order to identify which VP is used, a VPI (Virtual Pa
th Identifier: virtual path identifier). Further, in order to identify which VC in the VP should be used to send data to the other party, a VCI is added to the header of the cell.
(Virtual Channel Identifier)
Is provided. The VPI / VCI is a part for determining which VP and which VC to select and communicate with the other party, and is therefore called a routing bit (bit for selecting a communication path).

The ATM cell input to the input terminal of the ATM switch 20 is distributed to the output terminal for each destination (VPI / VCI). At that time, hop-by-hop transfer or
If the cut-through transfer is not determined, each ATM cell is sent to the controller unit 10 to assemble it into an IP packet. That is, since it is not possible to determine the type of data used for the application and the data length and the like by looking at only one cell, the controller unit 10 can process the data by collecting the cells in packet units. To

FIG. 1A shows this state.

In a CSR system as shown in FIG. 1 (a), when a plurality of ATM cells arrive from an upstream edge router at a core router corresponding to the high-speed router of the present invention, these ATM cells are first converted to an ATM switch. Part 2
0 to the controller unit 10.

The ATM cells input to the controller 10 are sent to the cell disassembly / assembly unit (SA) in the controller 10.
R: Segmentation and Reassembly Sublayer) 11 at I
Assembled into P packets. The controller unit 10 composed of a microcomputer or a dedicated LSI
The header information is extracted from the P packet, and the destination IP address and the like are broken. Next, the forwarding table 12 is searched using the analyzed destination IP address as a key.

In the forwarding table 12,
Output line information is registered in advance in association with the destination IP address, and the output line to which the IP subnetwork or the host as the transfer destination is connected is determined according to the search result using the destination IP address as a key. The I
After the P packet is decomposed into ATM cells by the cell disassembly / assembly unit 11, a VC value corresponding to a target output line is newly added to the header portion thereof, and is again output to the output line via the ATM switch unit 20. Sent out.

Here, as shown in FIG. 1B, for example, when a cut-through trigger is detected in the upstream edge router, a cut-through path is generated in the controller unit 10. When a cut-through path is generated,
As shown in FIG. 1C, the data packet (ATM cell) having the same destination as that of the trigger is cut-through-transferred without passing through the controller unit 10, and includes another control packet including a control packet for performing cut-through control. Packets are forwarded non-cut through.

When a cut-through path is generated, FIG.
As shown in the figure, a VC performing cut-through transfer (this is
A dedicated VC) and a VC that performs non-cut-through transfer (this is referred to as a Default VC) are present at the same time. Will be entered. Therefore, when the input / output of the ATM switch unit 20 becomes congested due to the overload transfer of the user data in the traffic of the physical line (ATM 155M), the control packet for maintaining the cut-through path cannot reach the controller unit 10. Occurs.

In FIG. 2, reference numeral 13 denotes a CPU for controlling the controller unit 10, and reference numeral 14 denotes an ATM switch unit 2.
This is a packet processing memory for temporarily storing packets sent from 0.

(First Method) In order to avoid such a situation, the first method is to use Def of the control path.
The ult VC is defined as a priority class, and the Dedicated VC of the cut-through path is defined as a non-priority class.

That is, as shown in FIG. 3, the output buffer 21 provided at the output end of the ATM switch unit 20 is divided into a priority buffer 21a and a non-priority buffer 21b, and a packet to be output is determined on a VC basis. Then De
The control packet passing through the fault VC is transferred to the priority buffer 2
1a, the data packets passing through the Dedicated VC are stored in the non-priority buffer 21b, and the control packets stored in the priority buffer 21a are output with priority.

FIG. 4 shows a specific configuration.

FIG. 4 shows an AT to which the first method of the present invention is applied.
FIG. 3 is a diagram showing an internal configuration of an M switch unit 20. ATM cells (packets) input from two input ports now
Is a usage parameter control unit of the ATM switch unit 20
(UPC: Usage Parameter Control) 22, a routing process is performed by a header converter (HCV: Header Converter) 23, and switching to the same output port is performed by a self-routing switch 24.

The usage parameter control unit 22 monitors the cell flow rate for each connection. The header conversion unit 23
The VCI value added to the header of the input cell is converted to the VCI value of the output destination. Self-routing switch 2
4 routes the cell to an output destination based on the header information of the cell. The cells routed by the self-routing switch 24 are temporarily stored in the output buffer 21 and then output to the output port.

As shown in FIG. 3, the output buffer 21
Is provided with a priority buffer 21a and a non-priority buffer 21b, which are input from the two input ports,
Each cell (packet) routed to the same output port by the self-routing switch 24 is stored in one of the cells by the priority control unit 25. Whether to store in the priority buffer 21a or the non-priority buffer 21b is determined by CLP (Ce
ll Loss Priority (cell loss priority display) flag.

FIG. 5 shows the format of the cell header.
The ATM cell is composed of 53 bytes of data, of which 5 bytes are used as a header and the remaining 48 bytes are used as user information. The 5-byte header contains V
In addition to communication path identification information such as PI / VCI,
A CLP flag is provided. This CLP flag is 1
Bit "0" indicates priority and "1" indicates non-priority.

Here, Def for transferring the control packet
ult VC is set with CLP = 0 (priority), and Dedicated VC that transfers data packets is CLP
= 1 (non-priority). Then, as shown in FIG. 3, the output buffer 21 stores the control packet in the priority buffer 21a and outputs the control packet preferentially so that the Default VC through which the control packet passes is prioritized.
FIG. 6 shows the processing flow.

FIG. 6 is a flowchart showing the operation of the packet priority control process in the ATM switch unit 20.

At the output terminal of the ATM switch unit 20,
When storing the output target ATM cell (packet) in the output buffer 21 (step A11), the priority control unit 25 checks the CLP flag added to the header of the cell (step A12).

As a result, if the CLP flag is “0” (Yes in step A12), the priority control unit 25 determines that the cell is a priority cell (control packet),
The priority buffer 21 provided in the output buffer 21
is stored in a (step A13). Then, the priority control unit 25 sequentially reads out the priority cells stored in the priority buffer 21a in the order of storage and outputs them to the outside (step A14).

On the other hand, if the CLP flag is "1" (No in step A12), the priority control unit 25 determines that the cell is a non-priority cell (data packet),
This is transferred to the non-priority buffer 2 provided in the output buffer 21.
1b (step A15). Here, the non-priority cells stored in the non-priority buffer 21b are sequentially read out when no priority cells are stored in the priority buffer 21a, and otherwise, the reading of the priority cells ends. Waiting for processing until

That is, the priority control unit 25 checks the state of the priority buffer 21a and confirms that there is no priority cell in the priority buffer 21a (Yes in step A16).
s) The non-priority cells stored in the non-priority buffer 21b are sequentially read out in the storage order and output to the outside (step A14). If there is a priority cell in the priority buffer 21a (No in step A16), the priority control unit 25 waits for the output of the non-priority cell until the reading of the priority cell ends (step A17).

By such priority control processing, Defu
A priority is generated between the lt VC packet and the Dedicated VC packet, and the control packet passing through the Default VC is output with priority. As a result, even if the traffic of the output port becomes congested, D
It is possible to guarantee the transfer of the control packet through the default VC.

(Second Method) By the way, when a cut-through is generated, a data packet which is not to be controlled by the cut-through is also transferred to the controller unit 10 via the Default VC. In the conventional method, when a control packet and a data packet are received by the controller unit 10, these packets are stored in the packet processing memory 14 without discrimination as shown in FIG. For this reason, if the traffic of the data packet increases significantly, the controller unit 10 consumes the memory area for the data packet, and a state occurs in which the memory area for receiving the control packet cannot be secured.

Therefore, in order to avoid this state, the second
As shown in FIG. 8, the memory area of the packet processing memory 14 is divided into a control memory area for processing a control packet and a memory area for processing a data packet. Is determined by the state of the IP packet.
By processing the control packet and the data packet separately, a memory area for the control packet is secured.

FIG. 9 shows a specific configuration.

FIG. 9 is a diagram showing the internal configuration of the controller unit 10 to which the second system of the present invention is applied. The controller 13 includes a CPU 13 and a packet processing memory 1.
4. A discrimination memory 15 in which a discrimination program described later is stored, and an ATM interface 16 are provided.

The CPU 13 controls the controller unit 10. Here, the type of the IP packet is determined by activating a packet determination program, and the packet is used for controlling the packet processing memory 14 according to the determination result. A process for selectively storing data in the memory 14a or the data memory 14b is performed. Packet processing memory 14
Is constituted by a RAM, and the addresses a1 to an of the memory area are stored in the control memory 14a, the address an + 1.
To am are preset as the data memory 14b.

The discrimination memory 15 is composed of a RAM, and stores a discrimination program used for discriminating the type of a packet. The CPU 13 determines the type of the packet according to the determination program.

The ATM interface 16 performs packet input / output processing with the ATM switch unit 20. This A
The TM interface 16 includes a cell disassembly / assembly unit (SAR) 1 for assembling an IP packet from an ATM cell.
1 is provided.

Next, the packet processing operation of the controller unit 10 configured as described above will be described.

FIG. 10 is a flowchart showing the packet processing operation in the controller unit 10.

When an ATM cell is sent from the ATM switch section 20 to the controller section 10 via the ATM interface 16 (step B11), a cell disassembly / assembly section (SAR) 1 provided in the ATM interface 16 is provided.
1 assembles an ATM cell into an IP packet (step B12). When an IP packet is assembled in the cell disassembly / assembly unit (SAR) 11,
The CPU 14 temporarily stores the IP packet in the determination memory 15 in order to determine whether the IP packet is a control packet or a data packet.

The CPU 14 analyzes the data content of the IP packet using the discriminating program stored in the discriminating memory 15 to determine whether the IP packet is a control packet or a data packet. It is determined whether there is (Step B13).

If the result of the determination is that the packet is a control packet, the CPU 14 stores the IP packet in an area (a1 to an) of the control memory 14a set in the packet processing memory 14 and processes the IP packet (step S1). B14).
On the other hand, when the packet is a data packet, the CPU 14 sets the data memory 1 set in the packet processing memory 14.
The IP packet is stored in the area 4b (an + 1 to am) and processed (step B15).

As described above, in the controller unit 10,
By discriminating the type of the IP packet and distinguishing the control packet from the data packet and storing them in the packet processing memory 14, even if the traffic of the data packet is greatly increased, the memory area for the control packet is secured. Thus, control such as generation or disconnection of a cut-through path based on the control packet can be performed normally.

The control memory 14a in the packet processing memory 14 is set in advance in accordance with the amount of control packets at the peak, and if the packet transfer is normally performed, the control memory 14a The control packets stored in the control packet 14a are sequentially read out and output to the outside via the ATM switch unit 20, so that the control packet does not fill the control memory 14a.

As described above, by realizing the first method, the second method, or the two methods, a cut-through control packet can reach the controller unit 10 without loss. . As a result, even during traffic congestion, it is possible to secure the communication band of the control path and control the generation / disconnection of the cut-through path.

[0055]

As described above in detail, according to the present invention, A
At the output side of the TM switch, a packet to be output is determined in VC units, and the control packet is stored in a priority buffer according to the determination result so that a control path through which the control packet passes is prioritized. Output
Alternatively, an ATM cell transferred from the ATM switch to the controller is assembled into an IP packet, and it is determined whether the packet is a control packet or a data packet based on the IP packet. The control packet is stored in the packet processing memory separately from the data packet to secure the communication band of the control path through which the control packet passes, so that the control packet may be disconnected even during excessive traffic. Thus, a cut-through path can be maintained and high-speed transfer can be performed.

[Brief description of the drawings]

FIG. 1 is an exemplary view for explaining a cut-through method in a high-speed router according to an embodiment of the present invention.

FIG. 2 illustrates a VC (Dedicat) that performs cut-through transfer.
ed VC) and a VC that performs non-cut-through transfer (Def
FIG. 7 is a diagram for explaining an “ult VC”.

FIG. 3 is a diagram for explaining priority control in the first method of the present invention.

FIG. 4 is a diagram showing an internal configuration of an ATM switch unit to which the first system of the present invention is applied.

FIG. 5 is a diagram showing a format of a cell header.

FIG. 6 is a flowchart showing an operation of a packet priority control process in the ATM switch unit to which the first method of the present invention is applied.

FIG. 7 is a diagram showing a configuration of a packet processing memory of a controller unit according to a conventional method.

FIG. 8 is a diagram showing a configuration of a packet processing memory of a controller unit according to a second system of the present invention.

FIG. 9 is a diagram showing an internal configuration of a controller unit to which the second system of the present invention is applied.

FIG. 10 is a flowchart showing a packet processing operation in a controller unit to which the second method of the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Controller part 20 ... ATM switch part 11 ... Cell disassembly / assembly part (SAR) 12 ... Forwarding table 13 ... CPU 14 ... Packet processing memory 14a ... Control memory 14b ... Data memory 15 ... Determination memory 16 ... ATM interface DESCRIPTION OF SYMBOLS 21 ... Output buffer 21a ... Priority buffer 21b ... Non-priority buffer 22 ... Usage parameter control part (UPC) 23 ... Header conversion part (HCV) 24 ... Self-routing switch 25 ... Priority control part

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hirokazu Yasuda 3-1-1, Asahigaoka, Hino-shi, Tokyo F-term (reference) in Toshiba Communication Systems Engineering Co., Ltd. 5K030 GA03 GA13 HA10 HD03 KA01 KA02 LC11 LE05 9A001 JJ18 JJ25 JJ28

Claims (3)

[Claims] 1. A control path bandwidth guarantee method used for a high-speed router comprising an ATM switch and a controller, wherein an output side of the ATM switch determines a packet to be output on a VC basis, and according to a result of the determination. Storing the control packet in a priority buffer and outputting the control packet preferentially so as to give priority to the control path through which the control packet passes, thereby securing the communication band of the control path. Control path bandwidth guarantee method. 2. A control path bandwidth guarantee method used for a high-speed router comprising an ATM switch and a controller, wherein the ATM cell transferred from the ATM switch to the controller is assembled into an IP packet to determine whether the packet is a control packet. It is determined whether the packet is a data packet, and the control packet and the data packet are stored in the packet processing memory in accordance with the result of the determination to secure a communication band of a control path through which the control packet passes. A control path bandwidth guarantee method characterized by the following. 3. A control path bandwidth guarantee method used in a high-speed router including an ATM switch and a controller, wherein an output side of the ATM switch determines a packet to be output on a VC basis, and according to the determination result. The control packet is stored in a priority buffer and output with priority so as to give priority to the control path through which the control packet passes, and the ATM cells transferred from the ATM switch to the controller are assembled into IP packets. The control packet and the data packet are discriminated according to the discrimination result, and the control packet and the data packet are discriminated and stored in the packet processing memory. A control path band guarantee method characterized by securing a communication band of