JP2000138342A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000138342A JP2000138342A JP10310981A JP31098198A JP2000138342A JP 2000138342 A JP2000138342 A JP 2000138342A JP 10310981 A JP10310981 A JP 10310981A JP 31098198 A JP31098198 A JP 31098198A JP 2000138342 A JP2000138342 A JP 2000138342A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- chip
- semiconductor device
- power
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
- H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に、モールド樹脂によって封止された所定のチップの
電気的特性を容易に測定することが可能な半導体装置に
関するものである。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of easily measuring electrical characteristics of a predetermined chip sealed with a mold resin.
【０００２】[0002]
【従来の技術】従来の半導体装置の一例として、たとえ
ばエアコン、洗濯機などのインバータ用のスイッチング
素子として用いられる電力半導体装置について説明す
る。電力半導体装置では、大電流をスイッチングするた
めの絶縁ゲート形バイポーラトランジスタ（Insulated
Gate Bipolar Transistor 、以下「ＩＧＢＴ」と記
す。）やフライホイールダイオード（Fly Wheel Diode
、以下「 ＦＷＤ」と記す。）といったパワーチップ
と、そのパワーチップを制御するための低電圧集積回路
（Low Voltage Integrated Circuit、以下「ＬＶＩＣ」
と記す。）や高電圧集積回路（High Voltage Integrate
d Circuit 、以下「ＨＶＩＣ」と記す。）といった集積
回路チップが搭載されている。電力半導体装置は、これ
らのパワーチップおよび集積回路チップをリードフレー
ム上に搭載し、所定のワイヤボンドおよび樹脂モールド
工程を経ることによって形成される。2. Description of the Related Art As an example of a conventional semiconductor device, a power semiconductor device used as a switching element for an inverter in, for example, an air conditioner or a washing machine will be described. In power semiconductor devices, insulated gate bipolar transistors (Insulated) for switching large currents
Gate Bipolar Transistor, hereinafter referred to as "IGBT". ) And Fly Wheel Diode
Hereafter, it is described as “FWD”. ) And a low voltage integrated circuit (hereinafter referred to as “LVIC”) for controlling the power chip.
It is written. ) And high voltage integrated circuits (High Voltage Integrate)
d Circuit, hereinafter referred to as “HVIC”. ) Is mounted. The power semiconductor device is formed by mounting the power chip and the integrated circuit chip on a lead frame and performing a predetermined wire bonding and resin molding process.
【０００３】そこで、電力半導体装置の従来の製造方法
について図を用いて説明する。図９および図１０を参照
して、リードフレーム１０２およびパワーチップ１０４
および集積回路チップ１０６をそれぞれダイボンドによ
り搭載する。次に、ワイヤボンディングによってパワー
チップ１０４とリードフレーム１０２内の所定の内部リ
ードとをアルミニウム線１１０により電気的に接続す
る。同様に、集積回路チップ１０６と所定の内部リード
とを金線１０８により電気的に接続する。A conventional method for manufacturing a power semiconductor device will be described with reference to the drawings. 9 and 10, lead frame 102 and power chip 104
And the integrated circuit chip 106 are mounted by die bonding. Next, the power chip 104 and predetermined internal leads in the lead frame 102 are electrically connected by aluminum wires 110 by wire bonding. Similarly, the integrated circuit chip 106 and predetermined internal leads are electrically connected by the gold wire 108.
【０００４】次に図１１および図１２を参照して、パワ
ーチップ１０４および集積回路チップ１０６が搭載され
たリードフレーム１０２の面を覆うように、１次モール
ド樹脂１１２を形成する。このとき、パワーチップ１０
４および集積回路チップ１０６が搭載された面と反対側
のリードフレーム１０２の面は露出した状態にある。Referring to FIGS. 11 and 12, a primary molding resin 112 is formed so as to cover the surface of lead frame 102 on which power chip 104 and integrated circuit chip 106 are mounted. At this time, the power chip 10
4 and the surface of the lead frame 102 opposite to the surface on which the integrated circuit chip 106 is mounted is exposed.
【０００５】次に図１３および図１４を参照して、１次
モールド樹脂１１２から突出している内部リードのう
ち、不要なリード端子となるリード部分（斜線部分）を
カットする。次に図１５および図１６を参照して、１次
モールド樹脂１１２およびリードフレーム１０２を覆う
ように、さらに２次モールド樹脂１１４を形成する。こ
のとき、特にパワーチップ１０４から発生する熱を放出
するためのヒートシンク１１６が配設される。[0005] Next, referring to FIGS. 13 and 14, of internal leads protruding from the primary mold resin 112, a lead portion (hatched portion) serving as an unnecessary lead terminal is cut. Next, referring to FIGS. 15 and 16, a secondary mold resin 114 is further formed so as to cover primary mold resin 112 and lead frame 102. At this time, in particular, a heat sink 116 for releasing heat generated from the power chip 104 is provided.
【０００６】その後、リードフレーム１０２のタイバー
１０２ｇなどをカットして各リード端子を曲げることに
より、図１７（ａ）、（ｂ）および（ｃ）に示す電力半
導体装置が完成する。この電力半導体装置の回路ブロッ
ク図の一例を図１８に示す。回路ブロック図の周囲に示
された各端子は、図１７における各リード端子と対応し
ている。Thereafter, the power semiconductor device shown in FIGS. 17A, 17B and 17C is completed by cutting the tie bars 102g of the lead frame 102 and bending each lead terminal. FIG. 18 shows an example of a circuit block diagram of this power semiconductor device. Each terminal shown around the circuit block diagram corresponds to each lead terminal in FIG.
【０００７】[0007]
【発明が解決しようとする課題】上述した製造方法によ
って得られた電力半導体装置では、１回目のモールド工
程の後、不要なリード部分 (斜線部分) がカットされ
て、そのカットされたリード端部１０２ｈは、２回目の
モールド工程によってモールド樹脂１１４中に封止され
る。このリード端部１０２ｈの中には、パワーチップ１
０４と集積回路チップ１０６とを電気的に接続するため
に、アルミニウム線１１０と金線１０８とを中継する中
継リードの端部も含まれている。In the power semiconductor device obtained by the above-described manufacturing method, an unnecessary lead portion (shaded portion) is cut after the first molding step, and the cut end of the lead is cut off. 102h is sealed in the mold resin 114 by the second molding step. In the lead end 102h, the power chip 1
In order to electrically connect the integrated circuit chip 04 and the integrated circuit chip 106, an end of a relay lead for relaying the aluminum wire 110 and the gold wire 108 is also included.
【０００８】この中継リードは、たとえば図１８に示す
Ａ〜Ｆ点に対応している。すなわち、中継リードはパワ
ーチップ１０４のＩＧＢＴのゲートと集積回路チップ１
０６のＨＶＩＣまたはＬＶＩＣの出力端子とを電気的に
接続する中継部分に対応している。The relay leads correspond to, for example, points A to F shown in FIG. That is, the relay lead is connected to the gate of the IGBT of the power chip 104 and the integrated circuit chip 1
06 corresponds to a relay portion for electrically connecting the output terminal of the HVIC or LVIC.
【０００９】完成した電力半導体装置では、これらの中
継リードは２次モールド樹脂１１４中に封止されている
ため、ＩＧＢＴのゲート電圧やＨＶＩＣまたはＬＶＩＣ
の出力信号（電圧）を直接測定することができなかっ
た。In the completed power semiconductor device, since these relay leads are sealed in the secondary molding resin 114, the gate voltage of the IGBT, the HVIC or the LVIC
Could not be directly measured.
【００１０】本発明は上記問題点を解決するためになさ
れたものであり、パワーチップや集積回路チップの特定
部分の電圧を容易に測定することができる半導体装置を
提供することを目的とする。The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of easily measuring the voltage of a specific portion of a power chip or an integrated circuit chip.
【００１１】[0011]
【課題を解決するための手段】本発明の１つの局面にお
ける半導体装置は、電力用チップおよびその電力用チッ
プを制御するための集積回路チップと、リードフレーム
部と、モールド樹脂とを備えている。リードフレーム部
は、電力用チップを搭載するための第１フレーム部と集
積回路チップを搭載するための第２フレーム部とを有し
ている。モールド樹脂は、電力用チップおよび集積回路
チップを含むリードフレーム部を封止している。そのリ
ードフレーム部は、電力用チップとは第１の金属線によ
って電気的に接続され、集積回路チップとは第２の金属
線によって電気的に接続される中継リード部を有してい
る。そして、その中継リード部の端部がモールド樹脂よ
り突出している。According to one aspect of the present invention, a semiconductor device includes a power chip, an integrated circuit chip for controlling the power chip, a lead frame portion, and a molding resin. . The lead frame section has a first frame section for mounting a power chip and a second frame section for mounting an integrated circuit chip. The mold resin seals the lead frame portion including the power chip and the integrated circuit chip. The lead frame has a relay lead electrically connected to the power chip by a first metal wire and electrically connected to the integrated circuit chip by a second metal wire. Then, the end of the relay lead portion protrudes from the mold resin.
【００１２】この構成によれば、電力用チップと集積回
路チップとは、中継リード部を介して第１の金属線およ
び第２の金属線により電気的に直接接続されている。そ
の中継リード部の端部がモールド樹脂より突出してい
る。その結果、第１の金属配線が接続されている電力用
チップの特定の端子または第２の金属線が接続されてい
る集積回路チップの特定の端子の出力信号（電圧）を容
易に測定することができる。According to this configuration, the power chip and the integrated circuit chip are electrically directly connected to each other by the first metal line and the second metal line via the relay lead. The ends of the relay leads protrude from the mold resin. As a result, it is possible to easily measure an output signal (voltage) of a specific terminal of the power chip to which the first metal wiring is connected or a specific terminal of the integrated circuit chip to which the second metal line is connected. Can be.
【００１３】好ましくは、モールド樹脂は１回のモール
ド工程によって形成されている。モールド樹脂を形成す
る際のモールド工程では、リードフレーム部の不要なリ
ード部分はモールド工程の後にカットされるため、モー
ルド樹脂から中継リード部の端部が必ず突出する。これ
により、電力用チップまたは集積回路チップの特定の出
力信号（電圧）を容易に測定することができるととも
に、モールド工程数の削減も図ることができる。Preferably, the molding resin is formed by one molding step. In the molding process when forming the molding resin, unnecessary lead portions of the lead frame portion are cut after the molding process, so that the end of the relay lead portion always projects from the molding resin. Thus, a specific output signal (voltage) of the power chip or the integrated circuit chip can be easily measured, and the number of molding steps can be reduced.
【００１４】また好ましくは、中継リード部はモールド
樹脂内を最短距離でモールド樹脂の外側へ向かって延び
ている。[0014] Preferably, the relay lead portion extends to the outside of the mold resin at the shortest distance in the mold resin.
【００１５】この場合には、中継リード部の撓みが少な
くなり、製造工程において第１の金属線や第２の金属線
が中継リード部から外れてしまうような不具合を防止す
ることができる。In this case, the bending of the relay lead portion is reduced, and it is possible to prevent a problem that the first metal wire and the second metal wire are detached from the relay lead portion in the manufacturing process.
【００１６】さらに好ましくは、第１の金属線は第２の
金属線よりも多くの電力を流すことを許容する。More preferably, the first metal line allows more power to flow than the second metal line.
【００１７】電力用チップでは、集積回路チップと比較
して大電流を扱う必要がある。このため、第１の金属線
は第２の金属線よりも大電流を流すことができるものが
望ましい。Power chips need to handle large currents compared to integrated circuit chips. For this reason, it is desirable that the first metal wire can flow a larger current than the second metal wire.
【００１８】[0018]
【発明の実施の形態】本発明の実施の形態に係る電力半
導体装置について説明する。まず、電力半導体装置の平
面外観を図１に示し、側面外観を図２および図３にそれ
ぞれ示す。電力半導体装置は、従来の技術に項において
説明したように、大電流をスイッチングするためのＩＧ
ＢＴやＦＷＤといったパワーチップと、そのパワーチッ
プを制御するためのＬＶＩＣやＨＶＩＣといった集積回
路チップがリードフレーム上に搭載され、モールド樹脂
１２によって封止されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS A power semiconductor device according to an embodiment of the present invention will be described. First, a plan view of the power semiconductor device is shown in FIG. 1, and side views are shown in FIGS. 2 and 3, respectively. As described in the section of the related art, the power semiconductor device is an IG for switching a large current.
A power chip such as BT or FWD and an integrated circuit chip such as LVIC or HVIC for controlling the power chip are mounted on a lead frame and sealed with a mold resin 12.
【００１９】そのモールド樹脂１２内の平面構造を図４
に示す。図１〜図４を参照して、モールド樹脂１２から
は、パワーチップ４と接続されたパワーチップ側リード
端子２ｂと集積回路チップ６と接続された集積回路チッ
プ側リード端子２ｄとが突出して配設されている。さら
に、モールド樹脂１２からは、パワーチップ４とはアル
ミニウム線１０によって電気的に接続され、集積回路チ
ップとは金線８によって電気的に接続されている中継リ
ード３ａ〜３ｆの端部が突出している。パワーチップ４
と集積回路チップ６とは、その中継リード３ａ〜３ｆを
介して電気的に接続されている。なお、集積回路チップ
６には金線８を適用するのに対して、パワーチップ４に
はアルミニウム線１０を適用するのは、パワーチップ４
では、集積回路チップ６よりも大電流を扱うからであ
る。FIG. 4 shows a planar structure in the molding resin 12.
Shown in Referring to FIGS. 1 to 4, a power chip-side lead terminal 2 b connected to power chip 4 and an integrated circuit chip-side lead terminal 2 d connected to integrated circuit chip 6 protrude from mold resin 12. Has been established. Further, from the mold resin 12, the ends of the relay leads 3a to 3f electrically connected to the power chip 4 by the aluminum wire 10 and electrically connected to the integrated circuit chip by the gold wire 8 project. I have. Power chip 4
And the integrated circuit chip 6 are electrically connected via the relay leads 3a to 3f. Note that the gold wire 8 is applied to the integrated circuit chip 6, whereas the aluminum wire 10 is applied to the power chip 4
In this case, a larger current than that of the integrated circuit chip 6 is handled.
【００２０】パワーチップ４および集積回路チップ６を
含む回路ブロック図の一例は、従来の技術の項において
説明した図１８に示す回路ブロック図と同様である。し
たがって、中継リード３ａ〜３ｆは同図中のＡ〜Ｆ点に
対応している。同図に示されるように、Ａ〜Ｆ点は、パ
ワーチップ４のＩＧＢＴ４ａ〜４ｆのゲート電極とＨＶ
ＩＣ６ａ〜６ｃまたはＬＶＩＣ６ｄの各出力端子とをそ
れぞれ中継している部分である。その中継リード３ａ〜
３ｆの端部がモールド樹脂１２から突出している結果、
ＩＧＢＴ４ａ〜４ｆのゲート電圧、ＨＶＩＣ６ａ〜６ｃ
の出力信号（電圧）およびＬＶＩＣ６ｄの出力信号（電
圧）を直接測定することができ、電力半導体装置の電気
的な特性評価を容易に行なうことが可能となる。An example of a circuit block diagram including the power chip 4 and the integrated circuit chip 6 is similar to the circuit block diagram shown in FIG. 18 described in the section of the prior art. Therefore, the relay leads 3a to 3f correspond to points A to F in FIG. As shown in the figure, points A to F are the gate electrodes of the IGBTs 4a to 4f of the power chip 4 and the HVs.
This is a portion that relays each of the output terminals of the ICs 6a to 6c or the LVIC 6d. The relay leads 3a ~
As a result of the end of 3f projecting from the mold resin 12,
Gate voltages of IGBTs 4a to 4f, HVICs 6a to 6c
And the output signal (voltage) of the LVIC 6d can be directly measured, and the electrical characteristics of the power semiconductor device can be easily evaluated.
【００２１】上述した電力半導体装置の構造を得るに
は、モールド工程を１回とするのが望ましく、電力半導
体装置の電気的測定が容易になる効果に加えて、モール
ド工程を削減できる効果が得られる。そこで、そのよう
な電力半導体装置の製造方法の一例について図を用いて
説明する。図５を参照して、リードフレーム２のパワー
チップ用リードフレーム２ａ上にパワーチップ４をダイ
ボンドにより搭載する。また、集積回路チップ用リード
フレーム２ｃ上に集積回路チップ６をダイボンドにより
搭載する。In order to obtain the structure of the power semiconductor device described above, it is desirable to perform the molding step only once. In addition to the effect of facilitating the electrical measurement of the power semiconductor device, the effect of reducing the number of molding steps is obtained. Can be Therefore, an example of a method for manufacturing such a power semiconductor device will be described with reference to the drawings. Referring to FIG. 5, power chip 4 is mounted on power chip lead frame 2a of lead frame 2 by die bonding. Further, the integrated circuit chip 6 is mounted on the integrated circuit chip lead frame 2c by die bonding.
【００２２】次に、ワイヤボンディングによって、パワ
ーチップ４と所定の内部リードとをアルミニウム線１０
により電気的に接続する。同様に、集積回路チップ６と
所定の内部リードとを金線８により電気的に接続する。
なお、パワーチップ用リードフレーム２ａは、リード段
差部２ｅを介してパワーチップ側リード端子となるリー
ドに繋がれて、パワーチップ用リードフレーム２ａが位
置する面と集積回路チップ用リードフレーム２ｃが位置
する面とは同一平面上にはない。各パワーチップ用リー
ドフレーム２ａと集積回路チップ用リードフレーム２ｃ
とはタイバー２ｇなどによって繋がれている。Next, the power chip 4 and predetermined internal leads are connected to the aluminum wire 10 by wire bonding.
For electrical connection. Similarly, the integrated circuit chip 6 and predetermined internal leads are electrically connected by gold wires 8.
The power chip lead frame 2a is connected to a lead serving as a power chip side lead terminal via a lead step portion 2e, so that the surface on which the power chip lead frame 2a is located and the integrated circuit chip lead frame 2c are located. Plane is not on the same plane as Lead frame 2a for each power chip and lead frame 2c for an integrated circuit chip
Are connected by a tie bar 2g or the like.
【００２３】次に図６および図７を参照して、金型（図
示せず）をリードフレーム２に装着して、パワーチップ
側リード端子の側から樹脂注入ゲート１４により金型内
にモールド樹脂１２ａを注入する。注入の際には、特に
パワーチップ用リードフレーム２ａは金型に設けられた
可動ピン１６によって動かないように固定されている。
モールド樹脂１２によってパワーチップ４、集積回路チ
ップ６およびリードフレーム２を封止した後、中継リー
ド３ａ〜３ｆ、タイバー２ｇを含むリードをカットする
とともに、パワーチップ側リード端子および集積回路チ
ップ側リード端子を曲げることによって、図８に示す電
力半導体装置が完成する。Next, referring to FIGS. 6 and 7, a mold (not shown) is mounted on the lead frame 2, and the resin is injected into the mold by the resin injection gate 14 from the lead terminal side on the power chip side. Inject 12a. At the time of injection, the power chip lead frame 2a is particularly fixed so as not to move by a movable pin 16 provided on a mold.
After sealing the power chip 4, the integrated circuit chip 6, and the lead frame 2 with the mold resin 12, the leads including the relay leads 3a to 3f and the tie bar 2g are cut, and the power chip side lead terminal and the integrated circuit chip side lead terminal are cut. Is completed to complete the power semiconductor device shown in FIG.
【００２４】上述した製造方法では、図７に示すよう
に、樹脂注入ゲート１４から注入されるモールド樹脂１
２ａがリード段差部２ｅによって、パワーチップ４が搭
載されたパワーチップ用リードフレーム２ａの面 (表
面) とは反対側の面 (裏面) に位置するモールド樹脂が
比較的薄く形成されるべき部分へ積極的に流し込まれ
る。これによって、パワーチップ用リードフレーム２ａ
の裏面側のモールド樹脂の充填性が向上し、１回のモー
ルド工程によって所定のモールド樹脂１２を形成するこ
とができる。In the above-described manufacturing method, as shown in FIG.
2a is formed by a lead step 2e to a portion where the mold resin located on the surface (back surface) opposite to the surface (front surface) of the power chip lead frame 2a on which the power chip 4 is mounted should be formed relatively thin. Positively poured. As a result, the power chip lead frame 2a
The filling property of the mold resin on the back surface side of the substrate is improved, and the predetermined mold resin 12 can be formed by one molding process.
【００２５】このモールド工程に関して、従来の電力半
導体装置では、図１６に示すように、リードフレーム１
０２とヒートシンク１１６と間のモールド樹脂において
は、パワーチップにて発生した熱を効果的に放熱させる
ために、両者の電気的絶縁性が損なわれない程度に極力
薄くする必要がある。しかしながら、従来の電力半導体
装置の構造では、１回のモールド工程によって、リード
フレームとヒートシンクとの間にモールド樹脂を良好に
充填することが困難であった。そのため、既に説明した
ように、モールド工程を２回行うことによって、絶縁性
と放熱効果とを確保していたのである。Regarding this molding step, in a conventional power semiconductor device, as shown in FIG.
In order to effectively dissipate the heat generated by the power chip, the mold resin between the heat sink 02 and the heat sink 116 needs to be as thin as possible without impairing the electrical insulation between them. However, in the structure of the conventional power semiconductor device, it is difficult to satisfactorily fill the space between the lead frame and the heat sink with the molding resin by one molding process. Therefore, as described above, by performing the molding process twice, the insulating property and the heat radiation effect are ensured.
【００２６】従来の電力半導体装置に対して本電力半導
体装置では、上述したように、１回のモールド工程によ
ってモールド樹脂１２が形成されるため、必然的に中継
リード３ａ〜３ｆの端部もモールド樹脂１２より突出し
た構造が容易に得られる。これによって、電力半導体装
置の電気的測定が容易に行なえる効果に加えて、従来モ
ールド工程を２回行なっていたところを１回に低減で
き、生産コストの削減も同時に図ることが可能となる。In the present power semiconductor device, as compared with the conventional power semiconductor device, since the molding resin 12 is formed by one molding step, the ends of the relay leads 3a to 3f are necessarily molded. A structure protruding from the resin 12 can be easily obtained. As a result, in addition to the effect that the electrical measurement of the power semiconductor device can be easily performed, it is possible to reduce the number of times of performing the molding process from one to two in the past, and to reduce the production cost at the same time.
【００２７】また、中継リード３ａ〜３ｆとしては、迂
回させずにリードフレーム２のタイバー２ｇに向かって
最短距離となるように配置されていることが望ましい。
すなわち、完成した電力半導体装置においては、モール
ド樹脂１２によって封止された中継リード３ａ〜３ｆが
モールド樹脂１２内をモールド樹脂１２の外側へ向かっ
て最短距離で延びているのが望ましい。この場合には、
中継リード３ａ〜３ｆの撓みが少なくなり、製造工程中
にアルミニウム線１０や金線８が中継リード３ａ〜３ｆ
から外れてしまうなどの不具合を防止することができ
る。It is desirable that the relay leads 3a to 3f are arranged so as to be the shortest distance toward the tie bar 2g of the lead frame 2 without detouring.
That is, in the completed power semiconductor device, it is desirable that the relay leads 3a to 3f sealed by the mold resin 12 extend within the mold resin 12 to the outside of the mold resin 12 at the shortest distance. In this case,
The bending of the relay leads 3a to 3f is reduced, and during the manufacturing process, the aluminum wire 10 and the gold wire 8 are connected to the relay leads 3a to 3f.
It is possible to prevent troubles such as departure from the device.
【００２８】今回開示された実施の形態はすべての点で
例示であって制限的なものではないと考えられるべきで
ある。本発明の範囲は上記した説明ではなくて特許請求
の範囲によって示され、特許請求の範囲と均等の意味お
よび範囲内でのすべての変更が含まれることが意図され
る。The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
【００２９】[0029]
【発明の効果】本発明の１つの局面における半導体装置
によれば、電力用チップと集積回路チップとは、中継リ
ード部を介して第１の金属線および第２の金属線により
電気的に直接接続されている。その中継リード部の端部
がモールド樹脂より突出している。その結果、第１の金
属配線が接続されている電力用チップの特定の端子また
は第２の金属線が接続されている集積回路チップの特定
の端子の出力信号（電圧）を容易に測定することができ
る。According to the semiconductor device of one aspect of the present invention, the power chip and the integrated circuit chip are electrically directly connected to each other by the first metal wire and the second metal wire via the relay lead. It is connected. The ends of the relay leads protrude from the mold resin. As a result, it is possible to easily measure an output signal (voltage) of a specific terminal of the power chip to which the first metal wiring is connected or a specific terminal of the integrated circuit chip to which the second metal line is connected. Can be.
【００３０】好ましくは、モールド樹脂は１回のモール
ド工程によって形成されていることによって、モールド
工程の後にはモールド樹脂から中継リード部の端子が必
ず突出する。これにより、電力用チップまたは集積回路
チップの特定の出力信号（電圧）を容易に測定すること
ができるとともに、モールド工程数の削減も図ることが
できる。Preferably, the molding resin is formed in one molding step, so that the terminals of the relay lead portion always project from the molding resin after the molding step. Thus, a specific output signal (voltage) of the power chip or the integrated circuit chip can be easily measured, and the number of molding steps can be reduced.
【００３１】また好ましくは、中継リード部はモールド
樹脂内を最短距離でモールド樹脂の外側へ向かって延び
ていることにより、中継リード部の撓みが少なくなり、
製造工程において第１の金属線や第２の金属線が中継リ
ブから外れてしまうような不具合を防止することができ
る。Preferably, the relay lead portion extends in the mold resin toward the outside of the mold resin at the shortest distance, so that the bending of the relay lead portion is reduced,
In the manufacturing process, it is possible to prevent such a problem that the first metal wire and the second metal wire are detached from the relay rib.
【００３２】さらに好ましくは、電力用チップでは、集
積回路チップと比較して大電流を使う必要があるため、
第１の金属線は第２の金属線よりも大電流を流すことが
できるものが望ましい。More preferably, a power chip needs to use a larger current than an integrated circuit chip.
It is desirable that the first metal wire can carry a larger current than the second metal wire.
【図１】 本発明の実施の形態に係る電力半導体装置の
平面外観図である。FIG. 1 is a plan external view of a power semiconductor device according to an embodiment of the present invention.
【図２】 同実施の形態における電力半導体装置の１つ
の側面外観図である。FIG. 2 is an external side view of one of the power semiconductor devices according to the embodiment.
【図３】 同実施の形態における電力半導体装置の他の
側面外観図である。FIG. 3 is another side external view of the power semiconductor device according to the embodiment.
【図４】 同実施の形態における電力半導体装置の内部
の構造を示す平面図である。FIG. 4 is a plan view showing an internal structure of the power semiconductor device according to the embodiment.
【図５】 同実施の形態における電力半導体装置の製造
方法の一工程を示す平面図である。FIG. 5 is a plan view showing one step of a method for manufacturing the power semiconductor device in the embodiment.
【図６】 同実施の形態において、図５に示す工程の後
に行なわれる工程を示す平面図である。FIG. 6 is a plan view showing a step performed after the step shown in FIG. 5 in the embodiment.
【図７】 同実施の形態において、図６に示す工程のＡ
−Ａにおける断面図である。FIG. 7 is a view showing a step A shown in FIG.
It is sectional drawing in -A.
【図８】 同実施の形態における電力半導体装置の断面
図である。FIG. 8 is a cross-sectional view of the power semiconductor device according to the embodiment.
【図９】 従来の電力半導体装置の製造方法の一工程を
示す平面図である。FIG. 9 is a plan view showing one step of a conventional method for manufacturing a power semiconductor device.
【図１０】 図９に示す工程における断面図である。FIG. 10 is a cross-sectional view in the step shown in FIG. 9;
【図１１】 図９に示す工程の後に行なわれる工程を示
す平面図である。FIG. 11 is a plan view showing a step performed after the step shown in FIG.
【図１２】 図１１に示す工程における断面図である。FIG. 12 is a cross-sectional view in the step shown in FIG. 11;
【図１３】 図１１に示す工程の後に行なわれる工程を
示す平面図である。FIG. 13 is a plan view showing a step performed after the step shown in FIG.
【図１４】 図１３に示す工程における断面図である。FIG. 14 is a cross-sectional view in the step shown in FIG. 13;
【図１５】 図１３に示す工程の後に行なわれる工程を
示す平面図である。FIG. 15 is a plan view showing a step performed after the step shown in FIG.
【図１６】 図１５に示す工程における断面図である。FIG. 16 is a cross-sectional view in the step shown in FIG. 15;
【図１７】 従来の電力半導体装置の外観を示す図であ
り、（ａ）は平面外観図であり、（ｂ）は１つの側面外
観図であり、（ｃ）は他の側面外観図である。17A and 17B are views showing the appearance of a conventional power semiconductor device, wherein FIG. 17A is a plan view, FIG. 17B is one side view, and FIG. 17C is another side view. .
【図１８】 電力半導体装置の回路ブロック図である。FIG. 18 is a circuit block diagram of a power semiconductor device.
２ａ パワーチップ用リードフレーム、２ｂ パワーチ
ップ側リード端子、２ｃ 集積回路チップ用リードフレ
ーム、２ｄ 集積回路チップ側リード端子、２ｅ リー
ド段差部、２ リードフレーム、３ａ〜３ｆ 中継リー
ド、４ パワーチップ、４ａ〜４ｆ ＩＧＢＴ、６ 集
積回路チップ、６ａ〜６ｃ ＨＶＩＣ、６ｄ ＬＶＩ
Ｃ、８ 金線、１０ アルミニウム線、１２、１２ａ
モールド樹脂。2a Lead frame for power chip, 2b Lead terminal for power chip, 2c Lead frame for integrated circuit chip, 2d Lead terminal for integrated circuit chip, 2e Lead step, 2 Lead frame, 3a to 3f Relay lead, 4 power chip, 4a 4f IGBT, 6 integrated circuit chips, 6a to 6c HVIC, 6d LVI
C, 8 gold wire, 10 aluminum wire, 12, 12a
Mold resin.
フロントページの続き (72)発明者 田尻 貢 兵庫県伊丹市瑞原四丁目１番地 菱電セミ コンダクタシステムエンジニアリング株式 会社内 (72)発明者 岩崎 光孝 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 (72)発明者 ゴーラブ マジュムダール 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内Continued on the front page (72) Inventor Mitsuru Tajiri 4-1-1 Mizuhara, Itami-shi, Hyogo Ryoden Semiconductor System Engineering Co., Ltd. (72) Inventor Mitsutaka Iwasaki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Intra-company (72) Inventor Golove Majumudar 2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd.
Claims (4)
御するための集積回路チップと、 前記電力用チップを搭載するための第１フレーム部およ
び前記集積回路チップを搭載するための第２フレーム部
を有するリードフレーム部と、 前記電力用チップおよび前記集積回路チップを含む前記
リードフレーム部を封止するモールド樹脂とを備え、 前記リードフレーム部は、前記電力用チップとは第１の
金属線によって電気的に接続され、前記集積回路チップ
とは第２の金属線によって電気的に接続される中継リー
ド部を有し、 前記中継リード部の端部が前記モールド樹脂より突出し
ている、半導体装置。1. A power chip, an integrated circuit chip for controlling the power chip, a first frame for mounting the power chip, and a second frame for mounting the integrated circuit chip And a mold resin for sealing the lead frame portion including the power chip and the integrated circuit chip, wherein the lead frame portion is connected to the power chip by a first metal wire. A semiconductor device electrically connected and having a relay lead portion electrically connected to the integrated circuit chip by a second metal wire, wherein an end of the relay lead portion protrudes from the mold resin.
によって形成されている、請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said molding resin is formed by one molding step.
を最短距離で前記モールド樹脂の外側へ向かって延びて
いる、請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein said relay lead portion extends inside said mold resin by a shortest distance toward an outside of said mold resin.
りも多くの電流を流すことを許容する、請求項１〜３の
いずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein said first metal line allows more current to flow than said second metal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31098198A JP3843185B2 (en) | 1998-10-30 | 1998-10-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31098198A JP3843185B2 (en) | 1998-10-30 | 1998-10-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
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| JP2000138342A true JP2000138342A (en) | 2000-05-16 |
| JP3843185B2 JP3843185B2 (en) | 2006-11-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP31098198A Expired - Lifetime JP3843185B2 (en) | 1998-10-30 | 1998-10-30 | Semiconductor device |
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| JP (1) | JP3843185B2 (en) |
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| US6791167B2 (en) | 2002-03-28 | 2004-09-14 | Mitsubishi Denki Kabushiki Kaisha | Resin-molded device and manufacturing apparatus thereof |
| US7019394B2 (en) | 2003-09-30 | 2006-03-28 | Intel Corporation | Circuit package and method of plating the same |
| JP2006216989A (en) * | 2006-04-28 | 2006-08-17 | Matsushita Electric Ind Co Ltd | Semiconductor device and inverter circuit using the same |
| US7449774B1 (en) | 1999-10-01 | 2008-11-11 | Fairchild Korea Semiconductor Ltd. | Semiconductor power module having an electrically insulating heat sink and method of manufacturing the same |
| KR101116202B1 (en) | 2004-03-31 | 2012-03-07 | 르네사스 일렉트로닉스 가부시키가이샤 | semiconductor device |
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1998
- 1998-10-30 JP JP31098198A patent/JP3843185B2/en not_active Expired - Lifetime
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| US7449774B1 (en) | 1999-10-01 | 2008-11-11 | Fairchild Korea Semiconductor Ltd. | Semiconductor power module having an electrically insulating heat sink and method of manufacturing the same |
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| US6791167B2 (en) | 2002-03-28 | 2004-09-14 | Mitsubishi Denki Kabushiki Kaisha | Resin-molded device and manufacturing apparatus thereof |
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| KR101231792B1 (en) * | 2011-03-17 | 2013-02-08 | 엘에스파워세미텍 주식회사 | Semiconductor package |
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| JP2014130909A (en) * | 2012-12-28 | 2014-07-10 | Mitsubishi Electric Corp | Semiconductor device for electric power |
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| US9472538B2 (en) | 2013-07-04 | 2016-10-18 | Mitsubishi Electric Corporation | Semiconductor device manufacturing method and semiconductor device |
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| JPWO2018096573A1 (en) * | 2016-11-22 | 2019-02-28 | 三菱電機株式会社 | Semiconductor module |
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| WO2023223802A1 (en) * | 2022-05-19 | 2023-11-23 | ローム株式会社 | Semiconductor device |
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