JP2000133785A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To readily establish electrical connection by coating with a step reducing member a side of a conductive member which has a step between the top face and the insulating bottom surface arround the top face, and coating with a conductive film connected to the conductive member a side of the step reducing member, the top face of the conductive member, and the inner surface of a contact hole. SOLUTION: The top surface of an interlayer insulating film 10 that is exposed from the bottom of a contact hole 41 is higher than the top surface of an interlayer insulating film 40, that is exposed from the center of the bottom and projects from the bottom. A step at the bottom is reduced by a step- reducing member 50b. Hence, a Ti film 51 and a TiN film 52 that cover the top surface of the interlayer insulating film 40 have more uniform thickness, so as to establish good electrical connection between a conductive member 23 and a wire 54. A conductive member 23, a sidewall film 50a, and the step reducing member 50b are all made of amorphous silicon and are doped with phosphorus. Thus, contact resistances between these members are small, the effective contact areas is increased, thereby reducing the contact resistances.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an interlayer connection structure for connecting a lower conductive region and an upper conductive region via a contact hole formed in an interlayer insulating film. And a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7A shows a conventional dynamic run.
1 shows a cross-sectional view of a dumb access memory (DRAM). p-type
An element isolation structure 101 is formed on the surface of a silicon substrate 100.
Formed and an active region is defined. One active area
Inside, two MISFETs 102 are formed. each
The MISFET 102 is a storage device to which an n-type impurity is added.
Memory region 104, bit contact region 105, and
Formed on the channel region between the gate insulating film
And a word line 103. Word line 103
Act as a gate electrode. Above the word line 103
And the sides are SiO _TwoCovered with a covering insulating film 110 made of
ing.

An interlayer insulating film 111 is formed on the silicon substrate 100 so as to cover the MISFET 102. Storage contact holes 112 are formed in interlayer insulating film 111 at positions corresponding to storage regions 104. A storage electrode 114 made of amorphous silicon is formed on the inner surface of the storage contact hole 112, and the surface is covered with a dielectric film 115. The storage electrode 114 is electrically connected to the storage region 104. A counter electrode 116 made of amorphous silicon is formed on the surface of the dielectric film 115, and the storage electrode 1
14 and the counter electrode 116 constitute a capacitor.

In the position corresponding to the bit contact region 105 in the interlayer insulating film 111, the bit contact hole 1 is formed.
13 are formed. Bit contact hole 113
A conductive film 120 is formed on the inner surface of the substrate, and a dielectric film 121 covers the surface. A conductive film 122 is formed on the surface of the dielectric film 121. The conductive film 120 is deposited simultaneously with the storage electrode 114, the dielectric film 121 is deposited simultaneously with the dielectric film 115, and the conductive film 122 is deposited
6 and deposited simultaneously.

On the counter electrode 116, an interlayer insulating film 130
Are formed. The contact hole 1 is formed in the interlayer insulating film 130 at a position corresponding to the bit contact hole 113.
31 are formed. The contact hole 131 is a bit contact hole 11 when viewed from the normal direction of the substrate.
3 is included.

FIG. 7B is an enlarged sectional view of the bottom surface of the contact hole 131. The upper ends of the conductive films 120 and 122 protrude from the bottom surface of the contact hole 131.
The protrusion is formed because the conductive films 120 and 122 are less likely to be etched than the interlayer insulating films 111 and 130 and the dielectric film 121.

A Ti film 140 and a TiN film are formed so as to cover the upper surface of the interlayer insulating film 130 and the inner surface of the contact hole 131.
A film 141 and a W film 142 are formed. By patterning these three layers, bit lines 143 are formed. The bit line 143 contacts the conductive film 120 at the protruding portion of the conductive film 120. The Ti film 140 is for reducing the contact resistance between them. TiN film 141
Functions as a barrier layer for preventing interdiffusion of atoms between the W film 142 and the conductive film 120. Bit line 143
Are formed in the bit contact region 105 via the conductive film 120.
Is electrically connected to

[0008]

In the conventional example shown in FIG. 7B, the conductive film 12 is formed on the bottom of the contact hole 131.
The upper end of 0 protrudes. Because of the step of this protrusion,
The TiN film 141 may be locally thinned, and the function as a barrier layer may be reduced. W film 142 is Ti film 140
Alternatively, when reacting with the conductive film 120, the contact resistance increases.

An object of the present invention is to provide a semiconductor device in which the height of a conductive portion that appears on the bottom surface of a contact hole is different from the height of an insulating portion surrounding the conductive portion. An object of the present invention is to provide a semiconductor device capable of easily electrically connecting a portion and an upper layer wiring, and a method for manufacturing the same.

[0010]

According to one aspect of the present invention, a semiconductor substrate having a main surface, an interlayer insulating film formed on the main surface of the semiconductor substrate and provided with a contact hole, A conductive member constituting a part of the bottom surface of the conductive member, the height of the upper end surface of the conductive member and the height of the insulating bottom surface around the conductive member are different, and the conductive member forming a step, A step reducing member that covers the side surface of the step, and a conductive film that is arranged to cover the side surface of the step reducing member, the upper surface of the conductive member, and the inner surface of the contact hole, and is electrically connected to the conductive member. And a semiconductor device having:

Since the step reducing member is arranged on the side surface of the step, the step is reduced. Therefore, good electrical connection between the conductive film and the conductive member can be ensured.

According to another aspect of the present invention, a semiconductor substrate having a main surface, an interlayer insulating film formed on the main surface of the semiconductor substrate and provided with a contact hole, and a part of a bottom surface of the contact hole Wherein the height of the upper end surface of the conductive member and the height of the insulating bottom surface around the conductive member are different, and the conductive member forming a step and the inside of the contact hole. There is provided a semiconductor device having an embedding member formed of an embedding and conductive material, and a conductive film on an upper surface of the embedding member, which is in contact with the embedding member.

The conductive film is electrically connected to the conductive member via the embedded member. Since the embedding member also embeds the stepped portion, it is stably connected to the conductive member. Therefore, good electrical connection between the conductive film and the conductive material can be ensured.

According to another aspect of the present invention, there is provided a semiconductor substrate having a main surface, and a plurality of MISFETs formed on the main surface of the semiconductor substrate, wherein each of the MISFETs includes a source region, a drain region, A MISFET including a gate insulating film on a channel region between the two, and a gate electrode on the gate insulating film;
A first interlayer insulating film formed on the semiconductor substrate so as to cover the FET, and a plurality of first and second contact holes respectively formed in the first interlayer insulating film; Are arranged so as to match the first region of one of the source / drain regions of the MISFET, and each of the second contact holes is arranged to correspond to the second one of the source / drain regions of the MISFET. The first and second arrangements are arranged to match the second region.
And a first conductive layer disposed on an inner surface of the first contact hole, the first conductive hole having a shape matching the inner surface of the first contact hole, and electrically connected to the first region. A conductive member disposed on the inner surface of the second contact hole, having a shape matching the inner surface of the second contact hole, and electrically connected to the second region. A first dielectric film covering a member and a portion corresponding to an inner peripheral surface and a bottom surface of the first contact hole on a surface of the first conductive member, wherein the first dielectric film The first dielectric film, the upper edge of which is lower than the upper edge of the first conductive member; and the inner peripheral surface of the first contact hole among the surfaces of the first dielectric film. And a third conductive member covering a portion corresponding to the bottom surface, Low the third conductive member than the upper edge of the the upper edge of the sexual member first conductive member,
A second dielectric film covering a surface of the second conductive member;
A counter electrode layer disposed on the second dielectric film, the counter electrode layer forming a capacitor together with the second conductive member, and a counter electrode facing each of the second conductive members; Each of the electrode layers is connected to each other, and when viewed from a normal direction of the semiconductor substrate, the counter electrode layer includes an opening including an opening of the first contact hole. An electrode layer, a second interlayer insulating film disposed on the counter electrode layer, and a second contact hole provided in the second interlayer insulating film, the second contact hole being provided in a direction normal to the semiconductor substrate. When viewed, the second contact hole is disposed in the opening of the counter electrode layer and includes the opening of the first contact hole, and the first contact hole is formed on the bottom surface of the second contact hole. Outside the outer peripheral surface of the conductive member Are the second contact hole lower than the upper edge of the first conductive member, and a sidewall film disposed on the inner peripheral surface of the second contact hole. The inner peripheral surface is the first
The sidewall film continuous with the upper end surface of the conductive member, and the surface of a portion of the inner peripheral surface of the first conductive member that is higher than the upper edge of the first dielectric film. And a wiring disposed on an upper surface of the second interlayer insulating film, wherein the wiring is disposed on the upper surface of the second interlayer insulating film, and the wiring is disposed on the side surface of the first conductive member. A first conductive member that continuously covers a region up to a bottom surface of the opening via an inner peripheral surface of a wall film, an upper end surface of the first conductive member, and a slope of the step reducing member; And a wiring electrically connected to the semiconductor device.

The step on the bottom surface of the second contact hole is reduced by the sidewall film and the step reducing member. Therefore, good electrical connection between the wiring and the first conductive member can be secured.

According to another aspect of the present invention, a step of forming an impurity-doped region in a part of a surface layer of a semiconductor substrate, and forming a first interlayer insulating film on the surface of the semiconductor substrate. Forming a first contact hole exposing the surface of the impurity-added region in the first interlayer insulating film; and forming the first contact hole on an inner surface of the first contact hole. Forming a first conductive member having a shape matching the inner surface of the hole, and forming a second interlayer insulating film in the first contact hole and on the first interlayer insulating film; And the second
A second contact hole is formed in the interlayer insulating film so as to include the first contact hole when viewed from a normal direction of the semiconductor substrate, and an upper end of the first conductive member is Forming a first film covering the inner surface of the second contact hole and the upper surface of the second interlayer insulating film; and forming the first film anisotropically. By etching
The first film on the upper surface of the second interlayer insulating film and the upper surface of the first conductive member is removed, and the first conductive member is removed from the bottom surface of the second contact hole. Leaving the first film on the side surface of the protruding portion, forming a wiring layer covering the upper surface of the second interlayer insulating film and the inner surface of the second contact hole, and patterning the wiring layer And a step of leaving a wiring electrically connected to the first conductive member.

Since the first film is left on the side surface of the protrusion, the step on the bottom surface of the second contact hole can be reduced. Therefore, good electrical connection between the wiring and the first conductive member can be secured.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS.

The steps up to the state shown in FIG. 1A will be described. A field oxide film 2 having a thickness of 200 nm is formed on the surface of a p-type silicon substrate 1 using a local oxidation of silicon (LOCOS) technique. An active region is defined by field oxide film 2. A 7 nm thick SiO ₂ film is formed on the active region by thermal oxidation. This SiO ₂ film becomes the gate oxide film 3. A 150 nm thick polysilicon film containing phosphorus (P) is deposited on the SiO ₂ film by chemical vapor deposition (CVD). This polysilicon film becomes the word line 4. On the polysilicon film,
A 100 nm thick SiO ₂ film is deposited by CVD.
This SiO ₂ film becomes the upper protective film 5.

The thermally oxidized SiO ₂ film, the polysilicon film, and the SiO ₂ film thereon are patterned to leave a plurality of word lines 4. The gate oxide film 3 remains under the word line 4,
The upper protective film 5 remains on the word line 4. A plurality of word lines 4 are arranged in parallel with each other, and two word lines 4 pass over one active region, and field oxide films 2 on both sides thereof.
The word line 4 is also arranged above.

Using the word line 4 as a mask, the surface of the active region
Phosphorus ion (P⁺Inject). Ion implantation conditions
Is, for example, an acceleration energy of 20 keV and a dose of 1 × 10
¹⁴cm ^-2It is. By this ion implantation, MISFET
Source / drain regions are formed. Source / Dray
One of the storage areas is called storage area 7, and the other is
This is referred to as a short contact region 8. One active territory
The two MISFETs formed in the region have one bit
The contact region 8 is shared.

On the side walls of the word line 4 and the upper protective film 5,
The sidewall protection film 6 is formed. The sidewall protective film 6 has a thickness of 100
After depositing an SiO ₂ film having a thickness of nm, it is formed by anisotropic reactive ion etching (RIE).

On the entire surface of the substrate, a thickness of 100 n is formed by CVD.
An mN SiN film 9 is deposited, and an interlayer insulating film 10 made of borophosphosilicate glass (BPSG) is deposited thereon. The interlayer insulating film 10 is formed by depositing a BPSG film having a thickness of 2 μm, performing a heat treatment in a nitrogen atmosphere at a temperature of 850 ° C. for 15 minutes, and reflowing the BPSG film.

Next, steps required until a state shown in FIG. A storage contact hole 20 and a bit contact hole 21 are formed in the interlayer insulating film 10. Storage contact hole 20 is arranged at a position corresponding to storage region 7, and bit contact hole 21 is arranged at a position corresponding to bit contact region 8. The etching of the interlayer insulating film 10 is performed by, for example, C ₄
RIE using a mixed gas of F ₆ , Ar, CO, and O ₂
Performed by At this time, the SiN film 9 functions as an etching stop layer.

Si exposed on the bottom of each contact hole
The N film 9 is etched, and the storage region 7 and the bit
A part of the surface of the contact area 8 is exposed. SiN film 9
Etching is, for example, CHF_ThreeAnd O_TwoAnd RI using
Perform by E. When the SiN film 9 is etched,
The protective film 5 and the sidewall protective film 6 function as an etching stop layer.
Good. The storage area 7 and the bit contact area
8 with thin SiO _TwoAfter forming a film, the SiN film 9
After removal of this thin SiO_TwoWet etch membrane
It may be removed with a brush or the like. In this case, storage area 7 and
And the bit contact region 8 has an etching atmosphere of the SiN film 9.
Because they are not directly exposed to the atmosphere, their surface damage
Can be reduced.

On the inner surfaces of the storage contact holes 20 and the bit contact holes 21 and on the upper surface of the interlayer insulating film 10, an amorphous silicon film containing P and having a thickness of 100 nm is deposited by CVD. The deposition of the amorphous silicon film is performed at a growth temperature of 500 ° C. using SiH ₄ and PH ₃ as source gases. The phosphorus concentration is 1
× 10 ²¹ cm ^-3 .

The amorphous silicon film on the interlayer insulating film 10 is removed by mechanical chemical polishing (CMP). On the inner surface of the storage contact hole 20, the storage electrode 22 having a shape matching the inner surface shape remains, and on the inner surface of the bit contact hole 21, a conductive member 23 having a shape matching the inner surface shape remains.

Next, steps required until a state shown in FIG. A 6-nm-thick SiN film is deposited by CVD so as to cover the inner surfaces of the storage contact hole 20 and the bit contact hole 21 and the upper surface of the interlayer insulating film 10. The surface of the SiN film is thermally oxidized. This thermal oxidation is performed, for example, when a silicon substrate is
This is performed under the same conditions as those for forming the iO ₂ film. SiN
A part of the film is changed to a SiON film, and a dielectric film 30 is formed.

On the surface of the dielectric film 30, P is set to 1 × 10 ²¹
50n thickness of amorphous silicon containing cm ^-3
m counter electrode layers 31 are deposited by CVD. The counter electrode layer 31 is deposited at a growth temperature of 500 ° C. using SiH ₄ and PH ₃ as source gases.

As shown in FIG. 2B, the counter electrode layer 31
An opening 32 is formed in the opening. The opening 32 is arranged so as to include the bit contact hole 21 when viewed from the normal direction of the substrate. The etching of the counter electrode layer 31 is performed by Cl ₂
And RIE using O ₂ . The dielectric film 30 functions as an etching stop layer. A part (conductive member) 31 a of the counter electrode layer 31 remains along the inner surface of the bit contact hole 21. The upper end of the conductive member 31a is slightly lower than the upper surface of the interlayer insulating film 10.

3 and 4, only the vicinity of the opening of the bit contact hole 21 is enlarged.

As shown in FIG. 3A, an interlayer insulating film 40 of BPSG having a thickness of 300 nm is deposited on the entire surface of the substrate so as to fill the insides of the storage contact holes 20 and the bit contact holes 21. The deposition of the interlayer insulating film 40 is performed by using tetraethylorthosilicate (TEOS), ozone (O ₃ ), triethylboron (TEB), and tetraethylphosphous (T
This is performed by CVD using EPO). After film formation, heat treatment is performed at 900 ° C. for 10 minutes in a nitrogen atmosphere, and BPSG
Reflow the membrane.

As shown in FIG. 3B, the interlayer insulating film 40
Then, a contact hole 41 is formed. The etching of the interlayer insulating film 40 is performed, for example, by RIE using CHF ₃ and CF _4.
It is performed by The contact hole 41 is arranged so as to include the bit contact hole 21 and to be included in the opening 32 when viewed from the normal direction of the substrate.

On the bottom surface of the contact hole 41, the interlayer insulating film 40, the conductive member 3
1a, the dielectric film 30, the conductive member 23, and the interlayer insulating film 10 are exposed in this order. Since the etching rate for silicon is lower than the etching rate for BPSG, the upper surface of the interlayer insulating film 40 exposed at the bottom of the contact hole 41 is lower than the upper end of the conductive member 31a.
Since the upper end of the conductive member 31a is etched in the step of forming the opening 32 in FIG. 2B, the upper end is lower than the upper end of the conductive member 23.

When the contact hole 41 is formed, the dielectric film 30 is also etched.
It is slower than the etching rate of SG. For this reason, the upper surface of the interlayer insulating film 10 exposed at the bottom of the contact hole 41 is higher than the upper surface of the interlayer insulating film 40 exposed at the center of the bottom of the contact hole 41. The upper end of the conductive member 23 protrudes from the bottom of the contact hole 41. The protrusion has an annular shape when viewed from the normal direction of the substrate.

In this embodiment, the contact holes 4
1 shows a case where the diameter of the bit contact hole 21 is larger than the diameter of the bit contact hole 21. Even when the diameter of the contact hole 41 is equal to or smaller than that of the bit contact hole 21, a protrusion may appear due to a positional deviation between the two. Therefore, this embodiment is also effective when the diameter of the contact hole 41 is equal to or smaller than the diameter of the bit contact hole 21.

As shown in FIG.
Thickness on the inner surface of the
100 nm phosphorus-doped amorphous silicon film 50
Is deposited. The deposition of the amorphous silicon film 50
SiH as feed gas_FourAnd PH _ThreeBy CVD using
The growth is performed at a temperature of 500 ° C.

As shown in FIG. 4A, the amorphous silicon film 50 is anisotropically etched to leave the side wall film 50a on the inner peripheral surface of the contact hole 41, and to form on the side wall of the step portion on the bottom surface. The step reducing member 50b made of amorphous silicon is left. The anisotropic etching of the amorphous silicon film 50 is performed by RIE using HBr and O ₂ .

As shown in FIG. 4B, a thickness 50 covering the inner surface of the contact hole 41 and the upper surface of the interlayer insulating film 40 is obtained.
A Ti film 51 of nm is deposited. On the surface of the Ti film 51, a TiN film 52 having a thickness of 50 nm is deposited. The Ti film 51 is deposited by sputtering using a Ti target, and the TiN film 52 is deposited by reactive sputtering using a Ti target.

On the surface of the TiN film 52, a thickness of 100 nm
Is deposited. The W film 53 is deposited at a growth temperature of 350 ° C. by CVD using WF ₆ as a source gas. Ti film 51, TiN film 52, and W film 53
Are patterned to leave the wiring 54.

The Ti film 51 is a film for obtaining good electrical contact between the wiring 54 and the conductive member 23 made of silicon. The TiN film 52 functions as a barrier layer for suppressing the reaction between W and Ti and between W and Si. Wiring 5
4 is electrically connected to the bit contact region 8 shown in FIG.

In the case of the above embodiment, in the step shown in FIG. 4A, the step on the bottom surface of the contact hole 41 is reduced by the step reducing member 50b. Therefore, the Ti film 5
1 and the thickness of the TiN film 52 can be made more uniform. Therefore, the TiN film 52 can sufficiently function as a barrier layer, and the conductive member 23 and the wiring 5
4 can be obtained with a good electrical connection.

Conductive member 23, sidewall film 50
a and the step reduction member 50b are both formed of phosphorus-doped amorphous silicon. Therefore, it is considered that the contact resistance between these members is small. Wiring 54
Is not only in direct contact with the upper end surface of the conductive member 23 but also connected to the conductive member 23 via the sidewall film 50a and the step reducing member 50b. Therefore, the effective contact area between the conductive member 23 and the wiring 54 increases. By increasing the effective contact area between the two, the contact resistance between the two can be reduced.

Further, since the step on the underlying surface of the wiring 54 is reduced, there is also an effect that the margin when the wiring 54 is formed by patterning is increased.

In the above embodiment, the side wall film 50a
Although the case where the step difference reducing member 50b is formed of amorphous silicon has been described, it may be formed of another conductive material. For example, it may be formed of polysilicon, Ti, or the like.

Further, the sidewall film 50a and the step reducing member 50b may be formed of an insulating material such as SiO ₂ . When the sidewall film 50a and the step reducing member 50b are formed of an insulating material, the wiring 54 and the conductive member 23
Although the effect of increasing the substantial contact area between them cannot be obtained, the effect of reducing the step can be obtained. In addition, opening 3
Even if an alignment error occurs between the wiring 2 and the contact hole 41, an electrical short circuit between the wiring 54 and the counter electrode layer 31 can be prevented.

Next, a second embodiment will be described with reference to FIG. The steps up to the state of FIG.
This is the same as in the first embodiment. Hereinafter, steps after FIG. 3C will be described. The amorphous silicon film 50 on the flat surface of the interlayer insulating film 40 is removed by CMP.

FIG. 5A shows a state after the CMP. The conductive film 50c made of amorphous silicon remains on the inner surface of the contact hole 41.

As shown in FIG. 5B, on the surface of the conductive film 50c and on the upper surface of the interlayer insulating film 40, a Ti film 51, T
An iN film 52 and a W film 53 are deposited. The deposition of these films is performed in the same manner as the deposition of the corresponding films shown in FIG. The Ti film 51, the TiN film 52, and the W film 53 are patterned to leave the wiring 54.

In the case of the second embodiment, the conductive film 50c reduces the unevenness on the bottom surface of the contact hole 41. Also,
Since the wiring 54 is connected to the conductive member 23 via the conductive film 50c, the effective contact area between the wiring 54 and the conductive member 23 can be increased. Therefore, the first
As in the case of the embodiment, good electrical connection between the wiring 54 and the conductive member 23 can be secured.

Next, a modification of the first and second embodiments will be described with reference to FIG. In the first and second embodiments, the amorphous silicon film 50 does not completely fill the contact hole 41 in the state shown in FIG. 3C. The amorphous silicon film 50 may be deposited thick, and the inside of the contact hole 41 may be completely filled with the amorphous silicon film 50. Thereafter, in the case of the modification of the first embodiment, the amorphous silicon film 50 is etched back until the upper surface of the interlayer insulating film 40 is exposed. In the case of the modification of the second embodiment, the interlayer insulating film 40
Is polished until the upper surface of the substrate is exposed.

As shown in FIG.
The embedded member 50d made of amorphous silicon remains therein. On the buried member 50d and the interlayer insulating film 40, Ti
A film 51, a TiN film 52, and a W film 53 are deposited, and a wiring 5
4 is formed.

The wiring 54 is connected to the conductive member 23 via the embedded member 50d. Also in this case, since the thickness of the TiN film 52 can be made uniform, good electrical connection between the wiring 54 and the conductive member 23 can be ensured.

In the above embodiment, the case where the upper end of the conductive member 23 protrudes from the bottom of the contact hole 41 has been described. Even when the upper end of the conductive member 23 is lower than the surrounding bottom surface, the side wall film 50a and the step reducing member 50b of the first embodiment shown in FIG. 4B and the second step shown in FIG. By providing the conductive film 50c of the embodiment or the embedding member 50d of the modification shown in FIG.
It is possible to secure a good electrical connection between the conductive member 23 and the conductive member 23. That is, when the height of the upper end surface of the conductive member 23 is different from the height of the insulating bottom surrounding the conductive member 23 and a step is formed, the same method as in the above embodiment can be applied.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0056]

As described above, according to the present invention,
Even when the bottom surface of the contact hole has irregularities, it is possible to secure a good electrical connection between the conductive portion appearing on the bottom surface of the contact hole and the upper wiring.

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of a substrate for describing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of the substrate for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view (part 3) of the substrate for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view (part 4) of the substrate for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view of a substrate for describing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor device according to a modification of the first and second embodiments of the present invention.

FIG. 7 shows a bit line and MISFE of a conventional DRAM.
FIG. 4 is a cross-sectional view showing a connection structure between T and a source / drain region.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 3 Gate oxide film 4 Word line 5 Upper protective film 6 Sidewall protective film 7 Storage region 8 Bit contact region 9 SiN film 10 Interlayer insulating film 20 Storage contact hole 21 Bit contact hole 22 Storage electrode 23 Conductivity Member 30 Dielectric film 31 Counter electrode layer 32 Opening 40 Interlayer insulating film 41 Contact hole 50 Amorphous silicon film 50a Sidewall film 50b Step reducing member 50c Conductive film 50d Embedding member 51 Ti film 52 TiN film 53 W film 54 Wiring

Claims (7)

[Claims] A semiconductor substrate having a main surface; an interlayer insulating film formed on the main surface of the semiconductor substrate and provided with a contact hole; and a conductive member forming a part of a bottom surface of the contact hole. A height difference between an upper end surface of the conductive member and an insulating bottom surface around the conductive member, the conductive member forming a step; a step reducing member covering a side surface of the step; A semiconductor device having a conductive film disposed to cover a side surface of a relaxation member, an upper surface of the conductive member, and an inner surface of the contact hole, and electrically connected to the conductive member. 2. The semiconductor device according to claim 1, wherein said conductive film is in direct contact with an upper end surface of said conductive member. 3. The semiconductor device according to claim 1, wherein the step reducing member is formed of a conductive material. 4. A semiconductor substrate having a main surface, an interlayer insulating film formed on the main surface of the semiconductor substrate and provided with a contact hole, and a conductive member forming a part of a bottom surface of the contact hole. The upper end surface of the conductive member and the height of the insulating bottom surface around the conductive member are different from each other, and the conductive member forming a step is embedded in the contact hole and formed of a conductive material. A semiconductor device comprising: a buried member; and a conductive film on an upper surface of the buried member, which is in contact with the buried member. 5. A semiconductor substrate having a main surface, and a plurality of MISFs formed on the main surface of the semiconductor substrate
ET, wherein each of the MISFETs has a source region,
A drain region, a gate insulating film on a channel region therebetween, and a MISFET including a gate electrode on the gate insulating film; and a MISFET formed on the semiconductor substrate so as to cover the MISFET. A first interlayer insulating film, and a plurality of first and second contact holes respectively formed in the first interlayer insulating film, wherein each of the first contact holes is a source / drain region of the MISFET. Each of the second contact holes is arranged to match one of the first regions, and each of the second contact holes is arranged to match the other of the source / drain regions of the MISFET. A second contact hole, disposed on an inner surface of the first contact hole, having a shape aligned with the inner surface of the first contact hole, A first conductive member electrically connected to the region, and a second conductive region disposed on an inner surface of the second contact hole, the second conductive region having a shape matching the inner surface of the second contact hole; A second conductive member electrically connected to the first conductive member; and a first portion covering a portion corresponding to an inner peripheral surface and a bottom surface of the first contact hole on a surface of the first conductive member.
The first dielectric film, wherein an upper edge of the first dielectric film is lower than an upper edge of the first conductive member; and the first dielectric film. A third conductive member covering a portion corresponding to an inner peripheral surface and a bottom surface of the first contact hole on the surface of the first conductive member, wherein an upper edge of the third conductive member has the first conductive member. A third conductive member lower than an upper edge of the conductive member; a second dielectric film covering a surface of the second conductive member; and a facing member disposed on the second dielectric film. An electrode layer, wherein the counter electrode layer forms a capacitor together with the second conductive member, and each of the counter electrode layers facing each of the second conductive members is connected to each other; When viewed from the normal direction of the semiconductor substrate, the counter electrode layer includes an opening including the opening of the first contact hole. A second interlayer insulating film disposed on the counter electrode layer, and a second contact hole provided in the second interlayer insulating film, wherein: When viewed from the normal direction of the semiconductor substrate, the second contact hole is disposed in the opening of the counter electrode layer, and includes the opening of the first contact hole. The second contact hole, a portion of the bottom surface outside the outer peripheral surface of the first conductive member being lower than the upper edge of the first conductive member; A sidewall film disposed on a peripheral surface, wherein the inner peripheral surface of the sidewall film is continuous with an upper end surface of the first conductive member; and the first conductive member. Of the inner peripheral surface of the first Than the upper edge of the body layer disposed on the surface of the upper portion,
A step reducing member having a slope that is gentler than an inner peripheral surface of the first conductive member; and a wiring disposed on an upper surface of the second interlayer insulating film, wherein the wiring is formed in the side wall film. Via the peripheral surface, the upper end surface of the first conductive member, and the slope of the step reducing member, a region up to the bottom surface of the opening is continuously covered, and the first conductive member is electrically connected. A semiconductor device having the wiring connected thereto; 6. The semiconductor device according to claim 5, wherein said step reduction member is formed of a conductive material. 7. A step of forming an impurity-doped region to which impurities are added in a part of a surface layer of a semiconductor substrate; a step of forming a first interlayer insulating film on a surface of the semiconductor substrate; Forming a first contact hole exposing the surface of the impurity-added region in one interlayer insulating film; and forming a shape on the inner surface of the first contact hole, the inner surface being matched with the inner surface of the first contact hole. Forming a first conductive member having: a step of forming a second interlayer insulating film in the first contact hole and on the first interlayer insulating film; A second contact hole is formed in the insulating film so as to include the first contact hole as viewed from a normal direction of the semiconductor substrate, and an upper end of the first conductive member is placed in the second contact hole. The bottom of the contact hole Projecting; forming a first film covering an inner surface of the second contact hole and an upper surface of the second interlayer insulating film; anisotropically etching the first film to form the first film; The first film on the upper surface of the second interlayer insulating film and on the upper end surface of the first conductive member is removed, and the first conductive member protrudes from the bottom surface of the second contact hole. Leaving the first film on the side surface of the portion, forming a wiring layer covering the upper surface of the second interlayer insulating film and the inner surface of the second contact hole, and patterning the wiring layer. Leaving a wiring electrically connected to the first conductive member.