JP2000132508A - Power down control device and method therefor, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption with no sleeping of a CUP by providing an extending means which extends the cycle of actual access operations set to an accessed device based on an access request signal that is produced in a low power operation mode. SOLUTION: An address decoder 10 contained in a decoder 2 decodes the address signals received from a CPU 1 and a DMA control part 7 and outputs a 1st access signal. An OR gate 12 detects that anyone of a ROM 4, a RAM 5, a motor control part 6, the part 7, an I/F control part 8, a head control part 9 and an NC (a dummy element that is not packaged) is accessed and outputs an access signal ACS to an access delay control part 3. When an access request is received in a low power operation mode, the timing of an actual access operation is expanded and delayed. Thus, the power consumption is reduced with no sleeping of the CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving technique in an apparatus such as a recording apparatus using a central processing unit such as a CPU.

[0002]

2. Description of the Related Art Conventionally, a printer used as an output device of a computer can be distinguished by a state when a power switch is turned off. Although the display panel and the like are turned off, they are actually divided into those that are actually performing circuit operations.

In the latter case, a low-power-consumption element such as a CMOS IC is used to reduce power consumption, and the CPU is put to sleep.

[0004] However, when the CPU is put to sleep to reduce power consumption, the operation of the CPU is completely stopped, so that processing such as self-check cannot be performed.

In order to optimize the contents of the initialization processing when the power switch is turned on next time while the CPU is in a sleep state, a timer whose power supply is backed up by a battery or the like is provided. Was measured, and the next time the power switch was turned on, it was determined whether or not to clean the nozzles of the print head based on the measurement result.

[0006]

As described above, when the CPU is put to sleep, the software cannot perform self-check processing, measure the duration of the power switch-off state, and the like. In order to optimize the contents of the initialization processing at the time of switch-on, a special additional circuit such as a timer backed up by a battery or the like had to be provided.

For this reason, there has been a demand for reducing power consumption without putting a CPU (central processing unit) to sleep.

The present invention has been made under such a background, and an object thereof is to reduce power consumption without putting a central processing unit to sleep.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is a power down control device mounted on a device having at least two operation modes, a normal operation mode and a low power operation mode. And expansion means for expanding the period of the actual access operation to the accessed device based on the access request signal generated in the low power operation mode.

The present invention also relates to a power down control method applied to a device having at least two operation modes, a normal operation mode and a low power operation mode, wherein the power down control method includes: And a decompression step for decompressing a period of an actual access operation to the accessed device based on the extension process.

Further, the present invention is a storage medium storing a program to be executed by being mounted on an apparatus having at least two operation modes of a normal operation mode and a low power operation mode, wherein the program has a low power operation mode. A decompression routine is provided for extending the cycle of an actual access operation to the accessed device based on the access request signal generated in the mode.

Further, in the present invention, the stretching means, the step,
The routine includes timing means, steps, and a routine for timing a delay time for delaying the access request signal and outputting the access request signal to the accessed device.

In the present invention, the stretching means, the step,
The routine includes a wait unit, a step, and a routine that waits for the end of the current access until the processing of the accessed device corresponding to the access request signal ends.

In the present invention, the stretching means, the step,
The routine includes a timing unit, a step, and a routine for measuring a delay time for delaying the access request signal and outputting the access request signal to the accessed device, and a process until the process of the accessed device corresponding to the access request signal ends. And wait means, steps and routines for waiting for the end of the current access.

In the present invention, the stretching means, the step,
The routine extends the period of the actual access operation to the accessed device based on the access request signal by dummy-accessing the mapped address of the device not mounted.

In the present invention, the stretching means, the step,
The routine extends the period of the actual access operation based on the access request signal generated from the central processing unit.

In the present invention, the stretching means, the step,
The routine extends the period of the actual access operation based on the access request signal generated from the direct memory access control unit.

In the present invention, the power control device is mounted on a printing device, the power control method is applied to the printing device, and the program is executed by the printing device.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a perspective view showing a schematic configuration of a main part of a printer to which the power down control device according to the present invention is applied. In FIG. 2, reference numeral 51 denotes a recording sheet; 52, a roller for conveying the recording sheet 51;
Is driven to rotate by a paper feed motor 58 to feed the recording paper 51. 53 is a carriage 55
It is a shaft for supporting. The carriage 55 has a print head 54 mounted thereon, and scans the recording paper 51 by being reciprocated by a carriage motor 57 while being guided by a shaft 53.

Reference numeral 56 denotes a C to be described later for controlling the printer.
It is a control board on which a gate array in which control circuits such as PU1, ROM4, and RAM5 are integrated, an I / F section with a host computer, and the like are mounted.

FIG. 1 is a block diagram showing a main part of an electric circuit mounted on the control board 56 of FIG. 1 is a CPU for controlling the entire printer, and 2 is a decoder. The decoder 2 decodes an address signal output from the CPU 1 and a DMA (Direct Memory Access) control unit 7 described later when accessing a peripheral element, and outputs an access signal (chip select signal CS0 to CS) for each peripheral element.
S7), and an access signal ACS is generated.

Reference numeral 3 denotes an access delay control unit including a timer for delaying access by the CPU 1 and the DMA control unit 7, and 4 denotes an RO in which a control program of the recording apparatus is stored.
M and 5 are used as a work area of the CPU 1, and RAM for expanding and storing print data, 6 is a motor control unit for controlling the paper feed motor 58 and the carriage motor 57, and 7 is print data DMA controller for developing / processing, transferring to the print head, etc., 8 is an I / F controller for performing communication such as reception of print data from the host computer, and 9 is creation of drive timing signals for the print head, etc. This is a head control unit that performs the following.

An address decoder 10 in the decoder 2 decodes an address signal from the CPU 1 and the DMA controller 7 and outputs a first access signal. 12
To detect whether any of the ROM 4, the RAM 5, the motor control unit 6, the DMA control unit 7, the I / F control unit 8, the head control unit 9, and the NC (dummy element not mounted) has been accessed. And outputs an access signal ACS to the access delay control unit 3.

Numeral 11 denotes a NAND gate which takes a logical product of the address decoder 10 and the enable signal ENA output from the access delay control section 3, and outputs a second access signal (chip select signals CS0 to CS7). Of the chip select signals CS0 to CS7, the chip select signal CS7 is a signal for selecting a dummy peripheral element (NC) that is not mounted, and the dummy peripheral element (NC) is naturally connected to the address bus. Mapped to the corresponding address space.

FIG. 3 is a block diagram showing an example of the configuration of the access delay control unit 3.
This timer is cleared when CS is “L” and counts when it is “H”. Reference numerals 22 to 25 denote pulse generators for delay, which are connected to the output of the timer 21.
When the access signal ACS rises, the timer 21
Starts counting and presets t1, t2, t3, t
A pulse is generated after 4 hours. Flip-flops 27 to 30 invert the output from "L" to "H" at the falling edge of the input signal.

Reference numeral 31 denotes an AND gate, which takes the logical product of the output signal of the flip-flop 27 and the output signal of the inverter 38. 32 to 25 are NAND gates, NA
The ND gate 32 calculates the logical product of the output signal of the flip-flop 28 and the inverted input signal of the read R1X signal described later, and the NAND gate 33 calculates the logical product of the output signal of the flip-flop 29 and the inverted input signal of the write signal W1X signal described later. Perform a logical conjunction. The NAND gate 34 calculates the logical product of the output signal of the flip-flop 29 and the access signal ACS output from the decoder 12, and the NAND gate 35 calculates the logical product of the output signal of the flip-flop 30 and the decoder 12.
AND with the access signal ACS output from.
Note that the read signal R1X and the write signal W1X are
1 or a signal output from the DMA control unit 7.

Reference numeral 36 denotes a selector for switching the output signal between the normal operation mode and the low power mode. When the output of the mode register 37 is "L" (normal operation mode), the selector 36 has an input terminal. A0 to A3 are selected, and input terminals B0 to B when "H" (low power mode)
3 and outputs the signal of the selected input terminal to the output terminal Y0.
To Y3. The mode register 37 can be set by a program. The output signal of the power down signal PDOWN, for example, is set to “H” when entering a low power mode at power off, and returns to the normal mode at power on. Sometimes "L" is set.

The delay pulse generator 22, flip-flop 27, and AND gate 31 generate an enable signal ENA in the low power mode, and the delay pulse generator 23, flip-flop 28, AND gate 32, 33 generates a write signal R2X and a write signal W2X in the low power mode. Further, the delay pulse generator 24, the flip-flop 29, and the AND gate 34
Generates a wait signal WAIT in the normal mode, and the delay pulse generator 25, the flip-flop 30, and the AND gate 35 output the wait signal WAIT in the low power mode.
Generate AIT.

FIG. 4 is a time chart showing the operation timing of the power-down control device in the configuration shown in FIGS.

The signals ASX, R1 shown in FIGS.
X and W1X are signals output from the CPU 1 or the DMA control unit 7, the ASX signal is a strobe signal of negative logic indicating determination of an address signal, R1X is a first read signal output at the time of reading, and W1X Is a first write signal output at the time of writing.

After the strobe signal ASX falls, the delay pulse generator 22 generates the delay pulse signal P1 after a lapse of time t1. Then, based on the delay pulse signal P1, the access delay circuit 3 outputs a positive logic enable signal ENA to the NAND gate 11 of the decoder 2, and the NAND gate 11 outputs the second access signal (chip select signals CS0 to CS7). Is output.
Note that the enable signal ENA becomes a signal obtained by inverting the strobe signal ASX when the mode is switched to the normal mode and the power down signal PDOWN becomes “L”.

The delay pulse generator 23 generates a delay pulse signal P2 after a lapse of time t2 after the strobe signal ASX falls. Then, the delay pulse signal P
2, a second read signal R2X and a write signal W2X of negative logic are output from the access delay circuit 3 and the access is executed. The delay pulse generator 24 generates a delay pulse signal for generating a positive logic WAIT signal for securing the access time T3 required by the element to be accessed in the normal mode.

The delay pulse generator 25 generates the delay pulse signal P4 after the elapse of the time t4 after the fall of the strobe signal ASX. Then, when the positive logic wait signal WAIT falls based on the delay pulse signal P4, the CPU 1 or the DMA control unit 7 is notified that the current read / write access is enabled, and the current read / write access is enabled. Access ends.

As is clear from the above description, in the low power mode, when an access request is made, the actual access cycle to the accessed device is extended by delaying the actual access operation timing. The actual access operation time per unit time is shortened.

For example, t1 = 1000 microseconds, t2
= 1001 microseconds and t3 = 1002 microseconds, when the maximum time of the normal access cycle by the CPU 1 is 1 microsecond, the actual access operation time in the low power mode is the access time in the normal mode. It is almost 1/1000 of the operation time.

By the way, C which is currently the mainstream of IC
Since the MOS element consumes almost no current when not in operation and consumes through current or the like during operation (at the time of change during access or the like: activation), the access operation time during the low power mode as described above That is, by shortening the activation time of the accessed device, the average power consumption in the low power mode can be reduced.

As described above, the dummy access to the dummy element NC (CS7) mapped on the address space is performed at this timing because there is no peripheral device that consumes current at this timing. Thus, the same effect as when the access cycle is lengthened is exhibited, and the average power consumption in the low power mode can be further reduced.

As described above, in the present embodiment, the CPU is put to sleep by extending the access cycle to the peripheral device to reduce the number of accesses per unit time and shortening the actual access operation time to the peripheral device. Power consumption without any problems. Therefore, even in a low power consumption mode such as when the power is off,
Without using a timer backed up by a battery, the power-off time is measured by software,
Processing such as cleaning the nozzles of the print head can be performed based on the measured power-off time.

The present invention is not limited to the above-described embodiment. For example, the normal mode and the low-power mode may be appropriately changed according to the contents of software processing to be executed in a low-power state. Is also good. Further, by making connection / disconnection of the OR gate 12 selectable according to the peripheral device, at the time of power-off, it is possible to select only those peripheral devices that need to be accessed at the time of power-off, thereby simplifying the circuit configuration. It is also possible to convert. If the power consumption is within the allowable range in a state where the peripheral device is actually accessing, the second access signals (chip select signals CS0 to CS7, read signal R2X, and write signal W2X) are appropriately omitted. May be.

Further, depending on the system configuration, it is possible to use only the wait signal WAIT without using the second access signal. Further, the period of the actual access operation can be extended and the power consumption can be reduced by merely performing dummy access to the dummy device periodically without using the second access signal and the wait signal WAIT. . It is also possible to extend the cycle of the actual access operation only by software processing.
Furthermore, if the device is controlled by the central processing unit,
It is also possible to apply to a device other than the printing device.

[0042]

As described above, according to the present invention,
A power down control device mounted on a device having at least two operation modes of a normal operation mode and a low power operation mode, wherein an actual access operation to an accessed device based on an access request signal generated in the low power operation mode Is provided, the number of accesses per unit time and the access operation time are reduced, and power consumption can be reduced without putting the central processing unit to sleep.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a power down control device according to the present invention.

FIG. 2 is a perspective view showing a schematic configuration of a main part of a printer to which the power-down control device according to the present invention is applied.

FIG. 3 is a block diagram illustrating a configuration of an access delay control unit in FIG. 1;

FIG. 4 is a timing chart showing the operation of the power down control device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Tecoder, 3 ... Access delay control part,
4 ROM, 5 RAM, 6 motor control unit, 7 DM
A control unit, 8 ... I / F control unit, 9 ... Head control unit, 10
... Address decoder, 11 ... NAND gate, 12 ... O
R gate, 21 timer, 22 to 25 delay pulse generator, 27 to 30 flip-flop, 31 AND
Gates, 32-35 NAND gates, 36 selectors, 37 mode registers, 38 inverters, 54
Print head.

Claims (24)

[Claims] 1. A power down control device mounted on a device having at least two operation modes of a normal operation mode and a low power operation mode, wherein the access target device is based on an access request signal generated in the low power operation mode. A power down control device, comprising: a decompression means for decompressing a cycle of an actual access operation to the power down control. 2. The power-down control device according to claim 1, wherein the expansion unit includes a timer unit that counts a delay time for delaying the access request signal and outputting the access request signal to the accessed device. 3. The decompressing unit until the processing of the accessed device corresponding to the access request signal ends.
2. The power-down control device according to claim 1, further comprising a wait unit that waits for the end of the current access. 4. The decompression means for measuring the delay time for delaying the access request signal and outputting it to the accessed device, and the processing of the accessed device corresponding to the access request signal ends. 2. The power-down control device according to claim 1, further comprising a wait unit that waits until the end of the current access. 5. The decompressing means decompresses a mapped address of an unmounted device to extend a period of an actual access operation to the accessed device based on an access request signal. The power down control device according to claim 1. 6. The power-down control device according to claim 1, wherein said expansion means expands a cycle of an actual access operation based on an access request signal generated from a central processing unit. 7. The power-down control according to claim 1, wherein said expansion means extends the cycle of an actual access operation based on an access request signal generated from a direct memory access control unit. apparatus. 8. The power down control device according to claim 1, wherein the power control device is mounted on a printing device. 9. A power down control method applied to a device having at least two operation modes of a normal operation mode and a low power operation mode, wherein the accessed device is based on an access request signal generated in the low power operation mode. A power down control method, comprising: a decompression step of decompressing a period of an actual access operation to the power supply. 10. The method according to claim 9, wherein the decompressing step includes a time measuring step of measuring a delay time for delaying the access request signal and outputting the access request signal to the accessed device.
The described power down control method. 11. The decompression step according to claim 9, wherein the decompression step includes a wait step of waiting for the end of the current access until the processing of the accessed device corresponding to the access request signal ends. Power down control method. 12. The decompression step completes a timing step of timing a delay time for delaying the access request signal and outputting the access request signal to the accessed device, and a process of the accessed device corresponding to the access request signal. 10. The power-down control method according to claim 9, further comprising a wait step of waiting for the end of the current access until the end of the current access. 13. The decompressing step decompresses a mapped address of an unmounted device to extend a period of an actual access operation to an accessed device based on an access request signal. The power down control method according to claim 9. 14. The method according to claim 9, wherein said expanding step expands a cycle of an actual access operation based on an access request signal generated from a central processing unit.
3. The power down control method according to 3. 15. The power-down control according to claim 9, wherein said expanding step extends the cycle of an actual access operation based on an access request signal generated from a direct memory access control unit. Method. 16. The power down control method according to claim 9, wherein said power control method is applied to a printing apparatus. 17. A storage medium storing a program to be executed in a device having at least two operation modes of a normal operation mode and a low power operation mode, wherein the program is generated in the low power operation mode. And a decompression routine for decompressing a period of an actual access operation to the accessed device based on the access request signal. 18. The storage medium according to claim 17, wherein said decompression routine includes a timing routine for timing a delay time for delaying said access request signal and outputting it to the accessed device. 19. The decompression routine according to claim 17, wherein the decompression routine includes a wait routine that waits for the end of the current access until the processing of the accessed device corresponding to the access request signal ends. Storage medium. 20. The decompression routine terminates a timing routine for delaying the access request signal and outputting a delay time to the accessed device, and a process of the accessed device corresponding to the access request signal. Until,
18. The storage medium according to claim 17, further comprising a wait routine for waiting for the end of the current access. 21. The decompression routine decompresses a mapped address of a device which is not mounted and extends a period of an actual access operation to the accessed device based on an access request signal. The storage medium according to claim 17. 22. The storage medium according to claim 17, wherein said decompression routine extends the period of an actual access operation based on an access request signal generated from a central processing unit. 23. The storage medium according to claim 17, wherein said decompression routine extends the cycle of an actual access operation based on an access request signal generated from a direct memory access control unit. 24. The power control device according to claim 17, wherein the power control device is mounted on a printing device.
The storage medium according to the above.