JP2000125271A - Video signal multiplexer, multiplexed video signal decoding device and video signal multiplex transmitter having them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a video signal multiplexer which multiplexes a video signal in the form of plural formats with a simple circuit by having a means which performs time multiplexing of plural digital video signals in which a synchronizing signal identifying respective digital video signals is inserted into every horizontally synchronous period. SOLUTION: This device has a means which inserts a synchronizing signal that is used by a serial transmission system and identifies respective digital signals at a timing reference signal part in one horizontally synchronous period of respective digital video signals and a means which performs time multiplexing of plural digital video signals in which a synchronizing signal identifying respective digital video signals is inserted into every horizontally synchronous period, etc. The data converting part of this device has a 1st video signal switching circuit 12A of a transmission system to which a 1st luminance signal EY1 constituting a 1st 8-bit video signal is inputted and a 2nd video signal switching circuit 14A of the transmission system. It also has 1st and 2nd video signal memories 16A and 18A of the transmission system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data multiplex transmission apparatus, and more particularly to a video signal multiplex transmission apparatus. More specifically, the present invention provides a video signal multiplexing device for multiplexing video signals (video signals) in a plurality of formats, a multiplexed video signal decoding device for decoding a multiplexed video signal, and an integration of these devices. The present invention relates to a video signal multiplex transmission device. More specifically, the present invention uses relatively simple circuitry,
The present invention relates to a video signal multiplexing device that multiplexes video signals (video signals) in a plurality of formats, a multiplexed video signal decoding device that decodes a multiplexed video signal, and a video signal multiplex transmission device that integrates these devices.

[0002]

2. Description of the Related Art Techniques related to a data multiplex transmission apparatus will be described. As a data transmission device and a data transmission method of a digital data signal representing various kinds of signal information, a method of transmitting serial data as an electric signal using a coaxial cable or a twisted pair wire (twisted wire), or a method of transmitting serial data into an optical signal Various methods have been attempted, for example, to convert the data into an optical fiber and transmit it using an optical fiber.

A video signal multiplex transmission device will be described as an example of a data multiplex transmission device. As an example of digital data, a plurality of digital video (video) signals such as a D1 system, a D2 system, an HDTV system, and other information signals,
There is a demand for efficient multiplex transmission.

[0004]

At present, D1 system, D2 system
In order to multiplex a plurality of digital video (video) signals such as the HDTV system and other information signals and transmit them serially, parallel / serial (P / S) conversion and vice versa serial / parallel (S / P) Conversion is required.
However, a P / S conversion circuit, preferably a P / S conversion integrated circuit (IC) and an S / P conversion circuit, preferably an integrated circuit, capable of multiplexing and serially transmitting such a plurality of video signals. Circuitized S / P conversion IC
So far, a low-cost circuit with a simple circuit configuration has not been proposed. If a dedicated P / S conversion IC and S / P conversion IC for multiplexing a plurality of digital video signals of the D1, D2, and HDTV systems are independently developed, it takes a lot of time, labor, and cost.

[0005] Serial transmission standards for transmitting digital video (video) signals of the D1, D2, and HDTV systems, for example, SMPTE259M and BTA S-
The scrambling method specified in 004A outputs a serial signal whose mark ratio varies widely from 1/20 to 19/20 with respect to a certain kind of flat field signal input. 2 for some flat field signal inputs
Since a serial signal that repeats digital data of 0 bit high (high) and 20 bit low (low) is output, such a wide mark fluctuation occurs when DC reception is performed on the receiving side that receives a multiplexed serially transmitted signal. To cope with the rate, the circuit on the receiving side becomes complicated, and the circuit load on the receiving side is large. In particular, there is a problem that the jitter is accumulated in the reproduced clock when a reproduction circuit for reproducing the clock is connected in multiple stages on the receiving side.

Accordingly, it is an object of the present invention to provide a video signal multiplexing apparatus for multiplexing video signals of a plurality of formats by a relatively simple circuit using existing circuits and systems, and a multiplexing apparatus. It is an object of the present invention to provide a multiplexed video signal decoding device for decoding a video signal, and a video signal multiplex transmission device in which these devices are integrated via a serial transmission system.

[0007]

According to a first aspect of the present invention, a plurality of digital video signals each having a predetermined first number of bits are multiplexed with a video signal having a predetermined second number of bits to continuously multiplex them. A video signal multiplexing transmission device for transmitting to a serial transmission system, a synchronization signal used in the serial transmission system for a timing reference signal portion in one horizontal synchronization period of each of the digital video signals. Synchronization signal insertion means for inserting a synchronization signal for identifying a video signal; multiplexing means for time-multiplexing the plurality of digital video signals into which the synchronization signal has been inserted for each horizontal synchronization period; Bit conversion means for converting the video signal into parallel video signals of the second number of bits for each predetermined bit; Video signal multiplexing apparatus and a parallel / serial converting means for converting a video signal in a format is provided.

The digital video signal is a luminance signal,
It is a composite signal having color difference signals and information related thereto.

[0009] The serial transmission system includes a fiber channel and a gigabit Ethernet, and the synchronization signal included in the multiplexed video signal is a synchronization signal of the fiber channel and the gigabit Ethernet. Alternatively, the serial transmission system includes an asynchronous network, and the synchronization signal included in the multiplexed video signal is a synchronization signal of the asynchronous network. Further, the synchronization signal is made different so that a plurality of video signals can be identified on the receiving side, and the synchronization signal is made different so that, for example, a luminance signal and a color difference signal can be identified.

In the above-mentioned video signal multiplexing apparatus, for example, a D1 system, a D2 system, a high-definition television (HDT)
V) system or a plurality of 8-bit quantized digital video signals (digital video signals), for example, a composite video signal in which a luminance signal and a color difference signal are combined, or a luminance signal, a color difference signal, and green, blue, and red (GBR) A component video signal composed of a video signal and other information signals related to video signal processing are converted into a timing reference signal for one horizontal period of these video signals, for example, a SAV (Startof Active
Video), "FF (hexadecimal notation: the same applies hereinafter)", "00", "00", for example, 8B (bit)-
The word is replaced with three words including [K28.5], which is a 10B (bit) word synchronization signal, and a word including the word synchronization signal [K28.5] is added to the head of the other information signals, thereby providing one horizontal period. Digital video signals and other information signals are multiplexed by switching over in time.
By performing the B-10B conversion, a parallel / serial (P / P) signal is output using a network signal processing integrated circuit (IC) using an 8B-10B code such as a fiber channel or a gigabit Ethernet (Gigabit Ethernet).
S) Convert and send to serial transmission system such as Fiber Channel.

According to a second aspect of the present invention, there is provided a multiplexed video signal decoding apparatus for decoding a multiplexed video signal transmitted from the above-described video signal multiplexing apparatus and transmitted through a serial transmission system. You. That is, according to the present invention, a multiplexed digital video signal, which is transmitted through a serial transmission system and is multiplexed with a plurality of digital video signals each having a predetermined second bit number, is received to restore the multiplexed digital video signal A multiplexed video signal decoding device for decoding a digital video signal having a first predetermined number of bits, wherein the multiplexed video signal is included in a serial format multiplexed digital video signal transmitted through the serial transmission system. Synchronism detecting means for detecting a synchronizing signal present and outputting a synchronizing detection pulse; clock reproducing means for reproducing a clock based on the synchronizing detection signal; Horizontal synchronizing signal generating means for generating a horizontal synchronizing signal; and generating a horizontal synchronizing signal based on the type of the synchronizing signal. Data separation timing signal generating means for generating a data separation timing signal for identifying another; serial / parallel conversion for converting the synchronously detected multiplexed digital video signal of the first bit number of the serial format into a parallel format Means; bit conversion means for bit-converting the multiplexed video signal of the first number of bits converted into the parallel format by the serial / parallel conversion means to the video signal of the second number of bits; Signal separating means for separating the converted parallel video signal into original digital video signals and other information related to the video signals based on the data separation timing signal; and Multiplexing the digital video signal into the horizontal synchronization signal and the Demultiplexing means for demultiplexing based on the generated clock; and demultiplexing the serial transmission system synchronization signal included in the video signal demultiplexed by the demultiplexing means into the original video signal. A multiplexed video signal decoding device comprising: a synchronization signal replacement unit that replaces a synchronization signal.

The multiplexed video signal decoder serial / parallel (S / P) conversion means converts the received synchronization signal [K28.
5], word synchronization is performed, and a synchronization detection signal is output. A hardware circuit detects the word including the word sync signal [K28.5] replaced by the sync detection signal and the video signal multiplexing device, thereby separating the time-multiplexed video signal and information signal. Is demultiplexed and the original digital video signal is decoded. The multiplexed video signal decoding apparatus identifies a plurality of video signals according to the type of the synchronization signal, and further identifies, for example, a luminance signal or a color difference signal according to the type of the synchronization signal.

According to a third aspect of the present invention, there is provided a video signal multiplex transmission apparatus including the above-described video signal multiplexing apparatus and multiplexed video signal decoding apparatus.

According to a fourth aspect of the present invention, a plurality of digital video signals each having a predetermined first number of bits are multiplexed and transmitted to a serial transmission system as a video signal having a predetermined second number of bits. Video signal multiplexing device,
Synchronizing signal inserting means for inserting a synchronizing signal used in the serial transmission system into a timing reference signal portion of one horizontal synchronizing period of each of a plurality of digital video signals; Multiplexing means for generating a multiplexed video signal; time axis multiplexing means for respectively multiplexing the plurality of multiplexed video signals on a time axis;
Bit conversion means for converting the number of bits of the time-division multiplexed video signal of the first bit number into the second bit number for each predetermined bit; and the bit-converted multiplexed parallel format video image There is provided a video signal multiplexing apparatus having a parallel / serial conversion means for converting a signal into a video signal of a serial format.

In the above-mentioned video signal multiplexing apparatus, a plurality of 10-bit quantized digital video signals (luminance signal, color difference signal or GBR signal) such as D1, D2 and HDTV and other information signals are converted into one of these video signals. The first three words, 3FF, 000000, and the lower two bits 00 of the fourth word of the timing reference signal SAV in the horizontal period are used as word synchronization signals of 8B-10B, for example, fiber channel [K28. 5], and a word including a word synchronizing signal [K28.5] is added to the beginning of the other information signals, and the digital video signal and the information signal in one horizontal period are temporally switched. Multiplexing and further 8B-10B conversion to use 8B-10B codes applied to fiber channels and the like. With compatible integrated circuits to the serial transmission system such as Fiber Channel, P / S
Convert and send to serial transmission system.

According to a fifth aspect of the present invention, there is provided a multiplexed video signal decoding device for receiving and decoding a multiplexed video signal transmitted from the video signal multiplexing device. That is, according to the present invention, a multiplexed video signal that receives a multiplexed digital video signal of a first number of bits and decodes it into an original digital video signal of a second number of bits transmitted through a serial transmission system A synchronization detection means for detecting a synchronization signal included in a multiplexed digital video signal of a serial format transmitted through the serial transmission system and outputting a synchronization detection pulse; Clock reproducing means for reproducing a clock based on the clock; horizontal synchronizing signal generating means for generating a horizontal synchronizing signal for a video signal to be restored from the reproduced clock;
Data separation timing signal generation means for generating a data separation timing signal in accordance with the content of the video signal based on the content of the synchronization signal; and a multiplexed digital signal of the first bit number of the serial format detected in synchronization. Serial / converts video signals to parallel format
Parallel conversion means; bit conversion means for bit-converting the multiplexed video signal of the first number of bits converted into the parallel format by the serial / parallel conversion means into the video signal of the second number of bits; A plurality of video signals based on the data separation timing signal,
Signal demultiplexing means for demultiplexing the video signal into other information related to the video signal; demultiplexing means for demultiplexing the separated video signal based on the horizontal synchronization signal and the reproduced clock; A multiplexed video signal decoding device comprising: a synchronization signal replacement unit that replaces the serial transmission system synchronization signal included in the video signal demultiplexed by the demultiplexing unit with a synchronization signal of an original video signal. Is done.

In the above multiplexed video signal decoding apparatus, the serial / parallel (S / P) conversion means detects a synchronizing signal, for example, [K28.5] from the received multiplexed video signal and synchronizes the word, thereby obtaining word synchronization. Outputs a synchronization detection signal. By detecting the synchronization detection signal and the synchronization signal replaced by the video signal multiplexing device, for example, a word containing [K28.5] by a hardware circuit, the video signal and the information signal to be time-multiplexed are separated. Decoding is performed for each separated video signal.

According to a sixth aspect of the present invention, there is provided a video signal multiplex transmission apparatus in which the video signal multiplexing apparatus and the multiplexed video signal decoding apparatus are connected with respect to a serial transmission system.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a preferred embodiment of the present invention, a format of a digital video signal (digital video signal) applied in the embodiment of the present invention will be described with reference to FIGS. And FIG. FIGS. 1A and 1B show a digital luminance signal Ey and color difference signals Ecb, Ecr (Digital Video Signal) constituting a D1 system, a D2 system, a high definition television (HDTV) system or the like. FIG. 3 is a diagram illustrating formats of a first digital color difference signal Ecb and a first digital color difference signal Ecr).

The symbols in FIG. 1A are shown in Table 1, and the meanings of the symbols in FIG. 1B are shown in Table 2.

[0021]

Table 1: Meanings of symbols in FIG. 1A SAV (Start of Active Video): Start timing reference code of digital luminance signal YD0 to YD1919: Digital luminance signal Ey YA0 to YA267: In digital luminance signal Ey stream Ancillary data or blanking data YCR0, YCR1: Synchronization error detection code LN0, LN1: Line number data EAV (End of Active Video): End timing reference code of digital luminance signal

[0022]

Table 2: Meanings of symbols in FIG. 1 (B) SAV (Start of Active Video): Start timing reference code of digital color difference signal CBD0 to CBD959: First digital color difference signal E
cb CRD0 to CRD959: second digital color difference signal E
cr CA0CA267: first digital color difference signal Ecb1
/ Ancillary data or blanking data in second digital color difference signal Ecr1 CCR0, CCR1: Synchronization error detection code LN0, LN1: Line number data EAV (End of Active Video): End timing reference code of digital color difference signal

In this example, the SAV is 4T long, the luminance signal and the color difference signal as active lines are each 1920T long, the ancillary data or blanking data is 268T long, and the synchronization error detection code is 2T long. Length, line number is 2T length, EAV
Is the length of 4T, the length between SAV and EAV is 280T as digital line blanking, and the length of all data in the horizontal direction is 2200T. FIG. 1 (A),
Illustrated that illustrated in (B) is, T = 1 / 74.25MH _Z =
13.468 ns, and Ts = T / 2. When the digital video signal described above is transmitted as bit serial data, the LSB of each word is transmitted first.

As illustrated in FIGS. 1A and 1B, D
Digital video data of the 1 system, the D2 system, the HDTV system, etc. starts with 4 words at the beginning of the first video signal (for example, digital luminance signal Ey / digital color difference signal Ecb, Ecr) in each horizontal synchronization period (each line). The timing reference code SAV is placed, and at the end of the last video signal (for example, digital luminance signal Ey / digital chrominance signal Ecb, Ecr) of the last horizontal synchronization period, a 4-word end timing reference code EAV is provided.
Is placed.

FIGS. 1A and 1B show an example of a digital video signal of a 10-bit system. Therefore, a 4-word start timing reference code SAV is a 10-bit 4-word "3FF (hexadecimal number)". Notation, the same applies hereinafter) ",
It consists of “000”, “000”, and “XYZ”. The SAV for an 8-bit digital video signal is "F
F (each digit is in hexadecimal notation, the same applies hereinafter) "," 00 ",
"00" and "XY". EAV, which is a 4-word end timing reference code, is a 4-word “3FF” or “00” in the case of a 10-bit digital video signal.
The EAV of the digital video signal in the case of the 8-bit system consists of four words "FF", "00", "00", and "XY".

Of the four words in each of the above-described SAV and EAV, the first three words, for example, "3FF", "000", and "00" in the case of a 10-bit system.
"0" is a word synchronization signal used to establish word synchronization. The last one word is, for example, "XYZ" in the case of a 10-bit system is a selection of the first field in the same frame, in other words, a frame. Of the first field, and identification of the second and subsequent fields, SAV and EAV
It is for identifying.

Fiber Channel, Gigabit Ethernet, IEEE currently under consideration
In E1394 and the like, on the transmission side of digital data (not necessarily a data video signal), when transmitting a serial signal, serial digital data is converted into 10-bit parallel data every 8 bits, that is, "8 Bit (8B)-10 bit (10B) conversion "
To obtain a 10-bit parallel signal, and then perform a parallel-serial conversion (P / S conversion) to transmit the serial data stream to a receiving side via a serial transmission system such as a fiber channel.

FIG. 2 shows a digital luminance signal Ey obtained by multiplexing the digital video signals illustrated in FIGS. 1A and 1B and performing parallel / serial conversion, and first and second digital color difference signals Ecb. , Ecr and the transmission order are illustrated. The meanings of the symbols in FIG. 2 are the same as those illustrated in Tables 1 and 2. As is clear from the illustration of FIG. 2, the digital color difference signal Ec
b / Ecr and the digital luminance signal Ey are alternately continuous.

Ecb0 (CBD0) / Ey0 (YD
0), Ecr0 (CRD0) / Ey1 (YD1),.
・ ・

Similarly, the SAV for the luminance signal Ey, the SAV for the color difference signals Ecb and Ecr, ancillary data or blanking data, the synchronization error detection code, the line number data, and the EAV are alternately continuous. In this specification, these data may be collectively referred to as other related information (signal) for the luminance signal and the color difference signal. As a result of multiplexing in this manner, all digital lines in one horizontal period have two luminance signals and two color difference signals.
4400T.

The word synchronization signal will be described below word synchronization signal. 1. Necessity of Word Synchronization Signal When a serial transmission system such as a fiber channel is used, the receiving side that receives multiplexed transmission data converts the received serial data into 8 bits for every 10 bits. 8B conversion "to reproduce (decode) the digital video signal on the transmission side. When 10B-8B conversion is performed on the receiving side, word synchronization is necessary to accurately separate serial data every 10 bits (or 20 bits), and the transmitting side inserts this word synchronization signal as appropriate and transmits. .

2. Position of Word Synchronization Signal In the present embodiment, the word synchronization signal
As illustrated in (A) and (B), the digital luminance signal and the digital chrominance signal are respectively placed in the SAV. 1
In the case of a 0-bit digital video signal, three words, "3FF", "000", "00"
The position where the lower two bits of the 0th word and the fourth word are placed is a portion where the word synchronization signal is inserted. In the case of an 8-bit digital video signal, three words "FF" and "0" are used.
The positions where “0” and “00” are placed are portions where the word synchronization signal is inserted.

3. Word Synchronization Signal Contents Word synchronization data for transmission using a fiber channel or the like includes the above-mentioned “3FF”, “000”,
Instead of "000" or "FF", "00", "00", Fiber Channel standards, such as ANSI
X3.230-1994 is a code which is a word synchronization signal specified in 1994, typically K28.5, specifically, [K28.5, K28.5, K28.5] or [K28.5 , K28.5, K2
8.5, K28.5]. Therefore, when using a serial transmission system such as a fiber channel, it is necessary to use a word synchronization signal conforming to the standard of such a transmission system. In the present invention, when transmitting a multiplexed digital video signal using a serial transmission system such as a fiber channel, a word synchronization signal [K28.5, K28.5, K28.5 ] Or [K28.5,
K28.5, K28.5, K28.5] in the timing reference signal insertion portion, in this example, in the SAV portion, in the case of the above-mentioned 10-bit video signal, "3FF", "000", "000" or 8 bits "FF", "00", "0"
Insert "0" instead.

4. Types of Word Synchronization Signals 4.1 Identification of First Video Signal (Video Signal) and Second Video Signal (Video Signal) In the present invention, a word synchronization signal is divided into a first video signal and a second video signal. When restored and different, the difference between the original video signals is identified by the difference between the word synchronization signals.

4.2 Identification of Types of Multiplexed Video Signals Video signals can be generally classified into composite signals and component signals. As the composite signal, for example, a luminance signal, a color difference signal, and information related thereto (in the example described with reference to FIGS. 1A and 1B, SA
V, ancillary data or blanking data, synchronization error detection code, line number data, information such as EAV). The color difference signal is usually the first color difference signal Ecb.
And the second color difference signal Ecr. As component signals, for example, R (red), G (green), B (blue)
And information related to them. In the video signal multiplex transmission of the present invention, for example,
This is a composite signal and may be mixed when multiplexed as the second video signal, for example, as a component signal. When these video signals are multiplexed and transmitted through a serial transmission system, upon decoding on the receiving side, identification of a luminance signal and a chrominance signal, or R, G, B
Need to be identified. Therefore, in the present invention, for example, when a composite signal is multiplexed and transmitted, a word synchronization signal capable of distinguishing a luminance signal and a color difference signal is added at the time of multiplexing. In the present embodiment, as described later, for identification of the luminance signal Ey, [D21.4] is used as a representative code, specifically, [D21.4, D21.4,
D21.4) or (D21.4, D21.4, D21.4, D21.4),
To identify the color difference signals Ecb and Ecr, [K28.5] is used as a representative code, specifically, [K28.5, K28.5, K28.
5] or [K28.5, K28.5, K28.5, K28.5].

4.3 Identification of Other Information In the present invention, the luminance signal Ey and the color difference signals Ecb, Ec
When transmitting other information in addition to r, a code for identifying other information, for example, [K28.5, D20.4] is used.

The word synchronous data is a word having a 10-bit structure in the case of a 10-bit system, but has a specific code which is not used as a word having a 10-bit structure when information is transmitted. This is a word that does not appear at a 10-bit boundary over any two words when a 10-bit word for transmission is serially transmitted.

FIG. 3A shows that the transmitting side converts parallel data into serial data in synchronization with the read clock REFCLK, and the receiving side reproduces the reproduction clock RC.
FIG. 9 is a diagram illustrating an operation of converting serial data into parallel data in synchronization with LK. FIG. 3B is a diagram illustrating first data (byte) in the 20-bit mode and second data (byte) in the 10-bit mode. In the embodiment of the present invention, a video signal is multiplexed and transmitted on the transmitting side and decoded on the receiving side by the method illustrated in FIGS. 3A and 3B.

When a transmission path such as a fiber channel is used, the receiving side that receives the multiplexed transmission data performs 10B-8B conversion. 8B-10 used in serial transmission systems such as Fiber Channel
Each of the 10-bit words in the 10-bit word string data after the B conversion has 10 bits of which the number of “1” is larger than the number of “0” and the number of “0” is “1” among the 10 bits constituting the word. , Or the number of “1” is equal to the number of “0”. In representing the states of the respective numbers “1” and “0”, for example, running disparity (RD)
The idea is introduced. When the number of “1” is larger than the number of “0”, it is said that the running disparity RD is positive. When the number of “0” is larger than the number of “1”, the running disparity RD is negative. That is, when the number of "1" is equal to the number of "0", it is said that the running disparity RD is neutral (neutral). Word data in which the number of "1" s is larger than "0" is word data having a positive running disparity RD, and word data in which the number of "0s" is larger than "1" is running disparity. Word data having a negative RD and word data having the number of “1” equal to the number of “0” are referred to as word data (neutral word data) having the running disparity RD as neutral.

With the basics described above as background, an embodiment of the video signal multiplex transmission apparatus of the present invention will be described below. As an embodiment of the video signal transmission device of the present invention,
Composite transmission for transmitting digital video signals and other information signals via one transmission line (serial transmission system) will be described. As a composite video signal,
The luminance signal and the color difference signal illustrated in FIGS.
Examples of SAV, ancillary data or blanking data, synchronization error detection code, line number data, and EAV as other related information will be described. Fiber Channel as a serial transmission system
Will be exemplified.

Video signal multiplex transmission apparatus according to first embodiment A video signal transmission apparatus according to a first embodiment of the present invention includes an 8-bit quantized digital video signal such as a D1 system and a D2 system and other information signals. Multiplexed, converted using a fiber channel having 20-bit input / output means, a parallel / serial (P / S) conversion circuit, and a serial / parallel (S / P) conversion circuit, and transmitted to the fiber channel. A signal multiplexing apparatus and a multiplexed video signal decoding apparatus that receives and decodes a multiplexed video signal transmitted through a fiber channel transmission path will be described.

FIGS. 4 to 12 show the configuration of a video signal multiplex transmission apparatus according to a first embodiment of the present invention. The video signal multiplex transmission apparatus according to the first embodiment of the present invention includes one transmission path (composite transmission path) for transmitting a digital video signal.
4 to 8 through a channel transmission path (not shown).
The transmission system (video signal multiplexing device) illustrated in FIG.
The receiving system (multiplexed video signal decoding device) illustrated in FIG. 12 is connected and configured.

Video Signal Multiplexing Apparatus According to First Embodiment Referring to FIGS. 4 to 8, the transmission system of a video signal multiplexing transmission apparatus according to a first embodiment of the present invention, that is, a video signal multiplexing apparatus. Is described. The video signal multiplexing device according to the first embodiment is roughly divided into a data conversion unit and a data multiplexing / transmission unit. FIGS. 4 and 5 are circuit diagrams of the converter of the video signal multiplexing device. This video signal multiplexing device is divided into a first video (video) signal processing illustrated in FIG. 4 and a second video (video) signal processing illustrated in FIG. FIG. 6 is a circuit diagram of a multiplexing / transmission unit of the video signal multiplexing transmission device of the present invention. A circuit combining the circuits illustrated in FIGS. 4 and 5 and the circuit illustrated in FIG. 6 (or the circuit illustrated in FIG. 5 and the circuit illustrated in FIG. 6) is a video signal multiplexing apparatus according to an embodiment of the present invention. That is, the circuit of FIG. 4 and the circuit of FIG. 5 perform the conversion processing of the luminance signal Ey and the color difference signals Ecb and Ecr, and perform the multiplexing and transmission processing of the data converted by the circuit illustrated in FIG.

The circuit configuration of the video signal multiplexing device illustrated in FIGS. 4 and 5 will be described. The data conversion unit of the video signal multiplexing device illustrated in FIG. 4 that performs the multiplexing process of the first video signal includes a transmission system to which a first luminance signal Ey1 constituting an 8-bit first video signal is input. A first video signal switching circuit 12A, a transmission-system second video signal switching circuit 14A, a transmission-system first video signal memory 16A,
It has a second video signal memory 18A for the transmission system and a third video signal switching circuit 20A for the transmission system. The data converter of the video signal multiplexing transmission apparatus illustrated in FIG.
A first color difference signal Ec constituting a first video signal of bits
b1 and Ecr1 are input, the first video signal switching circuit 22A of the transmission system, the second video signal switching circuit 24A of the transmission system, the first video signal memory 26A of the transmission system, the second video signal of the transmission system It has a memory 28A and a third video signal switching circuit 30A of the transmission system.

The data converter of the video signal multiplexing device illustrated in FIG. 5 is configured to receive the first luminance signal Ey2 constituting the second digital video signal of 8 bits.
Video signal switching circuit 12B, transmission-system second video signal switching circuit 14B, transmission-system first video signal memory 16B, transmission-system second video signal memory 18B, and transmission-system third video signal switching It has a circuit 20B. The data converter of the video signal multiplexing transmission device illustrated in FIG. 5 also includes a first video signal of a transmission system to which the second color difference signals Ecb2 and Ecr2 constituting the 8-bit second digital video signal are input. The switching circuit 22B, the transmission-system second video signal switching circuit 24B, the transmission-system first video signal memory 26B, the transmission-system second video signal memory 28B, and the transmission-system third video signal switching circuit 30B Have.

The circuit configuration of the video signal multiplexing device illustrated in FIG. 6 will be described. The multiplexing / transmission portion of the video signal multiplexing device illustrated in FIG. 6 includes a transmission-system common signal switching circuit (multiplexing processing circuit) 32 and a transmission-system 8-bit-10-bit conversion unit (8B-10B conversion unit). 36, transmission system parallel /
It has a serial converter (P / S converter) 40.

The multiplexing / transmission portion of the video signal multiplexer shown in FIG. 6 further includes a time multiplexing timing signal generator 34, a read clock generator 38, a horizontal synchronizing signal generator 42 and a word clock generator 44. .
It should be noted that these circuits are only illustrated in FIG. 6 for the sake of illustration, and they can be arranged at any part of the video signal multiplexing transmission apparatus. It is supplied to a predetermined circuit of the device.

For easy understanding, the following table shows examples of synchronous signals to be replaced (switched) based on the serial transmission system in the present invention.

[0049]

Table 6 Contents of the present invention First synchronization signal illustrated in FIGS. 4 to 6 First synchronization signal for luminance signal Input to first video signal switching circuit 12A [D21.4, D21.4 , D21.4] First chrominance signal synchronization signal [K28.5, K28.5, K28.5] input to first chrominance signal switching circuit 22A Second synchronization signal Second luminance signal synchronization Signal [D21.4, D21.4, D21.4] Input to the second luminance signal switching circuit 12B [Second color difference signal synchronization signal] Input to the second color difference signal switching circuit 22B [K28.5 , K28.5, D21.4)

The word synchronization signal will be described. In order to distinguish the multiplexed luminance signal Ey from the chrominance signals Ecb and Ecr, the first luminance signal switching circuit 12A supplies a word synchronization signal [D21.4, D21.4, D2] in the fiber channel.
1.4] to switch (replace) the three word synchronizing signal of the SAV of the luminance signal Ey, and the word synchronizing signal [K28.5, K28.5 in the fiber channel is supplied to the first color difference signal switching circuit 22A. , K28.5] to switch (replace) the three-word synchronizing signal of the SAV of the color difference signals Ecb and Ecr. On the receiving side, these word synchronization signals [D21.4, D21.4, D21.4
] And [K28.5, K28.5, K28.5], the luminance signal Ey and the color difference signals Ecb, Ecr can be identified from the multiplexed video signal. Of course, as described above, SAV “X
Using Y ", the luminance signal Ey and the color difference signals Ecb, Ecr
Can be identified. Further, the first color difference signal processing first
The word synchronization signal input to the color difference signal switching circuit 22A is [K28.5, K28.5, K28.5], and the word synchronization signal input to the second color difference signal switching circuit 22B is [K28.
5, K28.5, D21.4], so that the first video signal or the second video signal can be identified from the difference between these word synchronization signals detected on the receiving side. .

Although the circuit configuration of FIG. 4 is similar to the circuit configuration of FIG. 5, the video signal multiplexing device of FIG. 4 uses the luminance signal Ey1 and the color difference signal Ec of the first video signal (video signal).
Since b1 and Ecr1 are converted, the luminance signal Ey1 and the color difference signals Ecb1 and Ecr1 of the first video signal are input, and the circuit of the video signal multiplexing device receives the first word clock CLK1 and the first horizontal synchronization signal H1. Driven by 5 converts the luminance signal Ey2 and the color difference signals Ecb2 and Ecr1 of the second video signal, so that the luminance signal Ey2 and the color difference signals Ecb2 and Ecr2 of the second video signal are input and the video signal The circuit of the multiplexer comprises a second word clock CLK2 and a second word clock CLK2.
Is driven by the horizontal synchronization signal H2. The read clock REFCLK and the time multiplex timing pulse are common to both.

Before describing the operation of the circuits of FIGS. 4 to 6, the conditions or states of the signals shown in FIGS. 4 to 6 will be described with reference to FIGS. The word clock CLK generated from the word clock generation circuit 44 includes the first
Word clock CLK1 and second word clock CL
K2 exists. The first word clock CLK1 is
It is activated while the SAV of the first digital luminance signal Ey1 and the SAV of the first digital color difference signals Ecb1 and Ecr1 exist. First word clock CLK
1 is a first digital video signal (a first digital luminance signal Ey1 and a first digital color difference signal Ecb).
1, Ecr1). The second word clock CLK2 is activated while the second digital luminance signal Ey2 and the second digital color difference signals Ecb2, Ecr2 are present. Second word clock CL
K2 is a second digital video signal (a second digital luminance signal Ey2 and a second digital color difference signal Ec).
b2, Ecr2).

The horizontal synchronization signal H includes a first horizontal synchronization signal H1 and a second horizontal synchronization signal H2. The horizontal synchronizing signal generation circuit 42 generates a first horizontal synchronizing signal H1 in response to the first word clock CLK1 and the second word clock CLK2 generated from the word clock generating circuit 44.
And the second horizontal synchronizing signal H2. The first horizontal synchronizing signal H1 is a horizontal synchronizing signal used for processing the first digital video signal, and includes the SAV of the 8-bit digital luminance signal Ey1 and the digital color difference signal Ecb.
1, a synchronous timing pulse that is activated during the period when the SAV of Ecr1 exists. Second horizontal synchronization signal H2
Is a horizontal synchronization signal used for processing the second digital video signal, and is a synchronization timing pulse activated when the second luminance signal Ey2 and the second color difference signals Ecb2 and Ecr2 are present.

The time multiplex timing signal generator 34 includes first and second horizontal synchronizing signals H1 and H2 from the horizontal synchronizing signal generator 42 and first and second word clocks CLK1 and CLK2 from the word clock generator 44.
Generates a time multiplex timing pulse TMUX for multiplexing two digital video signals based on The time multiplex timing pulse TMUX is activated during a period in which the luminance signal Ey and the color difference signals Ecb and Ecr are present in order to multiplex these signals.

As described with reference to FIG. 3, the read clock generation unit 38 provides a parallel / serial conversion unit (P /
A read clock REFCLK for use in conversion of parallel data and serial data in the S conversion section 40 and for reading data from the luminance signal memories 16 and 18 and the color difference signal memories 26 and 28 is generated.

Processing of First Digital Video Signal The operation of processing the first digital video signal in the video signal multiplexing apparatus will be described with reference to the circuits shown in FIGS. FIG. 7 is a diagram showing a state of a converted signal in a converting unit in the video signal multiplexing device illustrated in FIG.

The first luminance signal switching circuit 12A of FIG.
In the first digital luminance signal Ey1, the SAV original synchronization three words "FF", "00", "00" and the word synchronization signal for the luminance signal in the fiber channel [D24.1, D24.1, D24 .1] to the first horizontal synchronizing signal H
Exchange (replace) in synchronization with 1. First of FIG.
In the color-difference signal switching circuit 22A, the original 3 words for synchronization of the SAV of the first digital color-difference signals Ecb1 / Ecr1, "FF", "00", "00" and fiber
The first horizontal synchronizing signal H1 is used as the first color synchronizing signal H1
Exchange (replace) in synchronization with. in this way,
Word signal in Fiber Channel (D21.4, D21.
4, D21.4) and word synchronization signals (K28.5, K28.5, K28.5
] Is inserted into the SAV portion of the luminance signal and the color difference signal, thereby enabling multiplex transmission using the fiber channel. Word signals (D21.4, D21.4, D21.4
] Is inserted into the SAV portion of the luminance signal, and the word synchronization signal [K28.5, K28.5, K28.5] is inserted into the SAV of the color difference signal, and [D21.4, D21.4, D21.4 ) Or (K28.5, K28.5, K28.5
], The receiving side (multiplexed video signal decoding device)
, It is possible to identify whether the luminance signal Ey is the color difference signals Ecb and Ecr.

Next, the second luminance signal switching circuit 14A in FIG. 4 switches the first luminance signal Ey1 switched in the first luminance signal switching circuit 12A based on the first horizontal synchronization signal H1. By this switching operation, the output data of the second luminance signal switching circuit 14A is input to either the first luminance signal memory 16A or the second luminance signal memory 18A. That is, the luminance signal Ey1 switched in the first luminance signal switching circuit 12A is alternately output to the first luminance signal memory 16A and the second luminance signal memory 18A for each first horizontal synchronization signal H1. You. First color difference signals Ecb1, E
Similarly, for the cr1, the second color difference signal switching circuit 24A converts the first color difference signals Ecb1 / Ecr1 switched in the first color difference signal switching circuit 22A to the first color difference signal Ecb1 / Ecr1.
Based on the horizontal synchronization signal H1. By this switching operation, the output data of the second luminance signal switching circuit 24A is input to either the first color difference signal memory 26A or the second color difference signal memory 28A. That is, the first color difference signals Ecb1 and Ecr1 switched by the first color difference signal switching circuit 22A are alternately provided for each first horizontal synchronization signal H1. 28A.

The first luminance signal memory 16A or the second luminance signal memory 18A is connected to the first word clock CLK.
The data output from the second luminance signal switching circuit 14A is stored in synchronization with 1. Similarly, the first color difference signal memory 26A or the second color difference signal memory 28A
The data output from the second color difference signal switching circuit 24 is stored in synchronization with the word clock CLK1. In the present embodiment, the first luminance signal Ey1 is stored in the first luminance signal memory 16A, and the first color difference signal Ecb
1, Ecr1 is stored in the first color difference signal memory 26A. The first luminance signal memory 16A and the first color difference signal memory 26A each successively store one line of the luminance signal Ey and the color difference signals Ecb and Ecr.

The first luminance signal memory 16A outputs the stored data to the third luminance signal switching circuit 20A according to the read clock REFCLK. Third
The luminance signal switching circuit 20A of FIG. 4 converts the data output from the first luminance signal memory 16A into the first horizontal synchronization signal H1.
And outputs to the common signal switching circuit 32 in response to the time multiplex timing pulse TMUX from the time multiplex timing signal generator. The first color difference signal memory 26A is
The stored data is output to the third color difference signal switching circuit 30A according to the read clock REFCLK. The third color difference signal switching circuit 30A outputs the data output from the first color difference signal memory 26A to the common signal switching circuit 32 according to the first horizontal synchronization signal H1 and the time multiplex timing pulse TMUX.

FIG. 8 is a diagram showing the state and timing of a transmission signal in the entire video signal multiplexing device illustrated in FIGS. The common signal switching circuit 32 includes a first
Luminance signal memory 16A and second luminance signal memory 1
8A (or the first color difference signal memory 26A and the second color difference signal memory 28A, not shown in FIG. 8), these luminance signals Ey (color difference signals Ecb, Ec).
r) is represented by the transmission rate and the number of multiplexes of the digital video signal input to the video signal multiplexing device (in this example, the multiplexing of two video signals of the luminance signal Ey and the color difference signals Ecb and Ecr, that is, the multiplexing number = 2), parallel / serial converter (P
/ S conversion unit) by switching from the word clock at the time of P / S conversion by the time multiplex timing pulse TMUX generated by the time multiplex timing signal generation unit 34,
By time-multiplexing two digital video signals of the luminance signal Ey and the color difference signals Ecb and Ecr and other information signals, time-multiplexed 16-bit parallel data is created. As a result, the luminance signal Ey and the color difference signals Ecb, Ecb
cr are multiplexed in a format as illustrated in FIG. For example, the SAV portion of the multiplexed first luminance signal Ey1 and first chrominance signal Ecb1 / Ecr1 indicating the start of serial signal transmission is as follows.

[K28.5, D21.4, K28.5, D21.4, K28.
5, D21.4]

The luminance signal Ey and the color difference signals Ecb, Ec
r, other information signals, such as ancillary, have a bit rate of fiber channel, parallel /
It also has a role to match the operation transmission rate of the serial converter 40.

The time-multiplexed parallel signal is converted from 8 bits to 10 bits by the 8-bit to 10-bit conversion unit 36, and converted into a parallel / serial conversion unit (P / P The parallel / serial converter (P / S converter) 40 converts the parallel signal into a serial signal, and sends the serial signal to a receiving side (multiplexed video signal decoding device) described in detail later.

By performing the above-described operation in the video signal multiplexing apparatus, multiplexed data satisfying the transmission standard of the fiber channel exemplified as the serial transmission system can be transmitted to the receiving side.

Processing of Second Digital Video Signal In the conversion section of the video signal multiplexer shown in FIG.
The second luminance signal Ey2 and the second color difference signal Ecb2
The same processing as that for the first video signal is performed for Ecr2. However, the word synchronizing signal for the fiber channel inputted to the first color difference signal switching circuit 22B of FIG. 5, D21.4], and is different from the above-described one in that the second word clock CLK2 and the second horizontal synchronization signal H2 are used.

The multiplexed second digital video signal 2
SAV of the luminance signal Ey2 and the color difference signal Ecb2 / Ecr2 represents the beginning of the second digital video signal,
It is as follows.

[D21.4, D21.4, D21.4] (Ey2) [K28.5, K28.5, D21.4] (Ecb2 / Ecr2)

The luminance signal Ey2 and the color difference signals Ecb2
With respect to other information signals other than Ecr2, such as ancillary data, in the same procedure as described with reference to FIG. . The reason is that, as described above, the receiving side can identify the second color difference signals Ecb2 and Ecr2.

[K28.5, K28.5, D21.4]

The luminance signal Ey and color difference signals Ecb and Ecr for one horizontal period and other information signals are
Similarly to the above, while switching in synchronization with the second horizontal synchronization signal H2, the luminance signal Ey2 is written from the second luminance signal switching circuit 14B to the first luminance signal memory 16B or the second luminance signal memory 18B, and The color difference signals Ecb2 and Ecr2 are transmitted from the second color difference signal switching circuit 24B to the first color difference signal memory 26B or the second
, And from these memories, the time multiplexed timing pulse TMUX output from the time multiplexed timing signal generator 34 and the read clock R output from the read clock generator 38.
The data is read out to the third luminance signal switching circuit 20B and the third color difference signal switching circuit 30B in synchronization with EFCLK. The video signal read from the third luminance signal switching circuit 20B and the third color difference signal switching circuit 30B is transmitted to the common signal switching circuit 3 together with other information.
2 and time-division multiplexed by a time-multiplexed timing pulse TMUX, converted to 10 bits by an 8-bit to 10-bit conversion unit 36, converted to serial data by a parallel / serial conversion unit 40, and converted to a fiber channel. And transmitted to the multiplexed video signal decoding device.

The effect of the video signal multiplexing device of the first embodiment
According to the video signal multiplexing apparatus of the first embodiment described results above, is configured as a commercially available general-purpose low-cost integrated circuits such as Fiber Channel (IC), 8-bit -1
0-bit converter 36 and parallel / serial converter 4
Since 0 can be used, there is no need to newly develop a dedicated IC. As a result, time, labor and cost can be reduced.

The video signal multiplexing apparatus of the first embodiment can use a GLM (Gigabaud Link Module) or a device, which is a signal transmission module of a physical layer such as a fiber channel, and thereby can further increase the number of layers. It can be realized at low price.

Further, according to the video signal multiplexing apparatus of the first embodiment, a clock recovery circuit is usually built in a commercially available parallel / serial conversion IC such as a fiber channel, and it is necessary to provide a clock recovery circuit. , The circuit scale can be reduced. In addition, in the video signal multiplexing device of the first embodiment to which a fiber channel or the like is applied, low power consumption at the time of a serial signal, low cost and miniaturization of the video signal multiplexing device can be realized. . Further, the reliability can be improved by using a serial transmission system having a proven track record such as a fiber channel.

Further, according to the video signal multiplexing apparatus of the first embodiment, the signal quality as serial data to be transmitted can be improved by performing 8B-10B conversion and data transmission.

Multiplexed Video Signal Decoding Device of First Embodiment A receiving system of a video signal multiplex transmission device, that is, a multiplexed video signal decoding device will be described with reference to FIGS. 9 illustrates a first part (first half) of the multiplexed video signal decoding device, and FIG. 10 illustrates a second part of the multiplexed video signal decoding device. (The latter half). Therefore, the multiplexed video signal decoding device is a combination of the circuit illustrated in FIG. 9 and the circuit illustrated in FIG. FIG. 11 illustrates an operation mode of the circuit illustrated in FIG. 9, and FIG. 12 illustrates an operation mode of the circuit illustrated in FIG.

The first half 50A of the multiplexed video signal decoding device illustrated in FIG. 9 includes a serial / parallel converter (S / P).
Conversion unit) 52 and a 10-bit to 8-bit conversion unit (10B
-8B converter) 54 and first switching circuit 6 on the receiving side
0. A second half 50B of the multiplexed video signal decoding device illustrated in FIG.
It has a receiving-system second luminance signal memory 68, a receiving-system second luminance signal switching circuit 70, and a receiving-system third luminance signal switching circuit 72. The second half 50B of the multiplexed video signal decoding device further includes a first color difference signal switching circuit 74 of the reception system and a first color difference signal memory 76 of the reception system.
And a second color difference signal memory 78 of the receiving system, a second color difference signal switching circuit 80 of the receiving system, and a third color difference signal switching circuit 82 of the receiving system.

The first half 50A of the multiplexed video signal decoding apparatus shown in FIG. 9 has a data separation timing generator 56 and a horizontal synchronizing signal parallel block generator 58. FIG.
Has a video signal parallel clock generator 86 and a horizontal synchronizing signal generator 88. However, the data separation timing generator 56, the horizontal synchronizing signal parallel block generator 58, the video signal parallel clock generator 86, and the horizontal synchronizing signal generator 88 can be placed at any positions in the multiplexed video signal decoding device.

The first switching circuit 60 converts the multiplexed video signal converted to 8 bits by the 10-bit to 8-bit conversion section 54 into the timing signal T as illustrated in FIG.
_1, according to T _2, T _3, the first luminance signal Ey1 and color difference signals ECB1, ECR 1 and other information, and, second
The luminance signal Ey2 and the color difference signals Ecb2 and Ecr2 are separated into other information.

The first luminance signal switching circuit 64 and the first color difference signal switching circuit 74 are switching circuits having three switching positions.
The position is switched according to ₁ , T ₂ and T ₃ .
The luminance signal Ey output from the first switching circuit 60 is input to the first luminance signal switching circuit 64.
As illustrated in FIG. 7, the signal is switched and input to the first luminance signal memory 66 or the second luminance signal memory 68. Similarly, the first color difference signal switching circuit 74 includes the color difference signals Ecb,
Ecr is input, switched, and input to the first color difference signal memory 76 or the second color difference signal memory 78.

The third luminance signal switching circuit 72 outputs the restored luminance signal E from the second luminance signal switching circuit 70.
y and the digital video signal's original word synchronization signal “F”.
F "," 00 ", and" 00 "are inputted, and as shown in FIG. 12, the SAV of the luminance signal Ey into which the fiber channel word signal [D21.4] is inserted.
Are replaced with the original word synchronizing signals "FF", "00", and "00" of the digital video signal. Similarly, the third luminance signal switching circuit 82 outputs the restored color difference signals Ecb, Ecb from the second color difference signal switching circuit 80.
1 and the word synchronizing signals “FF”, “00”, and “00”, which are digital video signals, are input.
As illustrated in FIG. 2, the color difference signal Ec into which [K28.5], which is the word synchronization signal of the fiber channel, is inserted.
The original word synchronizing signals “FF”, “00”, and “00” of the digital video signal are replaced with the SAV portion of b and Ecr.

Next, the overall operation of the multiplexed video signal decoding device will be described. The serial / parallel converter 5 of the multiplexed video signal decoder converts the multiplexed serial digital video signal transmitted from the above-described video signal multiplexer through a serial transmission system such as a fiber channel.
2 receives. When the serial / parallel converter 52 receives the multiplexed digital video signal, the serial / parallel converter 52 performs word synchronization when it receives the fiber channel word synchronization signal [K28.5, K28.5, K28.5]. And outputs the synchronization detection pulse COM_DET for one word period (20-bit period in this example) to the 10-bit to 8-bit conversion unit 54, the data separation timing generation unit 56, and the horizontal synchronization signal parallel block generation unit 58. . Further, the serial / parallel converter 52 converts the parallel clock CLK (in this case, a cycle of 20 bits) synchronized with the word synchronization signal [K28.5, K28.5, K28.5, K28.5] into 10 bits to 8 bits. Output to the conversion unit 54.

The 10-bit to 8-bit conversion unit 54 converts the 20-bit data after the S / P conversion in the serial / parallel conversion unit 52 into one by using the 20-bit parallel clock CLK output from the serial / parallel conversion unit 52.
0B-8B conversion and 16-bit multiplexed data
To the switching circuit 60 (demultiplexing circuit 60).

The data separation timing generation section 56 is provided with the synchronization detection pulse COM from the serial / parallel conversion section 52.
From the _DET and the 20-bit output, the timing signals T ₁ , T ₂ , and T ₃ illustrated in FIG. 11 are generated. These timing signals T ₁ , T ₂ , T ₃ are supplied to the first switching circuit 6
0, which is applied to the first luminance signal switching circuit 64 and the first color difference signal switching circuit 74 and used for switching.

Horizontal synchronization signal parallel block generator 58
Detects the synchronization detection pulse COM_DET from the serial / parallel converter 52 by a hardware circuit, detects the time when each digital video signal is multiplexed using the detection signal, and detects the time during which the digital video signal is multiplexed. The word clock output from the counter 52 is counted, and the word clock CLK of the video signal is reproduced by a digital phase locked loop (digital PLL).

The digital PLL has an oscillator which is digitally controlled, counts the number of output pulses of this oscillator and the number of pulses of an input signal, and makes the integrated value of both the numbers of pulses equal in a fixed time. This circuit is used to reproduce an accurate clock with phase synchronization.

As shown in FIG. 11, the first switching circuit 60 for separating the multiplexed data is switched from a high state during a period of three words (here, 20 bits / word) to a high period of two words. Until high, first
Of the digital video signal 1 (the first luminance signal Ey and the color difference signals Ecb and Ecr) are separated and output. Digital video signal 2 (second luminance signal E
y and the color difference signals Ecb, Ecr) are output separately. Further, the first switching circuit 60 operates for one word period high.
The information signal other than the luminance signal Ey and the chrominance signals Ecb and Ecr is separated from the time when the signal becomes high until the period becomes high for three words.

By the above processing, the first switching circuit 6
0, the first and second digital video signals 1, 2
And other information signals, and a luminance signal Ey
And the color difference signals Ecb and Ecr can be identified and separated.

In the video signal parallel clock generating section 86 and the horizontal synchronizing signal generating section 88, the synchronizing detection pulse C
The parallel clock CLK from the OM_DET and horizontal synchronization signal parallel block generator 58 is counted, and the clock CLK and the horizontal synchronization signal H are reproduced by the digital PLL.

In the first luminance signal memory 66 or the second luminance signal memory 68, the second luminance signal switching circuit 70, and the third luminance signal switching circuit 72, the clock CLK reproduced by the video signal parallel clock generation unit 86 Using the horizontal synchronizing signal H reproduced by the horizontal synchronizing signal generating section 88 and the horizontal synchronizing signal generating section 88, as shown in FIG. As shown in FIG. 12, the third luminance signal switching circuit 72 adds the digital video signal to the SAV portion of the luminance signal Ey into which the fiber channel word signal [D21.4] is inserted. "FF", "00", "00"
Is inserted. Thus, the digital luminance signal Ey input to the video signal multiplexer is decoded. Similarly, the first color difference signal memory 76 or the second color difference signal memory 78, the second color difference signal Switching circuit 80 and third
In the color difference signal switching circuit 82, the clock CLK reproduced by the video signal parallel clock generation unit 86
Using the horizontal synchronizing signal H reproduced by the horizontal synchronizing signal generating section 88 and the horizontal synchronizing signal generating section 88, as shown in FIG.
b, Ecr is reproduced. As shown in FIG. 12, the third luminance signal switching circuit 82 generates a digital signal in the SAV portion of the color difference signals Ecb and Ecr into which [K28.5], which is a word synchronization signal of the fiber channel, is inserted. The video signal original word synchronization signals “FF”, “00”
“00” is inserted, whereby the digital color difference signals Ecb and Ec input to the video signal multiplexing device are inserted.
r is decoded.

Multiplexed Video Signal Decoding Apparatus of First Embodiment
As described above, according to the multiplexed video signal decoding apparatus of the first embodiment, a low cost serial / parallel conversion unit 52, which is a commercially available general-purpose, integrated circuit, such as a fiber channel, is provided. Since the 10-bit to 8-bit conversion unit 54 can be used, the time, labor, and
Costs can be reduced. According to the multiplexed video signal decoding apparatus of the first embodiment, a GLM (Gigabaud Lin), which is a module for transmitting a signal of a physical layer such as a fiber channel, is used.
It can be configured at a low price by using a k module) or device. Further, a commercially available serial / parallel converter 52 such as a fiber channel according to the first embodiment usually incorporates a clock recovery circuit using a digital PLL, and it is not necessary to newly provide a digital PLL. The scale can be reduced. Also, in the multiplexed video signal decoding device of the first embodiment, 8B-
Since highly reliable multiplexed data of the 10B-converted and data-transmitted signal is received and decoded, the circuit load on the receiving circuit can be reduced, and jitter can be reduced even when a clock recovery circuit is connected in multiple stages. Can be reduced.

Modification of First Embodiment As a video signal multiplex transmission apparatus according to the first embodiment of the present invention, multiplexing of luminance / chrominance signals of 8-bit quantization has been described. The present invention can also be applied to the multiplexing of the luminance / color difference signals of the quantization, for example, the multiplexing of the luminance / color difference signals of the 10-bit quantization.

The present invention is not limited to the above-described multiplex transmission of the luminance signal and the color difference signal, but can be applied to the multiplexing of G (green), B (blue), and R (red) signals. In this case, the multiplexing number is 3 for GBR. In the video signal multiplexing device, instead of the multiplexing of the two video signals of the luminance signal Ey and the color difference signals Ecb and Ecr, three video signals of GBR are used. In the multiplexed video signal decoding device.
Species separation may be performed.

In the above embodiment, a fiber channel is exemplified as the serial transmission system. However, other serial transmission systems such as a gigabit Ethernet may be used.

In the present invention, the parallel / serial (P / S) conversion circuit (IC) and the serial / parallel (S / P) conversion for ATM are not limited to the above-mentioned fiber channel and gigabit Ethernet. A digital video signal can be time-multiplexed and transmitted using a circuit (IC). However, at that time, the word synchronization signal of the 8B-10B code in the above-mentioned fiber channel, gigabit Ethernet, etc. [K28.
5] and [D21.4] are replaced with A1 and A2 which are ATM word synchronization and frame synchronization pulses.

In the above description, a video signal multiplexing transmission apparatus in which a video signal multiplexing apparatus and a multiplexed video signal decoding apparatus operate in cooperation via a serial transmission system such as a fiber channel has been described. In practicing the present invention, a video signal multiplexing device alone or a multiplexed video signal decoding device alone can be applied.

Video Signal Multiplexing Transmission Apparatus of Second Embodiment As a second embodiment of the present invention, for example, FIGS. 1A and 1B shown in FIGS. D
Fiber channel parallel / serial conversion of 10-bit quantized digital video signals (luminance signal and color difference signal) such as 1, D2, and other information signals such as ancillary and line number data with 10-bit input / output means A video signal multiplex transmission apparatus for transmitting a multiplexed video signal using a circuit and a serial / parallel conversion circuit will be described.

FIGS. 13 to 17 are diagrams illustrating a video signal multiplexing device (transmission system) of a video signal multiplexing transmission device according to a second embodiment of the present invention. 13 and 14 illustrate circuits for multiplexing the first video signal, FIGS. 15 and 16 illustrate circuits for multiplexing the second video signal, and FIG. It is located after the circuit that multiplexes signals and is connected to these circuits.
FIG. 18 is a diagram illustrating the operation of the conversion unit of the video signal multiplexing device illustrated in FIG. 19 to 23 are diagrams illustrating a multiplexed video signal decoding device (reception system) of a video signal multiplex transmission device according to a second embodiment of the present invention. Second
The video signal multiplex transmission apparatus according to the embodiment has a serial transmission system, for example, a fiber channel shown in FIG.
17 to the multiplexed video signal decoding device illustrated in FIGS. 19 to 23 and the multiplexed video signal decoding device illustrated in FIGS.

Video Signal Multiplexer of Second Embodiment A first part of the video signal multiplexer shown in FIG. 13 for multiplexing the first video signal is a 10-bit first digital luminance signal Ey1. , A first luminance signal memory 102A of the transmission system, a digital luminance signal Ey1 read from the first luminance signal memory 102A, and a 4-word word synchronization signal [D21.
4, D21.4, D21.4, D21.4] in the transmission system. The fiber channel word signal replaced with the SAV of the first luminance signal Ey1 in the second embodiment is four words [D21.4, D21.4, D21.4, D21.4]. The video signal multiplexer also includes a 10-bit first digital color difference signal E.
The first color difference signal memory 104A of the transmission system to which cb1 / Ecr1 is input, and the digital color difference signals Ecb1 and Ecr1 read from the color difference signal memory 104A and the word synchronizing signal of four words [K28.5, K28.5 , K28.5, K28.5] is input to the first color difference signal switching circuit 11 of the transmission system.
0A. The word synchronization signal of the fiber channel replaced with the SAV of the first color difference signals Ecb1 and Ecr1 in the second embodiment is a 4-word [K28.5,
K28.5, K28.5, K28.5]. The video signal multiplexing apparatus further includes a first common signal switching circuit 112A of the transmission system.

The second part of the video signal multiplexer shown in FIG. 14 for multiplexing the first video signal is located after the video signal multiplexer shown in FIG. A transmission-system second common signal switching circuit 114A to which the output signal of the signal switching circuit 112A is input, a transmission-system switching first memory 116A, a transmission-system switching second memory 118A, And a third common signal switching circuit 120A.

The first part of the video signal multiplexer shown in FIG. 15 for multiplexing the second video signal is a first luminance signal of a transmission system to which a 10-bit second digital luminance signal Ey2 is input. The memory 102B and the digital luminance signal Ey read from the first luminance signal memory 102B
2 and a first luminance signal switching circuit 108B of a transmission system to which a word synchronization signal [D21.4, D21.4, D21.4, D21.4] of 4 words in the fiber channel is input.
SAV of second luminance signal Ey2 in the second embodiment
Is a four-word [D21.4, D21.4, D21.4, D21.4].
The video signal multiplexer also includes a first color difference signal memory 104B of a transmission system to which a 10-bit second digital color difference signal Ecb2 / Ecr2 is input, and a color difference signal memory 10B.
4B read out from the digital color difference signal Ecb2,
Ecr2 and 4-word word synchronization signal [K28.5, K28.5, K2
8.5, D21.4] in the transmission system. The word synchronization signal of the second embodiment, which is replaced by the SAV of the second color difference signals Ecb2 and Ecr2, is the following:
Unlike the SAV word synchronization signal [K28.5, K28.5, K28.5, K28.5] of the first color difference signals Ecb1, Ecr1, [K2
8.5, K28.5, K28.5, D21.4]. The video signal multiplexer further includes a first common signal switching circuit 112 of the transmission system.
B.

The second part of the video signal multiplexer shown in FIG. 16 for multiplexing the second video signal is located after the video signal multiplexer shown in FIG. A second common signal switching circuit 114B for the transmission system to which the output signal of the signal switching circuit 112B is input, a first memory 116B for switching the transmission system, a second memory 118B for switching the transmission system, and a transmission system. And a third common signal switching circuit 120B.

The third part of the video signal multiplexer shown in FIG. 17 is the third common signal switching circuit 120 shown in FIG.
A selected output (first multiplexed video data V1), FIG.
The fourth common signal switching circuit 12 of the transmission system for inputting the selection output signal (second multiplexed video data V2) of the fifth third common signal switching circuit 120B and other information
6 and a transmission system 8-bit to 10-bit conversion unit (8B-1
0B conversion section) 132 and a transmission system parallel / serial conversion section (P / S conversion section) 134.

The video signal multiplexer further has a first word clock conversion circuit 122A illustrated in FIG. The first word clock conversion circuit 122A converts the first word clock CLK1 used to store the 10-bit first digital brightness signal Ey1 into the first brightness signal memory 102A from the first brightness signal memory 102A.
A first bit conversion read clock BCCLK1 for reading the digital luminance signal Ey1 every 8 bits from A is generated. As illustrated in FIG. 18, when the first horizontal synchronization signal H1 is activated, the first luminance signal memory 102A converts the digital luminance signal Ey1 of the first line using the first word clock CLK1. The data is continuously packed from LSB to MSB at 10 bits / word and stored. When the luminance signal Ey1 stored in the first luminance signal memory 102A is activated by the first horizontal synchronization signal H1, the first bit conversion read clock B
The data is read from the first luminance signal memory 102A every 8 bits / word using CCLK1. Therefore, the first luminance signal memory 102A functions formally as a circuit that performs 10-bit to 8-bit conversion on the first digital luminance signal Ey1. First luminance signal memory 102A
Similarly to the above, the first color difference signal memory 104A also stores 10 digital color difference signals Ecb1 and Ecr1 of the first line.
It functions as a circuit for performing bit-8 bit conversion. First
The 8-bit first digital luminance signal Ey1 is input to the luminance signal switching circuit 108A. Similarly, the first
The 8-bit first digital color difference signals Ecb1 and Ecr1 are input to the color difference signal switching circuit 110A.

The video signal multiplexing apparatus further has a first word clock conversion circuit 122B illustrated in FIG.
The first word clock conversion circuit 122B is the first word clock conversion circuit 122B.
Is similar to the word clock conversion circuit 122A of FIG.
To process the video signal of the second word clock C
LK2 to second bit conversion read clock BCCL
The difference is that K2 is generated. That is, the first word clock conversion circuit 122B uses the second word clock CLK2 to store the second 10-bit digital luminance signal Ey2 in the first luminance signal memory 102B.
Then, a bit conversion read clock BCCLK2 for reading the digital luminance signal Ey2 from the first luminance signal memory 102B every eight bits is generated. Such a second
The second digital luminance signal Ey2 is stored in the first luminance signal memory 102B using the word clock CLK2, and the digital luminance signal Ey2 stored in the first luminance signal memory 102B is read using the bit conversion read clock BCCLK2. Thus, the first luminance signal memory 102B functions as a circuit that performs 10-bit to 8-bit conversion on the second digital luminance signal Ey2. Similarly to the first luminance signal memory 102B, a 10-bit second digital color difference signal Ecb2, Ecr2 is stored based on the second clock CLK2, and an 8-bit digital color difference signal Ecb2, based on the bit conversion read clock BCCLK2. The first color difference signal memory 104B for reading Ecr2 is also provided with the second digital color difference signal Ec.
It functions as a circuit that performs 10-bit to 8-bit conversion on b2 and Ecr2. First luminance signal switching circuit 1
08B has an 8-bit second digital luminance signal Ey2.
Is entered. Similarly, the first color difference signal switching circuit 1
10B has an 8-bit second digital color difference signal Ecb.
2, Ecr2 is input.

The video signal multiplexing apparatus has the second word clock conversion circuit 123A illustrated in FIG. 14 and a read clock generation circuit 124. The second word clock conversion circuit 123A is connected to the first common signal switching circuit 1
The first memory 1 for switching the data multiplexed in 12A through the second common signal switching circuit 114A.
A recording clock MCLK1, which is a clock for storing in the 16A or the second switching memory 118A, is generated from the first clock CLK1. The read clock generation circuit 124 generates a read clock REFCLK used to read data from the first switching memory 116A and the second switching memory 118A. The video signal multiplexing apparatus has the second word clock conversion circuit 123B illustrated in FIG. FIG. 16 illustrates the read clock generation circuit 124. Reading of data from the memory is performed according to the frequency of the first video signal and the frequency of the second video signal. The second word clock conversion circuit 123B is the second word clock conversion circuit 123B.
Of the second word clock CLK2 for the second video signal processing.
From the multiplexed data in the first common signal switching circuit 112B to the second common signal switching circuit 114B.
, A recording clock MCLK2 that is a clock for storing in the first switching memory 116B or the second switching memory 118B.

The video signal multiplexing apparatus further includes a time multiplex timing signal generator 128, a horizontal synchronizing signal generator 136, and a word clock generator 138 illustrated in FIG. The word clock generator 138 generates a clock CLK1 for processing a first video signal and a second clock CLK2 for processing a second video signal. The horizontal synchronizing signal generator 136 converts the first horizontal synchronizing signal H1 for the first video signal processing and the second horizontal synchronizing signal for the second video signal processing from the first clock CLK1 and the second clock CLK2. The signal H2 is generated. The time multiplexed timing signal generator 128 includes first and second clocks CLK1 and C1.
A time multiplex timing pulse TMUX for time multiplexing a video signal is generated from LK2 and the first second horizontal synchronization signal H1, H2.

The first word clock conversion circuit 122A and the double clock generation circuit 106A illustrated in FIG.
Second word clock conversion circuit 123 illustrated in FIG.
A and the read clock generation circuit 124, the first word clock conversion circuits 122B and 122 illustrated in FIG.
Double clock generation circuit 106B, second word clock conversion circuit 123B and read clock generation circuit 124 illustrated in FIG. 16, time multiplexed timing signal generation section 128 illustrated in FIG. 17, horizontal synchronization signal generation section 136 and word clock generation section 138 is only illustrated near the portion where those signals are provided and can be located anywhere in the video signal multiplexer.

First luminance signal switching circuit 10 in FIG.
8A, the horizontal synchronization signal generator 1 illustrated in FIG.
In synchronization with the first horizontal synchronizing signal H1 provided from S36, the SAV synchronizing data “3FF”, “000”, “000”, “000” of the first digital luminance signal Ey1
"Is a four word word signal [D2
1.4, D21.4, D21.4, D21.4]. Similarly, in the first color difference signal switching circuit 110A, the SAV synchronization data “3FF”, “000”, “000” of the first digital color difference signals Ecb1 and Ecr1 are synchronized with the first horizontal synchronization signal H1. , "000
"Is the fiber channel word sync signal [K28.5, K2
8.5, K28.5, K28.5]. On the receiving side, the word signal (D21.4, D21.4, D21.
4, D21.4) and word sync signals (K28.5, K28.5, K28.5, K28.
5], the luminance signal Ey1 or the color difference signal Ec
b, Ecr1.

The video signal multiplexing apparatus further has a double clock generation circuit 106A illustrated in FIG. The double clock generation circuit 106A generates a clock 2CLK1 having a frequency twice the frequency of the bit conversion read clock BCCLK1 generated in the first word clock conversion circuit 122A, and applies the clock 2CLK1 to the first common signal switching circuit 112A to perform a switching operation. Used for That is, in the first common signal switching circuit 112A, the luminance signal Ey1 from the first luminance signal switching circuit 108A and the color difference signals Ecb1 from the first color difference signal switching circuit 110A.
Since the Ecr1 is switched and multiplexed, the first luminance signal memory 102A and the first chrominance signal memory 10A are switched.
4A, the luminance signal Ey1 and the color difference signals Ecb1, Ec
Bit conversion read clock BCCLK for reading r1
A clock having a frequency twice as high as the frequency of 1, ie, a double clock 2CLK1 is required.

The portion for processing the second video signal of the video signal multiplexing apparatus further has a double clock generation circuit 106B illustrated in FIG. 15 similar to the double clock generation circuit 106A illustrated in FIG. The double clock generation circuit 106B outputs the bit conversion read clock BCCLK2 generated in the first word clock conversion circuit 122B.
Clock 2CLK2 having a frequency twice as high as
To the common signal switching circuit 112B for switching operation. That is, also in the second video signal processing, in the first common signal switching circuit 112B, the luminance signal Ey2 from the first luminance signal switching circuit 108B and the color difference signal Ecb2 from the first color difference signal switching circuit 110B are used. Since Ecr2 is switched and multiplexed, the frequency of the bit conversion read clock BCCLK2 is twice the frequency of the bit conversion read clock BCCLK2 for reading the luminance signal Ey2 and the color difference signals Ecb2 and Ecr2 from the first luminance signal memory 102B and the first color difference signal memory 104B. A clock, that is, a double clock 2CLK2 is required.

The first video signal V1 multiplexed in the first common signal switching circuit 112A is supplied to the first horizontal synchronization signal H1 provided from the horizontal synchronization signal generator 136 in the second common signal switching circuit 114A. The memory is selectively distributed to the first switching memory 116A or the second switching memory 118A in synchronization with the selected memory (116A or 11A).
8A) is stored in synchronization with the recording clock MCLK1. First memory 116A and second memory 118A
And the first multiplexed video signal V1 is stored in the read clock REF from the read clock generation circuit 124.
The signal is read out in synchronization with the clock signal CLK, and is time-multiplexed and output by the third signal switching circuit 120A based on the time multiplexing timing pulse TMUX supplied from the time multiplexing timing signal generator 128 illustrated in FIG. You.

The second multiplexed video signal V2 multiplexed in the first common signal switching circuit 112B is
Is selectively distributed to the first switching memory 116B or the second switching memory 118B in synchronization with the second horizontal synchronization signal H2 provided from the horizontal synchronization signal generator 136 in the common signal switching circuit 114B. Any input and selected memory 116B or 1
18B is stored in synchronization with the recording clock MCLK2. First memory 116B and second memory 118B
And the second multiplexed video signal V2 is stored in the read clock REF from the read clock generation circuit 124.
The signal is read out in synchronization with the clock signal CLK, and is selectively output in the third common signal switching circuit 120B based on the time multiplexing timing pulse TMUX supplied from the time multiplexing timing signal generator 128 illustrated in FIG.

Processing of First Video Signal Referring to FIG. 13, FIG. 14, FIG. 17, and FIG.
Multiplexing of the digital luminance signal Ey1 and the first digital color difference signal Ecb1 / Ecr1 will be described.

The first luminance signal memory 102A stores the first digital luminance signal Ey1 of 10 bits / word in synchronization with the first horizontal synchronizing signal H1 and the first word clock CLK1. S of signal Ey1
8 bits / word are sequentially separated from the LSB of the first word of the AV. Thus, the first luminance signal memory 102A
In S1, the SAV of the 10-bit / word first line digital luminance signal Ey1 is converted to an 8-bit / word digital luminance signal to decompose the SAV portion. Similarly to the above, the SAV of the first color difference signals Ecb1 and Ecr1 is stored in the first color difference signal memory 104A in synchronization with the first horizontal synchronization signal H1 and the first word clock CLK1, and the first line of 10 bits / word. The SAV portion of the digital color difference signal Ecb1 / Ecr1 is stored, and 8 bits / word are sequentially separated from the LSB of the first word of the SAV of the digital color difference signal Ecb1 / Ecr1. Thus, in the first color difference signal memory 104A, 10
S of digital color difference signal of first line of bit / word
The AV is converted to an 8-bit / word digital color difference signal to decompose the SAV portion.

Next, the first luminance signal switching circuit 108
In A, the first four words after converting the SAV of the first digital luminance signal Ey1 into 8 bits / word in the first luminance signal memory 102A, that is, 1
“3FF”, “00” which is a SAV with 0 bits / word
0, “000” and the lower two bits of four words “00”
"And a fiber channel word signal [D21.4, D21.
4, D21.4, D21.4] in synchronization with the first horizontal synchronizing signal H1. As a result, the luminance signal E
The SAV portion of y1 is a word synchronization signal [D21.4, D21.
4, D21.4, D21.4].

[D21.4, D21.4, D21.4, D21.4] (Ey1)

As described above, the word signals [D21.4, D21.4, D2
1.4, D21.4], as described in detail in the first embodiment, in order to transmit a multiplexed video signal using a fiber channel transmission path and to enable synchronization on the receiving side. It is.

Similarly to the processing of the luminance signal Ey1, the first
Of the first digital chrominance signal Ecb1 / Ecr1 in the first chrominance signal memory 104A after converting it to 8 bits / word, that is, 10 bits / word.
"3FF", "000", "0" which are SAV in word
00 and the lower two bits "00" of the four words and the fiber channel word synchronization signal [K28.5, K28.5, K28.5, K2
8.5] is switched (replaced) in synchronization with the first horizontal synchronization signal H1. As a result, the digital color difference signal E
The SAV portion of cb1 and Ecr1 is replaced by the following word synchronization signal [K28.5, K28.5, K28.5, K28.5].

[K28.5, K28.5, K28.5, K28.5] (Ecb1 / Ecr1)

Next, the first common signal switching circuit 11
In 2A, the data from the first luminance signal switching circuit 108A and the data from the first color difference signal switching circuit 110A are switched (switched) according to the double clock 2CLK1 from the double clock generation circuit 106A. ), And outputs a time-division multiplexed first digital video signal V1 of 8 bits.

As a result of the above operation, as illustrated in FIG. 18, the first digital luminance signal Ey at the time of transmitting the serial signal output from the first common signal switching circuit 112A.
1 and the first digital chrominance signal Ecb1 / Ecr1 are mixed, and the first part of the first multiplexed digital video signal V1 becomes a data sequence in the following order.

K28.5, D24.1, K28.5, D21.4, K28.5
, D21.4, K28.5, D21.4

As described above, the word synchronizing signal when the fiber channel is applied is inserted into the first multiplexed digital video signal. FIG. 18 typically illustrates the processing of the digital luminance signal Ey1, but the processing of the digital color difference signals Ecb1 and Ecr1 is the same as that of the digital luminance signal Ey1.

After the first part of the first digital video signal V1, a 10-bit digital luminance signal Ey
1 and 10-bit digital color difference signals Ecb1, Ecb1
Digital video signals obtained by extracting cr1 as 8-bit data sequentially follow. The above multiplexing process is performed on the digital luminance signal Ey1 and the digital color difference signals Ecb1 and Ecr1 of one field.

With respect to other information signals such as ancillary signals other than the digital luminance signal Ey1 and the digital chrominance signals Ecb1 and Ecr1, in the same procedure as described above, after the parallel / serial conversion at the beginning of the digital video signal, the following data is obtained. Add.

K28.5, D20.4

Here, the data following [K28.5] is as described above.
[D21.4] is replaced by [D20.4]. The reason is that the signals are different from the luminance signal Ey and the color difference signals Ecb and Ecr in order to identify other information.

The second common signal switching circuit 114A multiplexes the first multiplexed signal by the first common signal switching circuit 112A.
The video signal V1 is switched according to the first horizontal synchronization signal H1 and applied to the first memory 116 or the second memory 118. These memories have a first-line luminance signal Ey input in response to a first clock CLK1.
1 is continuously stored. Thus, the first video signal V1 stored in the memory 116A or 118A is read from these memories in response to the read clock REFCLK, and is read in the third common signal switching circuit 120A in response to the time multiplex timing pulse TMUX. The switched time axis is multiplexed and the fourth time illustrated in FIG.
Is applied to the common signal switching circuit 126. The first multiplexed video signal applied to the fourth common signal switching circuit 126 is extracted as 8-bit time-axis multiplexed data based on the time-multiplexed timing pulse TMUX, and is converted into an 8-bit-10-bit converter 132. Is converted to 10-bit data by the read clock REFCLK, and is converted to serial data by the parallel / serial converter 134 by the read clock REFCLK, and is transmitted to the fiber channel.

Processing of Second Video Signal Referring to FIG. 15, FIG. 16, FIG. 17, and FIG.
The multiplexing process of the digital luminance signal Ey2 and the second digital color difference signal Ecb2 / Ecr2 will be described.

The second processing circuit illustrated in FIG. 15 and FIG. 16 is similar to the circuit illustrated in FIG. 13 and FIG. The second digital luminance signal Ey2 is also stored in the first luminance signal memory 10 in the same manner as the first digital luminance signal Ey1.
2B. Second digital color difference signal Ecb
2 and Ecr2 are also the first digital color difference signals Ecb1 and Ecb1.
It is input to the first color difference signal memory 104B in the same manner as cr1. As described above, the processing of the second video signal is the same as the processing of the first video signal described above. The differences are as follows.

[0132] 1. First color difference signal switching circuit 110B
, The fiber channel word synchronization signal for identifying the second color difference signals Ecb2 and Ecr2 is [K28.5, K28.5, K28.5, K28.5] for the first video signal.
], Not [K28.5, K28.5, K28.5, D21.4]. 2. A second word clock CLK2 instead of the first word clock CLK1, a second horizontal synchronization signal H2 instead of the first horizontal synchronization signal H1, a second bit conversion instead of the first bit conversion read clock BCCLK1 Read clock BCCLK2, first double clock 2 ×
A second double clock 2 × CLK2 instead of CLK1;
The second storage clock MCLK2 is used instead of the first storage clock MCLK1. However, these control signals are merely used depending on the state of the video signal, and there is no essential difference in signal processing.

As a result of the above differences, the processing of the second video signal is as follows. S of the second digital luminance signal Ey2 in the first luminance signal switching circuit 108B
The AV synchronization signal and data sequence are as follows.

[D21.4, D21.4, D21.4, D21.4] (Ey2)

S of the second digital color difference signals Ecb2 and Ecr2 in the first color difference signal switching circuit 110B
The AV synchronization signal and data sequence are as follows.

[K28.5, K28.5, K28.5, D21.4] (Ecb2 / 2cr2)

These data are supplied to the double clock generation circuit 106B in the first common signal switching circuit 112B.
Is switched in response to the double clock 2CLK2 from the second clock, and a time-division multiplexed 8-bit second digital video signal V2 is output. SA of multiplexed data at this time
The portion of V is as follows.

K28.5, D24.1, K28.5, D21.4, K28.5
, D21.4, D21.4, D21.4

After the first part of the second digital video signal V2, a 10-bit digital luminance signal Ey2 and a 10-bit digital color difference signal Ecb2, Ecr2
Are successively output as digital video signals obtained by cutting out as 8-bit data.

For the first video signal, the second common signal switching circuit 114A illustrated in FIG. 13 and for the second video signal in the second common signal switching circuit 114B illustrated in FIG. The converted video signal V1 or the second multiplexed video signal V2 and other information signals are stored in a memory (the first switching memory 116A or the first switching memory 116A) according to the horizontal synchronization signals H1 and H2 from the horizontal synchronization signal generator 136. 2, memory 118A,
Then, the first switching memory 116B or the second switching memory 118B) is selected and stored according to the storage word clocks MCLK1 and MCLK2 from the second word clock conversion circuits 123A and 123B.

Thereafter, the memory (116A, 118A or 11A) selected by the horizontal synchronizing signals H1 and H2.
6B, 118B) and the read clock REFCLK from the read clock generation circuit 124.
Read out in synchronization with the third common signal switching circuit 1
Input to 20A and 120B.

The third common signal switching circuit 120A, 1
20B and the fourth common signal switching circuit (multiplexed signal separation circuit) 126
The input signal is switched in accordance with the time multiplexing timing pulse from 28 to perform time axis multiplexing.

The 8-bit parallel signal output from the common signal switching circuit 126 is converted into a 10-bit time base multiplexed signal by the 8B-10B converter 132 in synchronization with the read clock REFCLK from the read clock generation circuit 124. Is done. The time axis multiplexed signal is synchronized with the read clock REFCLK by the P / S converter 134.
Is converted to serial data. The data converted into serial data in this manner is sent to a fiber channel (not shown).

The video signal multiplexing device of the second embodiment, like the video signal multiplexing device of the first embodiment, transmits transmission data according to the communication protocol of a serial transmission system such as a fiber channel. Can be sent to Therefore, the effects are applied to the video signal multiplexing device of the first embodiment also in the video signal multiplexing device of the second embodiment.

The video signal multiplexing device of the first embodiment is as follows when compared with the video signal multiplexing device of the first embodiment. 1. The difference in the bits of the video signal input to the video signal multiplexer. This is an 8-bit parallel digital video signal in the first embodiment, whereas a 10-bit parallel digital video signal in the second embodiment. The difference between the bits is that in the second embodiment, the brightness signal memories 102A, 102A,
02B, in the color difference signal memories 104A and 104B,
It is adjusted by bit conversion processing. 2. There is a difference in the number of word synchronization signals according to the difference in bit length. For example, the luminance signal synchronizing signal has three words of [D21.4, D21.4, D21.4] in the first embodiment, but [D21.4, D21. 4, D21.4, D21.
4]. 3. In the second embodiment, a first common signal switching circuit 112 is provided after the first luminance signal switching circuits 108A and 108B and the first color difference signal switching circuits 110A and 110B. That is, the luminance signal Ey and the color difference signals Ecb and Ecr are multiplexed at an early stage before the first memory 116 and the second memory 118.

Multiplexed Video Signal Decoding Apparatus of Second Embodiment A receiving system, that is, a multiplexed video signal decoding apparatus in a video signal multiplex transmission apparatus according to a second embodiment of the present invention is shown in FIG.
This will be described with reference to FIGS. 19 to 23 are diagrams illustrating first to third parts of the multiplexed video signal decoding device according to the second embodiment of the present invention.

FIG. 19 shows a common processing section of the multiplexed video signal decoding device. The multiplexed video signal decoding device illustrated in FIG. 19 is a serial / parallel conversion of a receiving system that inputs serial data transmitted from the video signal multiplexing device transmitted via a fiber channel and converts the serial data into a parallel signal. (S / P converter) 202, a 10-bit to 8-bit converter (10B-8B converter) 204 of the receiving system, and a first switching circuit 210 on the receiving side. The multiplexed video signal decoding device illustrated in FIG.
It has a double clock generation circuit 206, a data separation timing generation section 208 of the reception system, and a horizontal synchronization signal parallel block generation section 209 of the reception system.

FIGS. 20 and 21 show a portion for decoding the first multiplexed video signal. The multiplexed video signal decoding device illustrated in FIG.
A, a first switching memory 214A for the receiving system, a second switching memory 216A for the receiving system, a third switching circuit 218A for the receiving system, and a fourth switching circuit 220A for the receiving system. . The multiplexed video signal decoding device illustrated in FIG.
A, a receiving system color difference signal switching circuit 226A, a receiving system luminance signal memory 228A, and a receiving system color difference signal memory 230A. The multiplexed video signal decoding device illustrated in FIG. 21 further includes a word clock conversion circuit 222A.

FIGS. 22 and 23 show a portion for decoding the second multiplexed video signal. The multiplexed video signal decoding device illustrated in FIG.
B, a first switching memory 214B for the receiving system, a second switching memory 216B for the receiving system, a third switching circuit 218B for the receiving system, and a fourth switching circuit 220B for the receiving system. . The multiplexed video signal decoding device illustrated in FIG.
B, a receiving system color difference signal switching circuit 226B, a receiving system luminance signal memory 228B, and a receiving system color difference signal memory 230B. The multiplexed video signal decoding device illustrated in FIG. 23 further includes a word clock conversion circuit 222B.

The operation of the multiplexed video signal decoding device illustrated in FIGS. 19 to 23 will be described below. The serial digital video signal multiplexed from the transmission system of the data transmission apparatus described above is received by the serial / parallel converter 202 conforming to the fiber channel standard illustrated in FIG. 19 and converted into a 10-bit parallel video signal. I do. At this time, when the serial / parallel converter 202 receives the synchronization signal [K28.5] inserted in the SAV, the serial / parallel converter 202 establishes word synchronization and sets the synchronization detection pulse C for a period of 20 bits.
Output OM_DET. Further, the serial / parallel converter 202 outputs a parallel clock for a 20-bit period synchronized with the synchronization signal [K28.5].

The double clock generation circuit 206 generates a double clock 2CLK having a frequency twice as high as the frequency of the parallel clock output from the serial / parallel converter 202 of the receiving system, and applies it to the 10-bit / 8-bit converter 204. . 1
The 0-bit to 8-bit conversion unit 204 converts the 10-bit parallel data output from the serial / parallel conversion unit 202 into 8-bit parallel data in response to the double clock 2CLK, and sends the converted data to the first switching circuit 210. Apply.

The data separation timing generation section 208, like the one illustrated in FIG. 11, outputs the data separation timing signals T ₁ , T ₂ , and T ₂ based on the 10-bit parallel data output from the serial / parallel conversion section 202. T ₃
Occurs. Horizontal synchronization signal parallel block generator 20
9 generates the first and second horizontal synchronization signals H1 and H2.

The first switching circuit 210 converts the data input from the 10-bit to 8-bit conversion unit 204 based on the data separation timing signals T ₁ , T ₂ , and T ₃ output from the data separation timing generation unit 208. Separate,
The signals are separated into a first digital video signal V1, a second digital video signal V2, and other information signals, and output from terminals OT1, OT2, and OT3. The method of data separation in the first switching circuit 210 will be described more specifically.

[0154] The first switching circuit 210, the received data according to the data separation timing signal T ₁ to the high level when below, and outputs a first digital video signal V1 from the first output terminal OT1 .

K28.5, D21.4, K28.5, D21.4, K28.5
, D21.4, K28.5, D21.4

[0156] The first switching circuit 210, the received data according to the data separation timing signal T _2, which becomes high level when below, and outputs a second digital video signal V2 from the second output terminal OT2 .

K28.5, D21.4, K28.5, D21.4, K28.5
, D21.4, D21.4, D21.4

[0158] The first switching circuit 210, the received data according to the data separation timing signal T _3, which becomes a high level when the following, and outputs the other information from the third output terminal OT3.

K28.5, D20.4

The multiplexed video signal decoding device illustrated in FIGS. 20 to 21 decodes the first digital video signal separated by the first switching circuit 210. That is, in the second switching circuit 212A, in response to the timing signal for data separation _T 1, T _2, T ₃ first
The first video signal is applied to the switching memory 214 or the second switching memory 216. Data applied to these memories is stored according to the parallel clock CLK. Thereafter, the signal is read out in response to the read clock REFCLK, and is switched in the third switching circuit 218A in accordance with the first horizontal synchronization signal H1, and in the fourth switching circuit 220A, the first horizontal synchronization signal H1 and the parallel signal are output. Switching is performed according to the clock CLK, and separated into the first luminance signal Ey1 and the first color difference signals Ecb1 and Ecr1. In the luminance signal switching circuit 224A, the SA of the first luminance signal Ey1 is
V, “FF”, “03”, “00”, “00”, which are the original word synchronization signals of the digital video signal, are inserted according to the first horizontal synchronization signal H1 and the first word clock CLK1. Similarly, the color difference signal switching circuit 22
6A, S of the first color difference signals Ecb1 and Ecr1
In the AV, "FF", "03", "00", "00", which are the original word synchronization signals of the digital video signal, are applied to the first horizontal synchronization signal H1 and the first word clock CLK1.
Inserted according to. In the luminance signal memory 228A, the 8-bit digital luminance signal Ey1 output from the luminance signal switching circuit 224A is converted into a 10-bit digital luminance signal Ey1 applied to the video signal multiplexer.
Is converted to a signal corresponding to The 8-bit to 10-bit conversion process in the luminance signal memory 228 is performed by the first
Is realized by performing a process reverse to that of the luminance signal memory 102A. Similarly, in the color difference signal memory 230A, the 8-bit digital color difference signals Ecb1 and Ecr1 output from the color difference signal switching circuit 226A are converted into the 10-bit digital color difference signals Ecb1 and Ecr1 applied to the video signal multiplexer. Is converted to a signal corresponding to

As described above, the 10-bit digital luminance signal Ey1 and the 10-bit digital color difference signals Ecb1 and Ecr1 of the first video signal are decoded.

In the multiplexed video signal decoding device illustrated in FIGS. 22 to 23, the second digital video signal V2 separated by the first switching circuit 210 is decoded and the 10-bit second video signal is decoded. The luminance signal Ey2 and the 10-bit color difference signals Ecb2 and Ecr2 are decoded. The operation is the same as the decoding described with reference to FIGS. 20 to 21 except that the circuit configuration of the multiplexed video signal decoding device illustrated in FIGS. Description is omitted.

Multiplexed Video Signal Decoding Apparatus of Second Embodiment
The effects of the multiplexed video signal decoding device according to the second embodiment are the same as those of the multiplexed video signal decoding device according to the first embodiment described above.

In the video signal multiplex transmission apparatus of the second embodiment, not only the multiplexing of 10-bit quantized luminance / color difference signals but also the multiplexing of 8-bit digital video signals or GBR signals. Is similarly applicable.
However, in the case of an 8-bit digital video signal, the first luminance signal memory 102A and the first color difference signal memory 104A illustrated in FIG. 13, the first luminance signal memory 102B illustrated in FIG. Signal memory 104B,
In addition, the luminance signal memory 228A and the color difference signal memory 230A of the receiving system illustrated in FIG. 21 and the luminance signal memory 228B and the color difference signal memory 230B of the receiving system illustrated in FIG. 23 can be deleted.

The implementation of the video signal multiplex transmission apparatus of the present invention is not limited to the above-described embodiment, and various modifications can be made based on the technical concept of the present invention. For example, by using A1 and A2 which are the word synchronization and frame synchronization pulses of the ATM in place of the word synchronization signal [K28.5] of the 8B-10B code, the P / S conversion circuit for the ATM can be obtained in the same manner as described above. , And a digital video signal can be time-multiplexed and transmitted using an S / P conversion circuit.

[0166]

According to the present invention, Fiber Channel, Gigabit Ethernet (Gigabit Ethernet)
digital video signals can be transmitted using commercially available general-purpose inexpensive P / S converter circuits and S / P converter circuits such as bit Ethernet), so that the time, labor and cost of developing a new dedicated IC can be reduced. Can be done.

Further, according to the present invention, the price can be reduced by using a GLM (Gigabaud Link Module) or a device which is a signal transmission module of a physical layer such as a fiber channel or a gigabit Ethernet.

Further, according to the present invention, commercially available P / S such as Fiber Channel and Gigabit Ethernet,
The S / P conversion IC has a built-in clock recovery circuit, and by using the clock recovery circuit, it is not necessary to separately provide such a circuit, so that the circuit scale can be reduced. Further, power consumption, price, size, and reliability of the serial signal transmission device can be reduced.

According to the present invention, the signal quality as serial data to be transmitted can be improved by performing data conversion by bit conversion by a 10-bit to 8-bit conversion unit or the like. The circuit load on the receiving circuit can be reduced, and the accumulation of jitter in multistage connection can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a format of a video signal applied to a video signal multiplex transmission apparatus according to the present invention; FIG. 1A is a diagram illustrating a digital luminance signal Ey; ) Is the digital first color difference signal Ecb.
FIG. 10 is a diagram illustrating a format of a stream of a / digital second color difference signal Ecr.

FIGS. 2A and 2B are diagrams illustrating the format of a multiplexed parallel data stream obtained by multiplexing the video signals illustrated in FIGS. 1A and 1B.

FIGS. 3A and 3B are a functional waveform diagram and a diagram illustrating data mapping for 8-bit / 10-bit notation, respectively.

FIG. 4 is a partial circuit configuration diagram of a first video signal processing portion (conversion unit) in the video signal multiplexing device according to the first embodiment of the present invention.

FIG. 5 is a partial circuit configuration diagram of a second video signal processing section (conversion section) in the video signal multiplexing apparatus according to the first embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a multiplexing / transmission portion of a video signal multiplexing device according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a conversion process in the video signal multiplexing device illustrated in FIGS. 4 and 5;

FIG. 8 is a diagram illustrating a multiplexing / transmission process in the video signal multiplexing device illustrated in FIG. 6;

FIG. 9 is a circuit configuration diagram of a first portion of the multiplexed video signal decoding device according to the first embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of a second part of the multiplexed video signal decoding device according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating the operation of the circuit illustrated in FIG. 9;

FIG. 12 is a diagram for explaining the operation of the circuit illustrated in FIG. 10;

FIG. 13 is a first partial circuit configuration diagram of a first video signal processing portion (conversion unit) in a video signal multiplexing device according to a second embodiment of the present invention.

FIG. 14 is a first partial circuit configuration diagram of a first video signal processing part (conversion unit) in a video signal multiplexing apparatus according to a second embodiment of the present invention.

FIG. 15 is a first partial circuit configuration diagram of a second video signal processing section (conversion section) in the video signal multiplexing apparatus according to the second embodiment of the present invention.

FIG. 16 is a first partial circuit configuration diagram of a second video signal processing section (conversion section) in the video signal multiplexing apparatus according to the second embodiment of the present invention.

FIG. 17 is a circuit configuration diagram of a multiplexing / transmission part of a video signal multiplexing device according to a second embodiment of the present invention.

FIG. 18 is a diagram illustrating processing in the video signal multiplexing device illustrated in FIGS. 13 to 17;

FIG. 19 is a circuit configuration diagram of a first portion of a multiplexed video signal decoding device according to a second embodiment of the present invention.

FIG. 20 is a circuit configuration diagram of a first portion that decodes a first video signal of a multiplexed video signal decoding device according to a second embodiment of the present invention.

FIG. 21 is a circuit configuration diagram of a second portion that decodes a first video signal of a multiplexed video signal decoding device according to a second embodiment of the present invention.

FIG. 22 is a circuit configuration diagram of a first portion that decodes a second video signal of the multiplexed video signal decoding device according to the second embodiment of the present invention.

FIG. 23 is a circuit configuration diagram of a second portion that decodes a second video signal of the multiplexed video signal decoding device according to the second embodiment of the present invention.

[Explanation of symbols]

10. Video signal multiplexing device (transmission system) of video signal multiplexing transmission device 10A First half of video signal multiplexing device 12 First luminance signal switching circuit 14 Second luminance signal switching circuit 16 A first luminance signal memory 18 a second luminance signal memory 20 a third luminance signal switching circuit 22 a first color difference signal switching circuit 24 a second color difference signal switching circuit 26 First color difference signal memory 28 Second color difference signal memory 30 Third color difference signal switching circuit 10B Second half of video signal multiplexer 32 Common signal switching circuit 34 Time multiplex timing signal Generating unit 36 ··· 8-bit to 10-bit converting unit 38 ··· Readout clock generating unit 40 ··· Parallel / serial converting unit 42 ··· Horizontal synchronization signal generating circuit 44 ··· Word clock Lock generation circuit 50: Multiplexed video signal decoding device of video signal multiplex transmission device (reception system) 50A: First half of multiplexed video signal decoding device 52: Serial / parallel converter 54: 10 bits to 8 bits Conversion section 56 Data separation timing generation section 58 Horizontal synchronization signal parallel block generation section 60 First switching circuit 50B Second half of multiplexed video signal decoding device 64 First luminance signal switching circuit 66 first luminance signal memory 68 second luminance signal memory 70 second luminance signal switching circuit 72 third luminance signal switching circuit 74 first color difference signal switching circuit 76 First color difference signal memory 78 second color difference signal memory 80 second color difference signal switching circuit 82 third color difference signal switching circuit 86 1 video signal parallel clock generation unit 88 horizontal synchronization signal generation unit 100 video signal multiplex transmission device (transmission system) 100A of second embodiment 100A first part of video signal multiplexing device 102 first Luminance signal memory 104, first color difference signal memory 106, double clock generation circuit 108, first luminance signal switching circuit 110, first color difference signal switching circuit 112, first common signal switching Circuit 114 Second common signal switching circuit 116 First switching memory 118 Second switching memory 120 Third common signal switching circuit 122 First word clock conversion circuit 123 ..The second word clock conversion circuit 124..the read clock generation circuit 126..the fourth common signal switching circuit 128..the time multiplexor. Ming signal generating section 132 8 bit-10 bit converting section 134 parallel / serial converting section 136 horizontal synchronizing signal generating section 138 word clock generating section 200 multiplexed video signal of video signal multiplex transmission apparatus Decoding device (reception system) 202: serial / parallel converter 204: 10-bit to 8-bit converter 206: double clock generation circuit 208: data separation timing generator 209: horizontal synchronization signal parallel block generator 210 first switching circuit 212 second switching circuit 214 first switching memory 216 second switching memory 218 third switching circuit 220 fourth switching circuit 222 word clock conversion circuit 224 luminance signal switching circuit 226 color difference signal switching Road 228 ... luminance signal memory 230 ... color difference signal memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C057 AA03 BA02 BA11 CB07 EB01 EL01 GB02 GB03 GB07 GF05 GF07 GG01 GH05 5C059 RA01 RB01 RC02 5C063 AA01 AA11 AB03 AB07 AC01 AC10 CA14 CA16 CA23 CA40 5K028 BB08 NN08 KK08 BB08 KK08 SS16 SS24

Claims (43)

[Claims] A video signal multiplexing transmission apparatus for multiplexing a plurality of digital video signals each having a predetermined first number of bits into a video signal having a predetermined second number of bits and continuously transmitting the multiplexed video signal to a serial transmission system. Synchronizing signal insertion means for inserting a synchronizing signal used in the serial transmission system and identifying each digital video signal into a timing reference signal portion of one horizontal synchronizing period of each digital video signal; Multiplexing means for time-multiplexing the plurality of digital video signals into which the synchronization signal has been inserted for each horizontal synchronization period; parallel video of the second number of bits for each predetermined bit of the multiplexed serial video signal A bit converting means for converting the parallel video signal into a serial format video signal; A video signal multiplexing device having a real / serial conversion means. 2. The video signal multiplexing apparatus according to claim 1, wherein said plurality of digital video signals are a composite signal having a luminance signal, a color difference signal, and information related thereto. 3. The video signal according to claim 2, wherein the synchronization signal includes a luminance signal synchronization signal for identifying a luminance signal in each of the digital video signals, and a color difference signal synchronization signal for identifying a digital color difference signal. Multiplexer. 4. The digital video signal according to claim 1, wherein said plurality of digital video signals are digital video signals of a D1 system, a D2 system, a high-definition television system, and the like. 4. The video signal multiplexer according to claim 3, wherein the predetermined number of bits is 8 bits. 5. The synchronizing signal inserting means has a first input terminal, a second input terminal, and one output terminal, wherein the digital luminance signal is input to the first input terminal, A first input terminal for receiving the synchronizing signal for the luminance signal, replacing the data of a predetermined portion of the SAV of the digital luminance signal as the timing reference signal portion with the synchronizing signal for the luminance signal, and outputting from the output terminal. A luminance signal switching circuit, a first input terminal, a second input terminal, and one output terminal, wherein the digital chrominance signal is input to the first input terminal, and the second input terminal is connected to the second input terminal. 1 of the digital chrominance signal, and the data of a predetermined portion of the SAV of the digital chrominance signal is replaced with the first chrominance signal synchronization signal as the timing reference signal portion. First image signal multiplexing apparatus according to claim 4, further comprising a color difference signal switching circuit which outputs from. 6. The synchronizing signal inserting means has a first input terminal, a second input terminal, and one output terminal, wherein the digital luminance signal is input to the first input terminal, The second luminance signal synchronization signal is input to an input terminal of the digital luminance signal, and the data of a predetermined portion of the SAV of the digital luminance signal is replaced with the second luminance signal synchronization signal as the timing reference signal portion. And a second luminance signal switching circuit that outputs the digital color difference signal from the first input terminal, the second input terminal, and one output terminal. The first color difference signal synchronization signal is input to an input terminal of the digital color difference signal, and the data of a predetermined portion of the SAV of the digital color difference signal is replaced with the first color difference signal synchronization signal as the timing reference signal portion. Video signal multiplexing apparatus according to claim 4, further comprising a second color-difference signal switching circuit for outputting from the output terminal Te. 7. The multiplexing means has an input terminal for inputting the digital luminance signal and two output terminals, and outputs the input signal from any one of two output terminals in response to the first horizontal synchronization signal. A third luminance signal switching circuit for selectively outputting, and a third luminance signal switching circuit connected to two output terminals of the third luminance signal switching circuit, respectively, and an output from the second luminance signal switching circuit according to a first storage clock. Memorized data,
A first luminance signal memory and a second luminance signal memory provided in parallel for reading data stored in accordance with the read clock; and from the first luminance signal memory and the second luminance signal memory. The first luminance signal memory and the second luminance signal memory have two input terminals for inputting read data and one output terminal.
A fourth luminance signal switching circuit for switching data read from the luminance signal memory according to the first horizontal synchronization signal and the read clock; an input terminal for inputting the digital color difference signal; and two output terminals A third color difference signal switching circuit that selectively outputs the input signal from any of two output terminals in response to the first horizontal synchronization signal; and a third color difference signal switching circuit. Respectively connected to output terminals, storing data output from the second color difference signal switching circuit according to a first storage clock;
A first color-difference signal memory and a second color-difference signal memory provided in parallel for reading data stored in accordance with the read clock; and from the first color-difference signal memory and the second color-difference signal memory. The first color difference signal memory has two input terminals for inputting read data and one output terminal.
A fourth color difference signal switching circuit for switching data read from the color difference signal memory according to the first horizontal synchronization signal and the read clock; a fourth luminance signal switching circuit; and the fourth color difference signal 7. The video signal multiplexing apparatus according to claim 6, further comprising a common signal switching circuit for switching an output from the switching circuit in accordance with a time multiplexing timing pulse and outputting a parallel bit multiplexed video signal of a predetermined bit. 8. The second bit number in the serial transmission system is 20 bits, the common signal switching circuit outputs 8-bit data as 16-bit time-multiplexed data, and the bit conversion means outputs 16-bit data. 8. The video signal multiplexing apparatus according to claim 7, further comprising a circuit for converting data into 10-bit data every 8 bits and converting the data into 20-bit time multiplexed data. 9. The serial transmission system has means for serially transmitting 10-bit data, and the parallel / serial conversion means converts the 20-bit time-multiplexed data output from the bit conversion means to 10-bit serial data. 8. The video signal multiplexing device according to claim 7, further comprising a circuit for converting the video signal into a video signal. 10. The serial transmission system has a fiber channel, and the first luminance signal synchronization signal and the second luminance signal synchronization signal are [D21.4, D21.4, D21.4]. And the first color difference signal synchronization signal is [K28.5, K28.5, K28.5
And the second color difference signal synchronization signal is [K28.5, K
28.5, D21.4]. 11. The video signal multiplexing apparatus according to claim 7, wherein said serial transmission system is a transmission system for transmitting 10-bit encoded data. 12. A bit conversion circuit for converting the number of bits of a digital video signal into the first number of bits when the digital video signal input to the video signal multiplexer is not the first number of bits. 2. The video signal multiplexing apparatus according to claim 1, wherein said digital video signal bit-converted by said bit conversion circuit is applied to said synchronization signal inserting means. 13. A multiplexed digital video signal transmitted through a serial transmission system and multiplexed with a plurality of digital video signals each having a predetermined second bit number, and the multiplexed digital video signal is restored. A multiplexed video signal decoding device for decoding into a digital video signal of a predetermined first number of bits, respectively, wherein a synchronization signal included in a serial format multiplexed digital video signal transmitted through the serial transmission system. , And a clock recovery means for recovering a clock based on the synchronization detection signal; and a horizontal synchronization for processing the original digital video signal from the recovered clock. Horizontal synchronizing signal generating means for generating a signal; and identifying the type of the received video signal based on the type of the synchronizing signal. Data separation timing signal generation means for generating another data separation timing signal; serial / parallel conversion means for converting the multiplexed digital video signal of the first bit number of the serial format detected in synchronization into a parallel format; Bit conversion means for bit-converting the multiplexed video signal having the first number of bits converted into the parallel format by the serial / parallel conversion means into the video signal having the second number of bits; Signal separating means for separating the parallel video signal into original digital video signals and other information related to the video signals based on the data separation timing signal; and multiplexing the separated video signals. A digital video signal is reproduced by the horizontal synchronizing signal and the reproduced signal. Demultiplexing means for demultiplexing based on the obtained clock, and synchronizing the original video signal with the serial transmission system synchronization signal included in the video signal demultiplexed by the demultiplexing means. A multiplexed video signal decoding device, comprising: a synchronizing signal replacing unit that replaces the signal with a signal. 14. The digital video signal comprises a luminance signal,
14. The multiplexed video signal decoding device according to claim 13, wherein the multiplexed video signal decoding device is a composite signal having a color difference signal and information related thereto. 15. The digital video signal according to claim 1, wherein:
A digital video signal of a D2 system, a high-definition television system, or the like; a first number of bits transmitted through a serial transmission system and input to the multiplexed video signal decoding device is 10; 15. The multiplexed video signal decoding device according to claim 14, wherein the number of bits is eight. 16. The multiplexing system according to claim 15, wherein said serial transmission system includes a fiber channel and a gigabit Ethernet, and wherein the synchronization signal included in said multiplexed video signal is a synchronization signal of said fiber channel and gigabit Ethernet. Video signal decoding device. 17. The multiplexed video signal according to claim 15, wherein the serial transmission system is an asynchronous network (ATM), and the synchronization signal included in the multiplexed video signal is a synchronization signal of the asynchronous network. Decoding device. 18. A video signal multiplex transmission device having a video signal multiplexing device and a multiplexed video signal decoding device connected via a serial transmission system, wherein each of said video signal multiplexing devices has a predetermined A video signal multiplexing apparatus for multiplexing a plurality of digital video signals of one bit number into a video signal of a predetermined second bit number and continuously transmitting the multiplexed video signal to a serial transmission system, wherein the digital video signal Synchronizing signal insertion means for inserting a synchronizing signal used in the serial transmission system and identifying each digital video signal into a timing reference signal portion of one horizontal synchronizing period; Multiplexing means for time-multiplexing the plurality of inserted digital video signals; Bit conversion means for converting the second bit number into a parallel video signal;
Parallel / serial converting means for converting the bit-converted parallel video signal into a serial format video signal, wherein the multiplexed video signal decoding device transmits a predetermined second video signal transmitted through a serial transmission system. A multiplexed video which receives a multiplexed digital video signal in which a plurality of bits of digital video signals are multiplexed, restores the multiplexed digital video signal, and decodes the original digital video signal having a predetermined first number of bits. A signal decoding device, comprising: a synchronization detecting means for detecting a synchronization signal included in a serial format multiplexed digital video signal transmitted through the serial transmission system and outputting a synchronization detection pulse; Clock recovery means for recovering a clock based on the clock; and respective original digital data from the recovered clock. Horizontal synchronizing signal generating means for generating a horizontal synchronizing signal for video signal processing; a data separating timing signal for generating a data separating timing signal for identifying the type of the received video signal based on the type of the synchronizing signal Generating means; serial / parallel converting means for converting the synchronously detected multiplexed digital video signal of the first bit number of the serial format into a parallel format;
Bit conversion means for bit-converting the multiplexed video signal of the first number of bits converted into the parallel format by the serial / parallel conversion means to the video signal of the second number of bits; bit-converted by the bit conversion means Signal separating means for separating a parallel video signal into original digital video signals and other information related to the video signals based on the data separating timing signal; and the separated multiplexed digital video signals Demultiplexing means for demultiplexing a signal based on the horizontal synchronization signal and the reproduced clock; synchronization for the serial transmission system included in the video signal demultiplexed by the demultiplexing means Video signal multiplex transmission, comprising: synchronizing signal replacing means for replacing a signal with a synchronizing signal of an original video signal. Location. 19. The video signal multiplex transmission apparatus according to claim 18, wherein said plurality of digital video signals are a composite signal having a luminance signal, a color difference signal and information relating thereto. 20. The video signal according to claim 19, wherein the synchronization signal includes a luminance signal synchronization signal for identifying a luminance signal in each of the digital video signals, and a color difference signal synchronization signal for identifying a digital color difference signal. Multiplex transmission equipment. 21. The digital video signal according to claim 1, wherein
20. A digital video signal such as a digital video signal, a digital video signal, a high-definition television system, and the like, wherein the first predetermined number of bits of the digital video signal input to the video signal multiplexing transmission device is 8 bits. Video signal multiplex transmission equipment. 22. The video signal multiplexing system according to claim 18, wherein said serial transmission system is an asynchronous network (ATM), and wherein a synchronization signal included in said multiplexed video signal is a synchronization signal of said asynchronous network. Transmission equipment. 23. A video signal multiplexing apparatus for multiplexing a plurality of digital video signals each having a predetermined first number of bits and transmitting the multiplexed digital video signals to a serial transmission system as a video signal having a predetermined second number of bits. Synchronizing signal insertion means for inserting a synchronizing signal used in the serial transmission system into a timing reference signal portion of one horizontal synchronizing period of each of a plurality of digital video signals; and multiplexing the video signal into which the synchronizing signal has been inserted. Multiplexing means for generating a multiplexed video signal; time-axis multiplexing means for respectively time-multiplexing the plurality of multiplexed video signals; bits of the time-axis multiplexed video signal having a first number of bits Bit conversion means for converting the number of bits into the second number of bits for each predetermined bit, and serially converting the bit-converted multiplexed parallel format video signal. Video signal multiplexing apparatus and a parallel / serial converting means for converting the video signal format. 24. The digital video signal comprises a luminance signal,
24. The video signal multiplexing device according to claim 23, wherein the video signal multiplexing device is a composite signal having a color difference signal and information related thereto. 25. A synchronization signal for a luminance signal for identifying a luminance signal of each of the plurality of digital video signals, and a synchronization signal for a color difference signal for identifying a color difference signal of each of the plurality of digital video signals. The video signal multiplexing device according to claim 24, comprising: 26. The digital video signal according to claim 1, wherein:
26. The video according to claim 25, wherein the first predetermined number of bits of the digital video signal input to the video signal multiplexing transmission apparatus is 8 bits, the digital video signal being a D2 system, a high definition television system, or the like. Signal multiplexer. 27. The synchronizing signal insertion means has a first input terminal, a second input terminal, and one output terminal. The digital luminance signal is input to the first input terminal, and the second input terminal is connected to the second input terminal. A first input terminal for receiving the synchronizing signal for the luminance signal, replacing the data of a predetermined portion of the SAV of the digital luminance signal as the timing reference signal portion with the synchronizing signal for the luminance signal, and outputting from the output terminal. A luminance signal switching circuit, having a first input terminal, a second input terminal, and one output terminal, wherein the digital color difference signal is input to the first input terminal, and the color difference signal is input to the second input terminal. A signal synchronizing signal is inputted, and data of a predetermined portion of the SAV of the digital color difference signal is replaced with the color difference signal synchronizing signal as the timing reference signal portion and output from the output terminal. That the first video signal multiplexing apparatus according to claim 25 and a color-difference signal switching circuit. 28. The synchronization signal inserting means has a first input terminal, a second input terminal, and one output terminal. The digital luminance signal is input to the first input terminal, and The second synchronizing signal for the luminance signal is inputted to an input terminal of the digital signal, and the data of a predetermined portion of the SAV of the digital luminance signal is replaced with the synchronizing signal for the luminance signal as the timing reference signal portion, and is output from the output terminal. A luminance signal switching circuit, having a first input terminal, a second input terminal, and one output terminal, wherein the digital color difference signal is input to the first input terminal, and the color difference signal is input to the second input terminal. A signal synchronizing signal is inputted, and data of a predetermined portion of the SAV of the digital color difference signal is replaced with the color difference signal synchronizing signal as the timing reference signal portion and output from the output terminal. That the second video signal multiplexing apparatus according to claim 25 and a color-difference signal switching circuit. 29. The digital video signal according to the D1 system,
26. The video according to claim 25, wherein the first predetermined number of bits of the digital video signal to be input to the video signal multiplexing transmission apparatus is 8 bits, the digital video signal being a two-system, high-definition television system, or the like. Signal multiplexer. 30. The multiplexing means has an input terminal for inputting the digital luminance signal and two output terminals, and outputs the input signal from one of two output terminals in response to the first horizontal synchronization signal. A third luminance signal switching circuit for selectively outputting, the third luminance signal switching circuit being connected to two output terminals of the third luminance signal switching circuit, respectively, and outputting from the third luminance signal switching circuit in accordance with a first storage clock; Memorized data,
A first luminance signal memory and a second luminance signal memory provided in parallel for reading data stored in accordance with the read clock; and from the first luminance signal memory and the second luminance signal memory. The first luminance signal memory and the second luminance signal memory have two input terminals for inputting read data and one output terminal.
A fourth luminance signal switching circuit that switches data read from the luminance signal memory according to the horizontal synchronization signal and the read clock, an input terminal for inputting the digital color difference signal, and two output terminals; A third color-difference signal switching circuit for selectively outputting the input signal from any of two output terminals in accordance with the horizontal synchronization signal, and a third color-difference signal switching circuit connected to the two output terminals, respectively; Storing data output from the third color difference signal switching circuit in accordance with a first storage clock;
A first color difference signal memory and a second color difference signal memory provided in parallel for reading data stored according to the read clock; and reading from the first color difference signal memory and the second color difference signal memory. The first color difference signal memory and the second color difference signal memory.
A fourth color difference signal switching circuit that switches data read from the color difference signal memory according to the horizontal synchronization signal and the read clock; and a fourth luminance signal switching circuit and a fourth color difference signal switching circuit. 24. The video signal multiplexing apparatus according to claim 23, further comprising: a common signal switching circuit that switches the output of the video signal according to a time multiplexing timing pulse and outputs a parallel time multiplexed video signal of a predetermined bit. 31. The second bit number in the serial transmission system is 20 bits, the common signal switching circuit outputs 8-bit data as 16-bit time multiplexed data, and the bit conversion means outputs 16-bit data. 31. The video signal multiplexing apparatus according to claim 30, further comprising a circuit for converting data into 10-bit data every 8 bits and converting the data into 20-bit time multiplexed data. 32. The serial transmission system has means for serially transmitting 10-bit data, and the parallel / serial conversion means converts the 20-bit time multiplexed data output from the bit conversion means into 10-bit serial data. 31. A circuit for converting to
7. The video signal multiplexing device according to claim 1. 33. The serial transmission system has a fiber channel, and the first luminance signal synchronization signal and the second luminance signal synchronization signal are [D21.4, D21.4, D21.4, D21.4], and the first color difference signal synchronization signal is [K28.5, K28.5, K28.5,
K28.5], and the second color difference signal synchronization signal is [K28.5].
31. The video signal multiplexing apparatus according to claim 30, wherein 8.5, K28.5, K28.5, D21.4]. 34. The video signal multiplexing apparatus according to claim 30, wherein said serial transmission system is a transmission system for transmitting 10-bit encoded data. 35. A bit conversion circuit for converting the number of bits of the digital video signal into the first number of bits when the digital video signal input to the video signal multiplexing device is not the first number of bits. 24. The video signal multiplexing apparatus according to claim 23, wherein the digital video signal bit-converted by said bit conversion circuit is applied to said synchronization signal inserting means. 36. A multiplexed video signal decoding apparatus for receiving a multiplexed digital video signal of a first number of bits transmitted through a serial transmission system and decoding it into an original digital video signal of a second number of bits. A synchronization detection means for detecting a synchronization signal included in the serial format multiplexed digital video signal transmitted through the serial transmission system and outputting a synchronization detection pulse; Clock reproducing means for reproducing a clock; horizontal synchronizing signal generating means for generating a horizontal synchronizing signal for a video signal to be restored from the reproduced clock; and, in accordance with the content of the video signal, based on the content of the synchronizing signal. Data separation timing signal generating means for generating a data separation timing signal; and Serial / parallel conversion means for converting a multiplexed digital video signal having a bit number into a parallel format, and converting the multiplexed video signal having a first bit number converted into a parallel format by the serial / parallel conversion means into the second bit number Bit conversion means for bit-converting the video signal into a plurality of video signals based on the data separation timing signal, and a plurality of other video signals related to the video signal. Signal demultiplexing means for demultiplexing the separated video signal, demultiplexing means for demultiplexing the separated video signal based on the horizontal synchronization signal and the reproduced clock, and multiplexing by the demultiplexing means. The serial transmission system synchronization signal included in the released video signal is replaced with the synchronization signal of the original video signal. Multiplexed video signal decoding apparatus comprising a synchronizing signal replacement means for replacing the. 37. A digital video signal comprising: a luminance signal;
37. The multiplexed video signal decoding device according to claim 36, wherein the multiplexed video signal decoding device is a composite signal having a color difference signal and information related thereto. 38. The digital video signal according to claim 1, wherein:
A digital video signal of a D2 system, a high-definition television system, or the like; the first number of bits transmitted through a serial transmission system and input to the multiplexed video signal decoding device is 10; 37. The multiplexed video signal decoding device according to claim 36, wherein the number of bits is eight. 39. The video according to claim 36, wherein the serial transmission system includes a fiber channel and a gigabit Ethernet, and the synchronization signal included in the multiplexed video signal is a synchronization signal of the fiber channel and the gigabit Ethernet. Signal multiplex transmission equipment. 40. A video signal multiplex transmission device having a video signal multiplexing device and a multiplexed video signal decoding device connected via a serial transmission system, wherein each of said video signal multiplexing devices has a predetermined A video signal multiplexing device for multiplexing a plurality of digital video signals of a first number of bits and transmitting a video signal of a second number of bits to a serial transmission system. Synchronization signal insertion means for inserting a synchronization signal used in the serial transmission system into a timing reference signal portion of a horizontal synchronization period; multiplexing means for multiplexing a video signal into which the synchronization signal has been inserted to generate a multiplexed video signal Time-division multiplexing means for respectively time-division-multiplexing the plurality of multiplexed video signals; and determining the number of bits of the time-division-multiplexed video signal having the first number of bits. Bit conversion means for converting the predetermined number of bits into the second number of bits;
Parallel / serial conversion means for converting the bit-converted multiplexed parallel format video signal into a serial format video signal, wherein the multiplexed video signal decoding device is transmitted through a serial transmission system. A multiplexed video signal decoding device for receiving a multiplexed digital video signal having a first number of bits and decoding it into an original digital video signal having a second number of bits. Synchronization detection means for detecting a synchronization signal included in the multiplexed digital video signal of the format and outputting a synchronization detection pulse; clock recovery means for reproducing a clock based on the synchronization detection signal; Horizontal synchronizing signal generating means for generating a horizontal synchronizing signal for a video signal restored from a clock; Data separation timing signal generating means for generating a data separation timing signal in accordance with the content of the video signal; and converting the synchronously detected multiplexed digital video signal of the first bit number of the serial format into a parallel format. A serial / parallel converter for converting; a bit converter for bit-converting the multiplexed video signal of the first number of bits converted into the parallel format by the serial / parallel converter into the video signal of the second number of bits; Signal separating means for separating the parallel video signal bit-converted by the bit converting means into a plurality of respective video signals and other information related to the video signal based on the data separation timing signal; Based on the horizontal synchronization signal and the reproduced clock. Demultiplexing means for demultiplexing, and synchronizing signal replacement for replacing the serial transmission system synchronizing signal contained in the video signal demultiplexed by the demultiplexing means with the synchronizing signal of the original video signal And a video signal multiplex transmission device comprising: Multiplexed video signal decoding device. 41. The digital video signal comprises a luminance signal,
41. The video signal multiplex transmission apparatus according to claim 40, wherein the video signal multiplex transmission apparatus is a composite signal having a color difference signal and information related thereto. 42. The video according to claim 40, wherein the serial transmission system includes a fiber channel and a gigabit Ethernet, and the synchronization signal included in the multiplexed video signal is a synchronization signal of the fiber channel and the gigabit Ethernet. Signal multiplex transmission equipment. 43. The video signal multiplex transmission apparatus according to claim 40, wherein the serial transmission system includes an asynchronous network, and the synchronization signal included in the multiplexed video signal is a synchronization signal of the asynchronous network. .