JP2000124243A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a fine solder bump while its high productivity is ensured by a method wherein high-accuracy solder plating is performed selectively into a plurality of fine through holes, solder pieces are moved collectively onto a semiconductor chip and fine solder bumps are formed. SOLUTION: A laminated film is formed of a nickel film and a gold film to use as barrier metals on a pellet H like bare semiconductor chip. Then, a hole is formed in a position corresponding to the electrode of the semiconductor chip on a carrier having a structure in which a conductor layer is sandwiched between resins. A copper foil inside the foil is etched. A hole is made on the copper foil. A through hole is formed. Then, solder plating is performed to the part of the copper foil which is exposed on the wall surface of the through hole in the carrier. A solder piece is formed inside the through hole. Then, the carrier is brought into close contact with the electrode pad. While this state is being kept, this assembly is passed through a reflow furnace, and the solder piece is made to reflow. In addition, the carrier is separated from the semiconductor chip in its reflow operation. As a result, the solder piece is transferred to the electrode pad, and it is possible to obtain a semiconductor element in which a spherical bump electrode 8 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bump electrode formed on a bonding pad of a semiconductor chip to be flip-chip mounted on a circuit wiring board.

[0002]

2. Description of the Related Art In recent years, with the development and spread of information processing technology, electronic devices have been reduced in size, thickness, and performance, and semiconductor chips have also been reduced in size and integrated. .

In particular, an LSI such as a microprocessor unit that operates at a frequency of several hundred MHz and performs arithmetic processing
A method of mounting a chip on a module substrate by flip-chip connection technology has been adopted in order to cope with multiple inputs / outputs, an increase in processing speed, and a reduction in size.

In the flip chip connection technology, the mounting area of the semiconductor element on the substrate can be made the same as the size of the semiconductor device, and the connection wiring length can be shortened as compared with the wire bonding method, the TAB method, etc. This mounting technology is suitable for high-speed mounting. Flip chip mounting is a general term for a method of connecting a semiconductor element and a circuit board to each other with bump electrodes facing each other. Depending on the connection method, solder bump connection, microbump connection, anisotropic conductive film connection, conductive paste connection , And press-fit connections.

[0005] Above all, the method using solder bumps has a wide allowable range for mounting position deviation due to the self-alignment effect at the time of reflow connection, and the solder bumps undergo plastic deformation to reduce stresses generated at the connection parts, thereby achieving high reliability. It has advantages such as being able to be used more easily, and has become the mainstream of flip chip mounting.

As a method for forming a solder bump on a semiconductor element electrode, a physical deposition method and a plating method are widely used. In the physical deposition method, a metal film is deposited by an evaporation method, a sputtering method, or the like, and is patterned by photolithography to form a barrier metal on an electrode.

The barrier metal is composed of a metal having good adhesion to the aluminum electrode, a metal having a relatively slow diffusion of tin in solder, a metal having good wettability with solder, and an antioxidant metal. Further, the barrier metal is generally composed of two or three layers by using a metal having the above-mentioned effects in order to reduce the cost and the number of steps.

[0008] As a barrier metal for solder, a laminated film of titanium / copper / gold, a laminated film of chromium / copper / gold, etc. are used. The highest reliability is obtained by a structure on which the layers are deposited. In particular, when a tin-lead eutectic solder having a high tin content is used, the reaction between nickel and tin is slower than the reaction between copper and tin. Higher reliability compared to barrier metal configurations (S. Honma, et. Al., "
Effectiveness of thin file
m barrier metals for eute
cticolder bumps ", Procee
ings of ISHM '96, pp. 87-
92, 1996).

A mask is placed on the barrier metal, and tin and lead are deposited by a vapor deposition method. In this case, since the deposited thickness of tin and lead is as thick as 10 μm or more, the shadow of the mask is formed due to the difference in the incident angle, and it is difficult to obtain a uniform film thickness. Further, since the amount of metal deposited on an extra place such as a wall surface in the vapor deposition apparatus becomes enormous, it becomes difficult to maintain the degree of vacuum by gas adsorption.

In the plating method, after a barrier metal portion is patterned in advance, a resist film is formed, an opening pattern is formed in a portion where a bump is to be formed by photolithography, and a bump is formed by a pattern plating method (Japanese Patent Application Laid-Open (JP-A) no. Japanese Patent Application Laid-Open No. 61-141159) discloses a technique of forming a bump electrode by a pattern plating method, and then etching and removing a barrier metal using the bump as a mask.
223436) and the like. In each case, since the bump electrodes are formed by electroplating, a thick solder film can be formed at a high speed, and the productivity is extremely high. Further, there is no problem due to deposits in the apparatus such as a physical deposition method.

However, since both the physical deposition method and the plating method use a photolithography technique,
The process at the wafer stage before the semiconductor chips are cut into pellets is essential. For this reason, it is impossible to form a solder bump electrode on a bare chip in a pellet state for mounting by a generally available wire bonding method, TAB method, or the like.

As a method of forming solder bump electrodes on the bare chip in a pellet state, a method by wire bonding, a solder ball supply method, a screen printing method, and the like have been developed.

The method using wire bonding is shown in FIG.
As shown in FIGS. 20 to 20, ball bonding is performed on the electrode pad 6 of the semiconductor element using the solder wire 20, and 1st
After bonding, the wires are cut off to form bumps one by one (T. Ogashiwa, et.
l. , "Solder bump formatio
n for flip-chip interconn
action by ball bonding me
things ", Proceedings ofIMC
1990, p. 228-234, 1990). After the wires 20 are cut off, reflow is performed to form the solder bumps 8. If the amount of solder is small, bonding is performed at the same location to form a multi-stage bump. For example, 80 μm
In order to obtain a solder ball having a height of 3 mm, it is necessary to use a 40 μm wire and stack three or four steps. That is, for a multi-terminal semiconductor chip, there is a problem that the efficiency is extremely low and the manufacturing cost increases.

The solder ball supply method is a method in which a solder ball is supplied onto an electrode of a semiconductor chip using a mask having a hole through which the ball passes, and the bump is formed as it is through a reflow furnace (K. Inoue, et.a
l. , "Development of solde
r ball arraying method fo
r BGA bump formation ", Pr
Oceedingsof IMC 1996, pp.
280-284, 1996). If a flux is applied on the chip in advance, the solder ball is fixed even if the mask is removed, so that the reflow operation becomes easy.
However, when the solder ball diameter is large, such as BGA or CSP, the mutual adhesion between the balls is weak, but 100 μm
Since the weight of a ball having a diameter equal to or smaller than the diameter is proportional to the cube of the radius, the mutual adhesion is increased, and the ball often does not enter the hole of the mask. That is, when forming fine bump electrodes on a semiconductor chip, it is difficult to obtain completeness.

The screen printing method uses a similar mask,
As shown in FIGS. 21 to 24, a method of filling a solder paste 23 into a hole of a print mask 21 using a squeegee 22 and printing the solder paste on the electrode 6 on the semiconductor chip is used. After printing, before or after removing the mask, reflow is performed to form solder bump electrodes 8 (H. Mishi).
ma, et. al. , "A new technology
ology of screen printing
method to soldier bumpform
ing applications ", Processe
dingsof IMC 1996, pp. 231-
236, 1996). In this method, similarly to the above-mentioned solder ball supply method, there is a problem that when the mask hole diameter is small, it becomes difficult for the paste to enter the holes, and it is difficult to form fine bumps while ensuring the integrity.

In any of the above-mentioned methods, the pellet-shaped semiconductor chip on which the bump electrodes are formed has fine electrode pads and a fine pitch.
It is difficult to obtain an electrical connection with a socket or the like used in a CP or the like, which makes a normal burn-in test very difficult. For this reason, there is a problem that the screening of the chip cannot be performed, and it is difficult to guarantee the quality of the chip as in the case of the semiconductor chip in the conventional package.

[0017]

As described above, when solder bumps are formed, the plating method is widely used because of its excellent productivity. The bump could not be formed on the semiconductor chip.

On the other hand, as a method of forming solder bump electrodes on a bare chip in a pellet state, a method by wire bonding, a solder ball supply method, a screen printing method, and the like have been developed. Low productivity because multiple bondings are required. Further, it is difficult to form a fine solder bump having a diameter of 100 μm or less by the solder ball supply method or the screen printing method.

Accordingly, it has been difficult to produce solder bump electrodes at high density on a pellet-shaped bare semiconductor chip while ensuring high productivity by using any of the methods. In addition, pellet-shaped bare semiconductor chips with bump electrodes formed have fine electrode pads, which cannot be screened by a burn-in test, and chip quality must be assured in the same way as for chips in conventional packages. Had difficult problems.

The present invention has been made in view of the above problems, and in particular, provides a method for collectively manufacturing fine solder bumps on a pellet-shaped bare semiconductor chip and a method for burn-in test of the semiconductor chip. The purpose is to do.

[0021]

In order to achieve the above object, the present invention (claim 1) provides a method for manufacturing a bump electrode on an electrode pad on a semiconductor element, in which a metal layer and a resin layer are separately laminated. Prepared carrier, a step of opening a through hole through the metal layer in the same arrangement as the electrode pads on the semiconductor element on the carrier, and a step of plating solder on the metal layer exposed on the through hole wall surface, Aligning the through hole and the electrode pad, and contacting the carrier and the semiconductor element; performing reflow while keeping the carrier and the semiconductor element in contact; melting the solder in the through hole; A method for manufacturing a semiconductor device, comprising a step of transferring solder onto a pad.

Here, the material used as the carrier is a material having a glass transition point higher than the solder reflow temperature in order to avoid deformation during reflow. More preferably, in order to completely transfer the solder in the through hole to the electrode pad on the semiconductor element at the time of reflow, a material in which liquid solder is hardly wetted, that is, a material having a critical surface tension smaller than the surface tension of liquid solder is used. It is desirable to form a carrier. In addition, in order to perform solder plating while maintaining integrity in the through holes formed in the carrier, the carrier is formed of a material that is easily wetted by the solder plating solution, that is, a material having a critical surface tension greater than the surface tension of the solder plating solution. It is desirable to do.

Further, according to the present invention (claim 2), the metal layer is patterned so as to lead out the electrode pads of the semiconductor element one-to-one to provide an enlarged test electrode pad. A method for manufacturing a semiconductor device according to claim 1 is provided.

Further, another aspect of the present invention (claim 2) is:
When the reflow is performed while the carrier and the semiconductor element are in contact with each other, the solder in the through hole is melted, and the solder is transferred onto the electrode pad on the semiconductor element. A step of testing the semiconductor device with the test electrode pads while maintaining an electrically connected state, and performing a reflow again to melt the solder in the through hole and transfer the solder to the electrode pads on the semiconductor device 3. A method for manufacturing a semiconductor device according to claim 2, further comprising the step of:

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.

The present inventors have been trying to manufacture fine solder bumps collectively on a bare semiconductor chip in the form of a pellet.
In order to carry out the burn-in test of this semiconductor chip, paying attention to the method of forming solder bumps, a method of solder plating into fine through holes and transferring it to electrode pads by melting this plated material is effective for the purpose. Has been found to act on.

An embodiment of the present invention will be described below. The present invention is not limited to the following embodiments, and can be used with various modifications.

FIGS. 1 to 6 show a first embodiment of a method of manufacturing a bump electrode on a semiconductor device according to the present invention.

First, a bare semiconductor chip 5 in the form of a pellet on which semiconductor elements as shown in FIG. 5 are formed is prepared. The semiconductor chip is not limited to silicon, but may be a compound semiconductor such as gallium arsenide or indium phosphide. The electrode pads 6 on the active element surface of the semiconductor element are made of aluminum, and the parts other than the electrodes 6 are covered with a passivation film 7. Note that the size of the semiconductor chip, the number of electrodes, and the electrode pitch can be arbitrarily set and can be appropriately selected.

Next, a stacked film 24 of a nickel film and a gold film serving as a barrier metal is formed on the semiconductor chip (FIG. 6). Here, the uppermost gold film functions as an antioxidant film for the nickel film, and a thickness of about 0.05 μm is sufficient.
With this thickness, even if the solder bumps are reflowed and gold diffuses into the solder, the characteristics of the solder are not affected.
The nickel film acts as a diffusion barrier for tin in the solder bumps. The film thickness is 0.2 μm considering the diffusion speed of tin.
I just need more.

These films are selectively formed only on aluminum electrodes by electroless plating. When electroless nickel plating using hypophosphorous acid as a reducing agent is performed on an aluminum electrode, aluminum itself is not catalytic for the oxidation reaction of hypophosphorous acid. . After uniformly forming zinc particles or nickel particles serving as catalyst nuclei on an aluminum electrode by a substitution reaction with aluminum, the film is immersed in a mixed solution of nickel sulfate and hypophosphorous acid at PH8 at PH8 for a predetermined time to form a film. A nickel film having a thickness of about 3 μm is formed. Then, the liquid temperature 85
Immersion in a mixed solution of potassium gold cyanide and potassium cyanide at 5.5 ° C. and PH 5.5 for a predetermined time, and a film thickness of about 0.0
A 5 μm gold film is formed.

Next, a carrier as shown in FIG. 1 is prepared. The carrier has a structure in which the conductive layer 2 is sandwiched between the resin 1 and the resin 3.
A 200 μm-thick polyimide film was used as the resin 1 and a 30 μm-thick polyimide was used as the resin 3. Polyimide has a critical surface tension that is less than the surface tension of molten solder, about 400 mN / m, and greater than the surface tension of the solder plating solution, about 20 mN / m. Further, a through hole 9 having a diameter of 40 μm is formed in this carrier at a position corresponding to the electrode pad 6 of the semiconductor chip, and the carrier end has a structure in which the copper foil 2 is exposed. FIG. 7 shows the carrier viewed from above.

This carrier can be formed, for example, as follows. First, a polyimide precursor 1 in a varnish state is coated on a polyimide film 1 having a conductive foil 2 serving as a base attached to the surface. After curing and curing the polyimide, the carbon dioxide laser was applied to a position corresponding to the electrode pad 6 of the semiconductor chip by 40 μm from both sides.
Drill holes. Thereafter, the copper foil 2 in the hole is etched to open a hole in the copper foil, and a through hole 9 is formed.

Next, the copper foil portion exposed on the wall surface of the through hole of the carrier formed as described above is subjected to solder plating. Solder plating is formed by an electroplating method in which the film forming speed is higher than that of electroless plating and the plating solution can be easily controlled. As the electroplating apparatus, a jet plating apparatus shown in FIG. 8 is used so that tin and lead ions in the plating solution can be sufficiently supplied into the through holes. The direction of the jet 11 of the plating solution is parallel to the through holes 9 of the carrier. So that In addition, solder plating solution 1
For 0, a sulfonic acid-based plating solution is used, and an appropriate amount of a surfactant is added so that the plating solution completely penetrates into the through holes, and the surface tension is adjusted to about 20 mN / m. Furthermore, the composition ratio of tin and lead in the film after plating is 6: 4.
The amounts of tin ions and lead ions are adjusted so that Also,
As the anode plate 12, a solder plate having a composition ratio of tin to lead of 6: 4 was used.

The cathode electrode 14 serving as a current supply source is brought into contact with the copper foil 2 exposed at the end of the carrier, and the anode electrode 1
3 is connected to the anode plate 12, and then a current is applied in the plating solution 10 to form the solder 4 in the through hole of the carrier (FIG. 2). Solder plating is performed until the deposited solder 4 completely fills the through hole. Since the solder is isotropically deposited from the end of the copper foil 2 in the through-hole, the height of the solder 4 in the through-hole at this time is about 40 μm, which is almost equal to the diameter of the through-hole.

The current density of the plating is 1.0 to 2.0 A / d
When performed at m ² , a dense plated film having a small composition distribution can be obtained, but the current density is maintained in the range of 1.0 to 2.0 A / dm ² because the cathode surface area changes with the deposition of solder. Therefore, it is preferable to control the plating current in accordance with the change in the area. Therefore, the plating current was analyzed by a simulation based on numerical calculation, and the time change of the cathode area was accurately obtained. As a result, the cathode area changes as shown by a in FIG. 9 with respect to the plating time, so that the plating current is reduced by b in FIG.
As shown in FIG.

Subsequently, the carrier formed as described above is brought into close contact with the semiconductor chip having the nickel and gold laminated film 24 formed on the electrode pads 6. In this case, the semiconductor chip 5 is placed on the lower surface of the carrier, and the through-hole filled with the solder of the carrier and the electrode pad 6 of the chip are aligned and brought into close contact with the resin layer 3 facing downward. Next, the solder 4 is reflowed while maintaining this state through a reflow furnace. Since the carrier has a critical surface tension smaller than the surface tension of the molten solder, the solder moves downward by its own weight during reflow, and comes into contact with the laminated film 24 on the electrode pads of the semiconductor chip. Since the uppermost layer of the laminated film 24 is formed of gold which is easily wetted by the solder, the contacted solder wets the entire electrode pad, and the solder and the electrode pad are completely connected (FIG. 3). Further, by separating the semiconductor chip from the carrier in a reflow furnace, the solder is transferred onto the electrode pads, and a semiconductor element having the spherical bump electrodes 8 formed thereon can be obtained (FIG. 4). At the time of reflow, a flux is previously applied to the carrier in order to remove a natural oxide film formed on the solder surface. The reflow temperature was set to, for example, 240 ° C.

As described above, the solder bumps can be collectively formed on the electrode pads of the pellet-shaped bare semiconductor chip. Note that the carrier used here can be reused by plating the solder again by the process shown in FIG. 2 after use.

Next, a second embodiment of the method for manufacturing a bump electrode on a semiconductor device according to the present invention will be described with reference to FIGS.

First, a carrier as shown in FIG. 10 is prepared. FIG. 14 shows the carrier as viewed from above. This carrier is similar to the carrier shown in FIG.
It has a shape in which the conductive layer 2 is sandwiched between the resin layer 1 and the resin layer 3. However, the conductive layer 2 is patterned, and the conductive layer 2 exposed in each through hole 9 is
, A pattern drawn independently to the carrier end is formed. In this case, the electrode 17 led out by the lead wire 18 is exposed from the resin layer 3, and the pitch of the electrode 17 is larger than the pitch of the through-hole 9. Probing is possible.

In this embodiment, the conductive layer 2 has a thickness of 9 μm.
A thick copper foil was used. A 200 μm thick polyimide film was used as the resin 1, and a 30 μm thick polyimide was used as the resin 3. Polyimide has a surface tension of molten solder of about 40.
It has a critical surface tension of less than 0 mN / m and greater than about 20 mN / m which is the surface tension of the solder plating solution. The diameter of the through hole 9 in the carrier was set to 40 μm and formed at a position corresponding to the electrode pad of the semiconductor chip.

This carrier can be formed, for example, as follows. First, a polyimide film 1 having a copper foil 2 serving as a base on the surface is prepared. This copper foil 2
A photosensitive resist film is formed thereon, and the resist film is processed into a shape of the lead line 18 by a photolithography technique. Thereafter, the copper foil 2 is etched and the resist film is removed, whereby the copper foil 2 is processed into the shape of a lead wire. Next, a polyimide precursor in a varnish state is coated on the copper foil 2 surface. After curing and curing this polyimide, a carbon dioxide laser was applied to the polyimide film from both sides at a position corresponding to the electrode pad of the semiconductor chip to a diameter of 40 μm.
Drill holes. Thereafter, the copper foil 2 in the hole is etched to open a hole in the copper foil, and a through hole 9 is formed.

Next, a portion of the copper foil 2 exposed on the wall surface of the through hole 9 of the carrier formed as described above is subjected to solder plating. Plating is performed using the same plating apparatus, plating solution and plating conditions as in the first embodiment. However, FIG.
The cathode electrode 14 in the plating apparatus shown in FIG.
Are electrically connected to all the electrodes 17 of the carrier shown in FIG. By performing plating in this manner, the solder plating 4 is filled in the through holes (FIG. 11).

Subsequently, a pellet-shaped bare semiconductor chip (FIG. 6) in which a nickel-gold laminated film 24 formed in the same manner as in the first embodiment was formed on the pad electrode 6 was prepared.
The carrier formed as described above is brought into close contact with this semiconductor chip. In this case, the semiconductor chip 5 is placed on the lower surface of the carrier, and the through-hole filled with the solder of the carrier and the electrode pad 6 of the chip are aligned and brought into close contact with the resin layer 3 facing downward. Next, the solder 4 is reflowed while maintaining this state through a reflow furnace. Since the carrier has a critical surface tension smaller than the surface tension of the molten solder, the solder moves downward by its own weight at the time of reflow and contacts the laminated film 24 formed on the electrode pads of the semiconductor chip. Since gold that easily wets the solder is formed on the uppermost layer of the laminated film 24, the contacted solder wets the entire electrode pad, and the solder and the electrode pad are completely connected (FIG. 12).

In this state, when taken out of the reflow furnace,
Since the thickness of the resin layer 3 is 30 μm and the height of the solder in the through hole is 40 μm, the conductive layer 2 in the carrier and the electrode pad 6 are mechanically and electrically connected. The carrier in this state is subjected to an appropriate screening process to screen the semiconductor chip. The energization of the semiconductor chip is performed by probing the electrode pads 17 on the carrier with a prober used for a normal energization test such as TAB. The screening process differs depending on the type of semiconductor chip, the difference in material, the use environment, and the application, and inspection is performed by applying thermal, mechanical, electrical stress, or the like as necessary. In this embodiment, a bare SRAM chip is used as a semiconductor chip, and a carrier electrode 17 is formed at 125 ° C.
By performing a burn-in screening in which a voltage equal to or higher than the rated maximum voltage is applied for one hour, a defective chip having an oxide film defect or the like can be selected and eliminated.

After the screening is completed, the semiconductor chip determined to be non-defective is again passed through a reflow furnace, and the carrier and the semiconductor chip are separated in the reflow furnace. As a result, the solder is transferred onto the electrode pads, and a semiconductor element on which the spherical bump electrodes 8 are formed can be obtained (FIG. 13). At the time of reflow, a flux is previously applied to the carrier in order to remove a natural oxide film formed on the solder surface. The reflow temperature was set to, for example, 240 ° C.

As described above, the screening of the pellet-shaped bare semiconductor chip can be performed, and at the same time, the solder bumps can be collectively formed on the electrode pads. It should be noted that the carrier used here can be reused by plating the solder again by the process shown in FIG. 11 after use.

FIG. 15 is a diagram comparing the completeness of the solder bumps formed by the conventional method and the solder bumps formed by the present invention with respect to the bump pitch. The sample chip is I
The number of evaluations is 20 for each using 100 I / O LSIs.
It was made into pieces. The completeness was evaluated by observing the shape of all the bumps after the bumps were formed and by electrically insulating them. In the drawing, sample a is a sample formed by the present invention, sample b is a sample formed by solder wire bonding, sample c is a sample formed by a solder ball supply method, and sample d is a sample formed by a screen printing method. I have.

As shown in FIG. 15, samples c and d were 2
Even at a pitch of 00 μm, many bumps were not formed, and it was difficult to form fine bumps. In the sample b, bumps could be formed with 100% integrity up to a pitch of 120 μm, but when the pitch was less than 100 μm, many short-circuits between bumps were observed after reflow. On the other hand, in the sample a according to the present invention, even at a pitch of 40 μm, 100
%, And proved to be an extremely excellent method for forming fine bumps.

FIG. 16 shows a sample in which a solder bump is formed by a wire bonding method and a sample in which a solder bump is formed by a forming method according to the present invention, after a high-temperature operating life test, for an SRAM having 100 I / Os. The result of totalizing and comparing bit defects is shown. In the figure, sample e shows a sample in which a solder bump was formed by a wire bonding method and screening was not performed, and sample f shows a sample in which a solder bump was formed by a forming method according to the present invention and burn-in screening was performed. The high-temperature operation life test was performed at a temperature of 125 ° C. by applying the rated maximum value to the power supply voltage. As a result, as shown in FIG.
In the meantime, a defect begins around 1 hour,
In sample f, no failure occurred until over 1000 hours.

Further, according to the bump manufacturing method of the present invention, a plurality of bumps can be collectively formed in a short time because plating and bump transfer are performed collectively. Therefore, when the I / O of the semiconductor chip is large, the production efficiency is extremely high as compared with the wire bonding method shown in FIGS. 17 to 20, which can greatly contribute to the reduction of the production cost. Further, in the plating step shown in FIG. 8, a plurality of carriers are provided in a plating tank, and the plurality of carriers are subjected to solder plating at the same time, whereby the production efficiency can be further improved.

It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with modifications without departing from the gist thereof. For example, an apparatus for plating a sample in a vertical state is used as a plating apparatus used for performing solder plating on a through hole in a carrier, but an apparatus for plating in a horizontal state may be used. Furthermore, the plating solution and plating conditions for plating the solder, the plating solution and plating conditions for electroless plating used for forming the barrier metal on the electrode pads, the reflow conditions, and the screening conditions depend on the material, shape,
It is desirable to change it appropriately depending on the function and the like.

The semiconductor chip, the barrier metal, the solder bumps, the resin of the carrier and the conductive layer can be used with various changes in the material, composition, dimensions and the like.
Further, it goes without saying that the method of manufacturing the carrier is not limited to the above-described example.

[0054]

As described above, according to the present invention,
When a solder bump is formed on an electrode pad of a semiconductor chip, a solder bump can be formed on a pellet-shaped semiconductor chip because a photolithography step is not required.

Also, high precision solder plating is selectively performed in a plurality of fine through holes, and the solder plating is collectively transferred onto a semiconductor chip to form bumps, thereby ensuring high productivity of fine solder bumps. It can be manufactured while.

Further, in the present invention, in the stage before separating the carrier and the semiconductor chip, the carrier having the independent electrodes corresponding to the respective electrode pads of the semiconductor chip is used as the carrier, so that the pellet-shaped semiconductor chip can be burned in. And can be screened,
The quality of the chip can be guaranteed in the same way as a chip in a conventional package.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating a first method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram illustrating a first method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a diagram illustrating a first method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a diagram illustrating a first method of manufacturing a semiconductor device according to the present invention.

FIG. 6 is a diagram illustrating a first method of manufacturing a semiconductor device according to the present invention.

FIG. 7 is a schematic view of a bump-forming carrier used in a first method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a schematic diagram of a solder plating apparatus used in manufacturing the semiconductor device of the present invention.

FIG. 9 is a diagram illustrating a method of controlling a plating current during solder plating used in manufacturing a semiconductor device according to the present invention.

FIG. 10 is a diagram illustrating a second method of manufacturing a semiconductor device according to the present invention.

FIG. 11 is a diagram illustrating a second method of manufacturing a semiconductor device according to the present invention.

FIG. 12 is a diagram illustrating a second method of manufacturing a semiconductor device according to the present invention.

FIG. 13 is a diagram illustrating a second method of manufacturing a semiconductor device according to the present invention.

FIG. 14 is a schematic view of a bump-forming carrier used in a second method for manufacturing a semiconductor device of the present invention.

FIG. 15 is a diagram comparing the integrity of a solder bump manufactured according to the present invention with a solder bump formed by a conventional method.

FIG. 16 is a diagram showing reliability test results of a semiconductor chip with solder bumps manufactured according to the present invention and a semiconductor chip with solder bumps formed by a conventional method.

FIG. 17 is a diagram illustrating a first method of manufacturing a conventional semiconductor device.

FIG. 18 is a diagram illustrating a first method of manufacturing a conventional semiconductor device.

FIG. 19 is a diagram illustrating a first method of manufacturing a conventional semiconductor device.

FIG. 20 is a diagram illustrating a first method of manufacturing a conventional semiconductor device.

FIG. 21 is a diagram illustrating a second method of manufacturing a conventional semiconductor device.

FIG. 22 is a diagram illustrating a second method of manufacturing a conventional semiconductor device.

FIG. 23 is a view illustrating a second method of manufacturing a conventional semiconductor device.

FIG. 24 is a view illustrating a second method of manufacturing a conventional semiconductor device.

[Explanation of symbols]

 1, 3, resin layer 2, conductive layer 4, solder 6, electrode pad 7, passivation film 8, bump electrode 9, through hole 10, plating solution 11, ... Plating solution flow 12 ... Anode plate 13 ... Anode electrode 14 ... Cathode electrode 15 ... DC power supply 16 ... Plating tank 17 ... Extraction electrode 18 ... Extraction line 19 ..Capillary 20 ... Solder wire 21 ... Print mask 22 ... Squeegee 23 ... Solder paste 24 ... Laminated film (barrier metal)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Yamada 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Production Technology Research Institute (72) Inventor Takashi Tsugasaki Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa 33 Toshiba Production Technology Research Institute Co., Ltd.

Claims (3)

[Claims] When a bump electrode is manufactured on an electrode pad on a semiconductor element, a carrier in which a metal layer and a resin layer are laminated is prepared separately, and the carrier is provided in the same arrangement as the electrode pad on the semiconductor element. A step of opening a through hole penetrating the metal layer, a step of plating solder on the metal layer exposed on the wall of the through hole, a step of aligning the through hole and the electrode pad, and contacting the carrier and the semiconductor element. A method of performing reflow while keeping the carrier and the semiconductor element in contact with each other, melting the solder in the through-hole, and transferring the solder onto the electrode pad on the semiconductor element. . 2. The semiconductor according to claim 1, wherein the metal layer is patterned so as to draw out the electrode pads of the semiconductor device one-to-one and provide an enlarged test electrode pad. Device manufacturing method. 3. A reflow process is performed while keeping the carrier and the semiconductor element in contact with each other to melt the solder in the through hole and transfer the solder onto the electrode pad on the semiconductor element. A step of testing the semiconductor element with the test electrode pads while maintaining the state in which the upper electrode pads are electrically connected, and performing a reflow again;
3. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of melting the solder in the through-hole and transferring the solder to an electrode pad on the semiconductor element.