JP2000122898A - Method and device for simulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To estimate a target execution time in cross environment wherein a target to be developed is absent by estimating the target execution time according to the time of the execution of a program to be measured by a host and a target/host performance ratio. SOLUTION: A program A for a target is read in target memory information 19 of a simulation device 10 and executed by a target execution route 14 to obtain a clock number, and an execution time is found from the clock number and the clock cycle determined by design. Then the performance ratio of the target and host is found from the target execution time and host execution time. A program for the host is generated through a target/host converting process from a program (measured program) A for simulation and executed by the host 11 to find the host execution time (measured program execution time) and the target execution time is estimated by referring to the target/host performance ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation method and apparatus, and more particularly, to a target system (hereinafter abbreviated as a target) and a host system (hereinafter abbreviated as a target).
A central processing unit (C) of a different type
PU) in a cross development environment.

[0002]

2. Description of the Related Art Conventionally, there has been known a simulation method for simulating the operation of a target in a cross development environment in which a target to be developed and a host are composed of different types of central processing units (CPUs).

As described above, the target and the host CPU
Are different, two methods are used to run the target object program on the host. The first method is to read the object program into software that performs the same processing as a CPU (hereinafter, abbreviated as a target CPU) that configures the target, and to perform the processing. The object program is converted into a host object program and operated.

In the first method, a program execution time can be obtained in clock units by simulating the state of the target CPU (states of registers, pipelines, cache memories, etc.) in clock units. However, since the state of the CPU in clock units is managed by software, the time required for the execution is 100 to 1000 times or more as long as the processing is actually performed by the target CPU.

[0005] As described above, the fact that a long time is required for the simulation not only imposes a great burden on a program developer, but also increases the development cost.

On the other hand, in the second method, since the program is directly executed by the host CPU, the processing can be basically completed at a high speed. This second
A conventional simulation method according to the above method is described below.

FIG. 3 is an explanatory diagram showing a flow of a simulation by a conventional simulation method. As shown in FIG. 3, first, the target program A is converted into a host computer program B by target / host conversion. That is, if the program A is for the target, the program A cannot be executed on the host, so that the instruction is changed to the host program B so that the program A can be executed on the host.

Next, the converted program B is executed by a host computer, and a host execution time b is obtained. Based on the host execution time b, a target execution time is estimated by referring to a target / host performance ratio which is a general performance ratio between the target computer and the host computer, and a target execution time estimate a is obtained.

[0009]

However, in the case of this simulation method, it has not been possible to obtain an accurate estimate of the program execution time. That is, since the execution time of each instruction on the target CPU changes depending on the state of the pipeline, the cache memory, and the like, and it is not known which part is executed and how many times, the execution time is obtained in advance. It is difficult. In addition, since the performance ratio of each instruction of the target object program and the converted host object program varies, the execution time cannot be simply estimated from the specification performance ratio of the target CPU and the host CPU. .

This variation in the performance ratio is due to the following reasons. First, even if instructions for the host correspond to instructions for the target, the execution time ratio of these instructions is not necessarily the same for all instructions. Next, when there is no instruction equivalent to the instruction for the target on the host, a routine consisting of a plurality of instructions of the host CPU that simulates the instruction of the target CPU must be called. The performance ratio greatly changes between the case and the case where the simulation routine needs to be called. Further, a process for converting addresses may be inserted due to a difference in memory configuration, and the performance ratio greatly changes depending on whether or not the conversion process is performed.

That is, in the target computer and the host computer, the special processing and the poor processing do not match, and the ratio of the special or poor processing differs depending on each program. Therefore, the target / host performance ratio is set to a constant value. Difficult to represent. In addition, the difference between the ratio of general strength or weakness and the rate of strength or weakness for each program lowers the accuracy of the performance ratio.

Therefore, the target execution time estimate a obtained by the above-mentioned conventional simulation method is
This is obtained by using the target / host performance ratio, which is a general performance ratio of the computer, which is irrelevant to the target program A, and it is inevitable that the estimation accuracy deteriorates.

Such a simulation method is also disclosed in the specification of Japanese Patent Application No. 10-081010 filed by the present applicant.

An object of the present invention is to provide a simulation method and apparatus capable of obtaining a target execution time estimation that accurately captures the characteristics of a target program in a cross development environment in which there is no target to be developed. is there.

[0015]

In order to achieve the above object, a simulation method according to the present invention converts a target instruction into a host instruction, performs a simulation, obtains a host execution time, and processes the host execution time with target hardware. A target instruction execution time is obtained by simulating a target instruction with software that performs the same processing as that described above, and a target / host performance ratio is obtained from the two execution times. Based on the host performance ratio,
Calculating a target execution time estimate when the program to be measured is executed on the target.

With the above configuration, the target instruction is converted into a host instruction, a simulation is performed to determine the host execution time, and the target instruction is simulated by software that performs processing equivalent to processing by the target hardware. The target / host performance ratio is calculated from the two execution times, and the target / host performance ratio is calculated based on the target / host performance ratio and the program execution time when the program to be measured is executed on the host.
A target execution time estimate when the program to be measured is executed on the target is required. As a result, in a cross-development environment where there is no target to be developed, an estimate of the target execution time that accurately captures the characteristics of the target program can be obtained in a short time.

Further, the above simulation method can be realized by the simulation device according to the present invention.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a simulation apparatus according to an embodiment of the present invention. As shown in FIG. 1, the simulation apparatus 10 has a host CPU 11 constituting a host, and a host memory 12, and a simulation program 13 is stored in the host memory 12.

With this simulation apparatus 10, in a cross development environment in which a target to be developed and a host are composed of different types of central processing units (CPUs),
Even when the target does not exist, the operation of the target can be simulated based on the program A for the target.

By executing the simulation program 13, each of the target execution routine 14, the state change (debugger) routine 15, the register information 16, the pipeline information 17, the cache memory information 18, and the target memory information 19 is stored in the host memory 12. An area is reserved.

The target execution routine 14 is a program for creating a target state (register information, pipeline information, cache memory information, target memory information, etc.) at the next clock from the current target state. The number of times
The number of clocks required for target execution can be found. That is, by simulating the state of the target CPU in clock units, the execution time of the program can be obtained in clock units.

By this target execution, the register and the target memory / cache memory are updated based on each instruction on the pipeline, and a new instruction is read from the target memory if the pipeline can execute a new instruction. When reading, the cache memory is updated. Finally, create the next pipeline state.

The state change (debugger) routine 15 is composed of a program for the user to manipulate the target state, so that the user can change the state of the target in a debugging operation or execute the target program for executing the target program. Each element of the state can be initialized. This initialization includes the operation of placing the program to be executed in the target memory.

The register information 16 is a place for storing a value stored in a register of the target CPU to be simulated, and the pipeline information 17 is a part of the pipeline in which the target CPU to be simulated is processing. This is where you save your progress. In order to simulate the parallel processing by the pipeline, it is necessary to know whether the processing in the pipeline can be performed without delay.

The cache memory information 18 is provided for the target CPU to be simulated, or stores information such as the location of the memory cached in the cache memory connected to the target CPU. Location.

Data newly read by the CPU is simultaneously written into the cache memory, and when the CPU next reads data, if there is necessary data in the cache memory, the data is read from the cache memory. This allows
The number of accesses to the main memory is reduced. In other words, if the necessary information is stored in the cache memory at that time, the process is fast, but if it is not, the slow memory must be accessed and temporarily waited, so the process becomes slow, so when estimating the execution time It is necessary to record where necessary data is stored.

The target memory information 19 is a place where the contents stored in the target CPU to be simulated or stored in the memory connected to the target CPU are stored. The program whose execution time is to be estimated is placed here.

FIG. 2 is an explanatory diagram showing a flow of a simulation using the simulation apparatus of FIG. FIG.
As shown in (1), first, a host execution time b by host execution and a target execution time a by simulation are obtained from the target program A to obtain a target / host performance ratio. Next, based on the simulation purpose program A ', the target execution time is estimated with reference to the target / host performance ratio to obtain a target execution time estimate a'.

The host execution time b due to execution of the host is obtained by obtaining the host program B from the target program A by the target / host conversion process, and then executing the host program B on the host. , By converting a target instruction into a host instruction and performing a simulation.

The estimation of the target execution time by this simulation is performed in a targetless environment. However, if the program is for a target, the program cannot be executed by the host. The host program B is created by changing the instruction.

The target execution time a by the simulation is obtained from the target program A by simulating the target operation, that is, by simulating the target instruction with software that performs the same processing as that performed by the target hardware. Can be At the time of the simulation, the target program A is read into the target memory information 19 of the simulation apparatus 10 and executed by the target execution routine 14 to obtain the number of clocks. The execution time is determined by the number of clocks and the clock cycle determined by design. You can ask.

That is, by executing a simulation including the operation state of the target only once, the program A
, An accurate target execution time a is obtained.

From the two execution times, the target execution time a and the host execution time b, the performance ratio between the target and the host is determined. This performance ratio is not the ratio of various instructions alone incorporated in the program, but the ratio of the entire program.
The exact performance ratio of the target to the host in this program can be determined.

The program A 'for simulation (program to be measured) A' is created by modifying or modifying the program A (creation source program) in accordance with an unfinished target system according to the specifications desired by the user. After creating a host program B 'from the simulation purpose program A' by target / host conversion processing, the host program B 'is executed on the host, and the host execution time (measured program execution time) b'
Ask for.

Based on the host execution time b ', the target execution time is estimated by referring to the target / host performance ratio obtained previously, and the target execution time estimate a' is obtained.

Therefore, the exact number of clocks is obtained by simulation, and the program A
Program A partially modified from Program A because the target / host performance ratio in the characteristics of
'Can be more accurately estimated.

As described above, according to the present invention, in the cross development environment where no target is present, the target / host performance ratio is measured once and the host executes the program A only by executing the program A. From b 'and the target / host performance ratio, the target execution time a' of the program A 'obtained by remodeling or modifying the program A can be estimated at high speed and with high accuracy.

In other words, the execution time of the program B 'obtained by subjecting the program A' to target / host conversion is very short because it is directly executed on the host computer to obtain the processing result. In addition, since the target / host performance ratio is not the ratio of the instruction itself but the ratio of the entire program, the flow of the program was grasped compared to the conventional case where the performance ratio was determined by the instruction alone. Based on the more accurate performance ratio, the target execution time a 'can be accurately estimated.

As a result, when performing program adjustment such as execution time reduction, the degree of necessary adjustment and the effect after adjustment become clear, and the man-hour can be reduced.

That is, if the execution time of the program is to be shortened without knowing the execution time of the entire program accurately, how much should be adjusted, and how much adjustment is possible or impossible based on the initial specification. Since it is necessary to check the adjustment results individually without performing any adjustments, the adjustment man-hours are very long. However, by accurately estimating the execution time, it is possible to clarify the degree of adjustment required and the effect after adjustment.

Also, simulating the target time requires a great deal of labor, for example, it takes 1000 times longer, and places a great burden on the developer and increases the development cost. In addition, in order to obtain accuracy, the actual measurement is performed only once, and based on the result, an accurate estimation of the execution time for the subsequent program correction is obtained, thereby reducing the burden on the developer and reducing the development cost. Can be reduced.

The target execution routine and various information shown in FIG. 1 are partially used in an electronic circuit simulation / logic circuit simulation using an electronic (logical) circuit simulator for simulating an electronic (logical) circuit of the target CPU, and a combination thereof. Alternatively, the whole can be replaced. For example, the part of the target execution routine that creates pipeline information for the next clock and the pipeline information can be replaced with an electronic (logic) circuit simulator that simulates the pipeline and circuits such as arithmetic units that constitute the pipeline.

[0044]

As described above, according to the present invention,
A target / host performance ratio is obtained from a target execution time and a host execution time by a simulation for the target, and the target program is measured based on the target / host performance ratio and the program execution time when the target program is executed on the host. Since a target execution time estimate in the case of execution is required, in a cross development environment where there is no target to be developed, an estimate of the target execution time that accurately captures the characteristics of the target program can be obtained in a short time.

As a result, when performing program adjustment such as execution time reduction, the degree of necessary adjustment and the effect after adjustment become clear, the man-hour can be reduced, and the accurate execution time for program correction can be reduced. By obtaining the estimate, the burden on the developer can be reduced and the development cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a simulation device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a flow of a simulation using the simulation device of FIG. 1;

FIG. 3 is an explanatory diagram showing a flow of a simulation according to a conventional simulation method.

[Explanation of symbols]

 Reference Signs List 10 simulation apparatus 11 host CPU 12 host memory 13 simulation program 14 target execution routine 15 state change (debugger) routine 16 register information 17 pipeline information 18 cache memory information 19 target memory information A target program A ′ simulation target program B Host program B 'Host program a Target execution time a' Target execution time estimation b Host execution time b 'Host execution time

Claims (6)

[Claims] 1. A target instruction is converted to a host instruction, a simulation is performed to determine a host execution time, and a target instruction is simulated by software that performs processing equivalent to processing by target hardware, and the target execution time is calculated. From the two execution times,
A process of obtaining a host performance ratio; and a process of obtaining a target execution time estimate when the measured program is executed on the target based on the measured program execution time of executing the measured program on the host and the target / host performance ratio. A simulation method comprising: 2. The simulation method according to claim 1, wherein the performance ratio is obtained by using a program from which the program to be measured is created by modifying or modifying the program. 3. The simulation method according to claim 1, wherein the target to be developed and the host are used when there is no target in a cross development environment including different types of central processing units. 4. A target instruction is converted into a host instruction, a simulation is performed to determine a host execution time, and the target instruction is simulated by software that performs processing equivalent to that performed by target hardware, and the target execution time is calculated. From the two execution times,
A simulation function is provided for obtaining a host performance ratio, and for estimating a target execution time when the measured program is executed on the target, based on a program execution time of executing the measured program on the host and the target / host performance ratio. A simulation device characterized by the above-mentioned. 5. The simulation apparatus according to claim 4, further comprising storage means for storing a simulation program having the simulation function. 6. The simulation program includes a target execution routine unit for simulating the state of the target CPU in clock units, a state change routine unit for changing the target state by a user operation, and a target CPU for simulating. A register information section that stores the values stored in the registers, a pipeline information section that stores the progress of the pipeline being processed by the simulated target CPU, and a location where the memory is cached. The simulation apparatus according to claim 5, further comprising: a cache memory information section that stores information; and a target memory information section that stores contents stored in a memory of a program or the like whose execution time is to be estimated.