JP2000122867A - Trap processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the delay for protecting the contents of registers by calling an exception handler when an instruction includes a synchronism exception before the specific execution time of a prefetch instruction. SOLUTION: When a software trap instruction is detected by a CF-DET unit, the internal exception mark bit in an instruction logic unit which corresponds to the instruction is set and a software trap number is stored corresponding to the trap instruction. An IFU 102 prefetches and puts a trap handler in an MBU lower instruction stream buffer and a logic unit sends the exception mark bit of the instruction set to an IEU 104 and reports which instruction in the instruction set is already judged to be the generation source of the synchronism exception in such a case. The IEU 104 does not respond immediately and all the instructions in the instruction set are scheduled by an ordinary method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to microprocessor architectures, and more particularly, to handling interrupts and exceptions in a microprocessor.

[0002] The description in this specification is based on the description in the specification of US Patent Application No. 07 / 726,942, which is a priority document of the present application. The contents of the description of the United States patent application form a part of the present specification.

[0003]

BACKGROUND OF THE INVENTION Cross-Reference to Related Patent Applications The U.S. patent applications listed below are filed concurrently with the present patent application,
Although pending, the matters disclosed in these U.S. patent applications and disclosed in correspondingly filed Japanese patent applications, are referenced in their application numbers herein. And thereby constitute a part of the present specification. 1. Title of invention "High performance RISC microprocessor
Architecture "(High-Performance)
RISC Microprocessor Arch
item) SMOS7984 MCF / GB
R, US patent application Ser. No. 07 / 727,006, 1991.
Filed on July 8, 2012, filed by the inventor Le T. Nguyen et al. And Japanese Patent Application No. 5-502150 (Japanese Patent Application No.
-501122). 2. Title of the Invention "Extensible RISC Microprocessor Architecture"
Microprocessor Architect
ure) SMOS 7895 MCF / GBR, U.S. patent application Ser. No. 07 / 727,058, filed Jul. 8, 1991, inventor LeT. Nguyen et al. And corresponding Japanese Patent Application No. 5-502153 (Japanese Patent Application No. Hei 6-5011).
No. 24). 3. "RISC with isolated architectural dependencies
Microprocessor Architecture ”(RISC M
microprocessor Architecture
e with isolated Architecture
ural Dependencies) SMOS 79
87 MCF / GBR, US patent application Ser.
No. 744, filed on Jul. 8, 1991, inventor LeT.
Nguyen et al. And corresponding Japanese Patent Application No. 5-50.
2152 (Japanese Unexamined Patent Publication No. 6-502034). 4. Title of Invention "R Using Multiple Register Set"
ISC Microprocessor Architecture ”(RIS
C Microprocessor Architectec
cure Implementing Multipl
e Typed Register Sets) SMOS
7988 MCF / GBR / RCC, U.S. Patent Application No. 07 / 726,773, filed July 8, 1991, inventor Sanjiv Garg et al. No.). 5. Title of Invention "Single Chip Page Printer Controller" (Single Chip Page)
Printer Controller) SMOS
7991 MCF / GBR, US patent application Ser. No. 07/72.
No. 6,929, filed on Jul. 8, 1991, inventor Der
ek J. Lentze et al. And Japanese Patent Application No. 5-502149 corresponding thereto (Japanese Patent Application Laid-Open No. 6-501586). 6. Title of the invention "Microprocessor architecture capable of supporting multiple heterogeneous processors"
(Microprocessor Architect
ure Capable of Supporting
Multiple Heterogeneous Pr
processors) SMOS 7992MCF / WM
B, U.S. patent application Ser. No. 07 / 726,893, 1991.
Filed on July 8, 1980, filed by the inventor Derek J. Lentze
Others and corresponding Japanese Patent Application No. 5-502151 (Japanese Patent Application No. 6-501123).

Description of the Related Art In a typical microprocessor, instructions are usually executed in order unless an instruction that changes the flow of control appears or an exception occurs. With respect to exceptions, mechanisms are incorporated to change the flow of control when a particular event occurs, regardless of whether the event occurred in relation to a particular instruction in the instruction stream. For example, a microprocessor may include an interrupt request (IRQ) read (1head), which when activated by an external device causes the microprocessor to indicate the address of the next instruction to be executed. Save some information about the current state of the machine, including
Then, immediately, the interrupt handler (1 interrupt)
hander),
The interrupt handler starts at a predetermined address. In another example, during execution of a particular instruction, a division-by-zero may occur.
When an exception error occurs, the microprocessor saves information about the current state of the machine and then passes control to the exception handler. In another example, certain microprocessors provide a "software trap" instruction in each instruction set. Again, the microprocessor saves information about the current state of the machine and then passes control to the exception handler. The terms interrupt, trap, fault, and exception as used herein are used interchangeably.

[0005] In some microprocessors, when an interrupt occurs externally, the microprocessor passes control to the entry point of the same interrupt handler. There are multiple external devices,
If those devices can activate an interrupt request read, the interrupt handler must first determine which device caused the interrupt and then give control to the piece of code that handles that particular device. For example, the Intel 8048 microprocessor has an I
It includes an NT input which, when activated, causes the microcontroller to pass control to absolute memory location 3. 8048 also includes a RESET input which, when activated, causes the microcontroller to transfer control to the absolute memory.
Pass it to location 0. It also contains an internal timer / counter, which causes control to be passed to absolute memory location 7 when it causes an interrupt.

Other microprocessors include an "interrupt level" read in addition to the interrupt request read. In these microprocessors, when an external device activates an interrupt request read, it also sends out a trap number unique to that particular device on the interrupt level line. In response, the microprocessor's internal hardware takes control, that is, the "vector" of one of a plurality of interrupt handlers, each corresponding to a different trap number.
Pass to one. Similarly, some microprocessors have only one entry point predefined for all routines written to handle internally raised exceptions, while others have A mechanism is provided for automatically passing vectors to routines that depend on the trap number defined for each particular type of possible internal exception.

Conventionally, when a vector is passed to an interrupt handler and an exception handler, several methods have been used to determine the entry point of the corresponding handler.
In one approach, an address table is created starting from a particular table base address, and the base address is fixed or user-definable. Each entry (item) in the table has the same length as the address, for example, 2 bytes or 4 bytes, and contains the entry point for the corresponding trap number. When an interrupt or exception occurs, the microprocessor first determines the base address of the table, adds m times the trap number (where m is the number of bytes in each entry), and then calculates The information stored at the address is loaded into the program counter (PC), and control is passed to the routine starting from the address specified in the table entry.

In other microprocessors, instead of storing only the address of the handler, the entire branch instruction is stored in each entry in the table. The number of bytes in each entry was equal to the number of bytes in the branch instruction. Upon receiving an interrupt or exception, the microprocessor first determines the table base address,
All that was required was to add the m times the trap number and load the result into the program counter. The first instruction executed after that was a branch instruction in the table, which ultimately passed control to the exception handler.

[0009]

Neither of the above techniques for passing a vector to a handler has a delay (latency) since the preliminary operation must be performed before the operation portion of the handler can begin execution. is happening. In the first approach, the entry point address could not be loaded into the program counter without first retrieving the entry point address from the table. 2
In the second approach, a critical portion of the handler could only begin executing after fetching and executing a preliminary branch instruction. The addition delay that occurs during the calculation of adding the m times the trap number to the table base address is caused by concatenating the trap number with the upper bits from the base address as the lower bits, followed by the lo
g ₂ m can be avoided by just continuing m zero bits,
The delay caused by the preliminary operations described above remained. Such a delay may be a hindrance in a system where response time (response time) for processing a certain type of interrupt is important.

Another problem associated with exception handling in conventional microprocessors is that when the trap handler returns to the main instruction flow, the "machine state" (s
This is related to the amount of information that needs to be stored so that the state of machine can be restored. There is a trade-off between the need to store as much information as possible and the need to minimize delays when dispatching to a trap handler. In particular, for the on-chip data registers, do not store any of the on-chip data registers, leave the data to each register temporarily, and leave it to the handler. Techniques were used to allow the handler to be used for its own purposes. In this case, the handler had to replace the data in the register before returning. In this case, the operation of the handler can be significantly slowed down because these registers need to be stored and restored. In another approach, the hardware automatically stores the contents of the registers on the stack before passing control to the handler. This method is also inappropriate because it complicates the hardware and can significantly delay the transfer of control to the handler. Therefore, with the vector approach described above, the delays that occur in existing approaches to protect the contents of registers when a trap handler is invoked are unacceptable in high performance microprocessors.

[0011]

SUMMARY OF THE INVENTION In accordance with the present invention, a microprocessor architecture is employed which overcomes many of the problems described above in known systems. In particular,
A "fast trap" exception dispatching technique is employed. According to this approach, the entire handler can be stored in a single vector address table entry. Each table entry must have at least 2
Microprocessor, and preferably more, to store more instructions, so when a fast trap occurs, the microprocessor bases the trap number on m times.
It is only necessary to branch to the address obtained by connecting to the address. The time delay required to fetch the entry point address from the table or to fetch and execute the preliminary branch instruction is eliminated. The microprocessor may also incorporate other time-inefficient vector techniques for less important types of traps.

In another form of the invention, when a trap occurs, the processor enters an interrupt state, which automatically shifts some shadow registers to the foreground and shifts the corresponding set of foreground registers to the background. Shift to (background). Register contents are not transferred; instead, shadow registers are only made available instead of regular registers. Thus, the handler will have a set of registers available immediately, without having to worry about corrupting the data needed for the main instruction stream.

US patent application Ser. No. 07 / 727,00, cited above.
No. 6, PCT / JP92 / 00868, entitled "High-Performance RISC Microprocessor Architecture" (High-Performance RISC)
Microprocessor Architecture
e) (Japanese Unexamined Patent Publication No. 6-501122) states that an advanced microprocessor that prefetches an instruction before execution can process an out-of-order instruction prefetch request return, and that two or more instructions are executed during the same execution time. And that instructions can be executed out of order on a sequence of instructions in the instruction stream. Another aspect of the present invention incorporates a mechanism for maintaining the accuracy of synchronous exceptions that have occurred for an instruction before and during execution of the instruction.

The microprocessor architecture described in the above-mentioned patent application further incorporates a mechanism for processing another procedure-relay instruction flow called from a procedural or emulation instruction in the main instruction flow. ing. Transfer of control to the procedural instruction flow is performed by a separate emulation prefetch queue without flushing any instructions already prefetched in the main instruction flow. According to another aspect of the present invention,
The interrupt state remains available, regardless of whether the processor is executing from the main or procedural instruction stream, and the processor returns to either instruction stream when returning from the trap. It has a sign indicating what to do. In addition, separate prefetch program counters are maintained for the main and emulation instruction streams, and the processor
Store only the prefetch PC from the current instruction stream when the handler is called, and restore the prefetch PC to the correct prefetch program counter when the handler returns.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. I. Overview of microprocessor architecture II. Instruction fetch unit A) IFU data path B) IFU control path C) IFU / IEU control interface D) Details of PC logic unit 1) Details of PF and ExPC control / data unit 2) Details of PC control algorithm E) Interrupt and exception handling 1) Overview 2) Asynchronous interrupt 3) Synchronous exception 4) Handler dispatch and return 5) Nest 6) Trap list III. Instruction execution unit A) Details of IEU data path 1) Details of register file 2 3) Floating point data path details 4) Boolean register data path details B) Load / store control unit C) IEU control path details 1) E decode unit details 2) Carry Details of checker unit 3) Data dependency More 4) Details 5 of the register rename unit) Details IV details 9) Bypass Control Unit Detail 8) Control Flow Control Unit Detail 7) saving control unit Details 6) completion control unit of the instruction issue unit of the checker unit. Virtual memory control unit Cache control unit VI. Summary and conclusions Overview of Microprocessor Architecture FIG. 1 provides an overview of the architecture 100 of the present invention. An instruction fetch unit (IFU) 102 and an instruction execution unit (IEU) 104 are the core functional elements of the architecture 100. Virtual memory unit (VMU) 108, cache control unit (CU)
U) 106, and a memory control unit (MCU) 11
0 is for directly supporting the functions of the IFU 102 and the IEU 104. The memory array unit (MAU) 112 is for operating the architecture 100 as a basic element. However, MAU 112 does not exist directly as one integral component of architecture 100. That is, in the preferred embodiment of the present invention, IFU 102, IEU1
04, VMU 108, CCU 106, and MCU 11
0 is the conventional low power CMOS with 0.8 micron design rule
It is mounted on a single silicon chip using a process and is composed of about 1,200,000 transistors. The clock speed of a standard processor or system of the architecture 100 is 40 MHz. However, according to a preferred embodiment of the present invention, the internal clock speed of the processor is 160 MHz.

The basic role of the IFU 102 is to fetch instructions and buffer the instructions while execution by the IEU 104 is pending, typically to the next virtual address used when fetching the next instruction. Is to calculate

In the preferred embodiment of the present invention, each instruction is fixed at 32 bits in length. Instruction set, that is, 4
A "bucket" of instructions consists of C
The data is simultaneously fetched from the instruction cache 132 in the CU 106 by the IFU 102 via the instruction bus 114 having a width of 128 bits. The transfer of the instruction set is performed between the IFU 102 and the CCU 106, adjusted by a control signal transmitted via the control line 116. The virtual address of the fetched instruction set is transferred to the IFU 10 via the bus 118, which also serves as IFU arbitration, control and address.
2 and further out on an arbitration, control and address sharing bus 120 which couples between the IEU 104 and the VMU 108. Arbitration of access to VMU 108 (ar
bitration) is between the IFU 102 and the IEU 104
Are performed by using the VMU 108 as a common shared resource. In the preferred embodiment of the present invention, the lower bits defining the address in the physical page of the virtual address are transferred from IFU 102 directly to cache control unit 106 via control line 116. IFU
The virtual upper bits of the virtual address given from the VMU 10
8 where it is converted to the corresponding physical page address. In IFU 102, this physical page address is used by VMU1 for half an internal processor clock cycle after the translation request is issued to VMU 108.
08 is transferred directly to the cache control unit 106 via the address control line 122.

The instruction stream fetched by IFU 102 is transmitted via instruction stream bus 124 to I
It is passed to the EU 104. The control signal is transmitted to control line 126
Are exchanged between the IFU 102 and the IEU 104 via the. In addition, certain instruction fetch addresses, such as those requiring access to a register file residing in the IEU 104, may be accessed via the target address return bus in control line 126 via the I
It is sent back to FU102.

The IEU 104 stores data to and retrieves data from the data cache 134 provided in the CCU 106 through an 80-bit wide bidirectional data bus 130. The entire physical address at which the IEU accesses data is passed to the CCU 106 by the address portion of the control bus 128. Also, a control signal for managing data transfer is transmitted through the control bus 128 to the IEU.
Communication between the CCU 104 and the CCU 106 is also possible. The IEU 104 assigns the virtual data address to CCU1
The VMU 108 is used as a resource for changing to a physical data address suitable for passing to the H.06. The virtualized portion of the data address is passed to the VMU 108 via the arbitration, control and address bus 120. IFU1
02, the VMU 108 transfers the corresponding physical address via the bus 120 to the IEU 104
Return to In a preferred embodiment of the architecture 100,
The IEU 104 uses physical addresses to ensure that load / store operations are being performed in the correct program stream order.

The CCU 106 has a conventional high-level function of judging whether a data request defined by a physical address can be satisfied from the instruction cache 132 or the data cache 134, whichever is applicable. If the access request is correctly satisfied by accessing the instruction cache 132 or the data cache 134, the CCU 106 coordinates the data transfer via the data buses 114, 130 and performs the transfer.

If the data access request cannot be satisfied from the instruction cache 132 or the data cache 134, the CCU 106 stores the corresponding physical address in the MC.
Pass to U110, determine whether MAU 112 is requesting read or write access,
The IFU 102 or IEU 104 provides sufficient control information and request operations to identify the source or destination cache 132, 134 of the CCU 106 for each request.
Additional identification information for association with the final data request issued by the RP is also passed.

The MCU 110 preferably includes a port switch unit 142, which is connected to the instruction cache 132 of the CCU 106 by a one-way data bus 136 and a two-way data bus 1
38 is connected to the data cache 134. The port switch 142 is basically a large multiplexer, allowing the physical address obtained from the control bus 140 to be sent to any of a plurality of ports (P ₀ -P _n ) 146 _{0 -n} , and Kara evening bus 1
36, 138. M
Each memory access request handled by CU 110 is associated with one of ports 146 _{0-n for} the purpose of arbitrating access to main system memory bus 162 required when accessing MAU 112. When a connection for data transfer is established, the MCU 110 passes control information to the CCU 106 via the control bus 140 and communicates with the instruction cache 132 or the data cache 134 via the corresponding one of the ports 146 _0-n. MAU
The transfer of data to / from 112 is started. In a preferred embodiment of the architecture 100, the MCU 110 includes:
Actually, data that is being transferred between the CCU 106 and the MAU 112 is not stored or latched. This minimizes the transfer latency and minimizes MCU 110
In order to avoid having to track or manage only one piece of data.

II. Instruction fetch unit Figure 2 shows the main elements of the instruction fetch unit 102
Shown in In order to facilitate understanding of the operation and interrelationship of these elements, the following description will be made in consideration of the case where these elements are involved in the IFU data path and control path.

A) IFU Data Path The IFU data path begins with the instruction bus 114 which receives the instruction set and temporarily stores it in the prefetch buffer 260. The instruction set from prefetch buffer 260 is passed through I decode unit 262 to IFIFO unit 264. Instruction FIFO2
The instruction set stored in the last two stages of 64 is:
The data can be continuously taken out to the IEU 104 through the data buses 278 and 280 for use.

Prefetch buffer unit 260
Receives one instruction set from the instruction bus 114 at a time. The complete 128-bit wide instruction set is typically stored in the main buffer (MB
UF) 188 portion is written in parallel to one of the four 128-bit wide prefetch buffer locations. The additional instruction set is the same for up to four, two 128-bit wide target buffers (TBUF) 1
90 prefetch buffer locations or two 128-bit wide procedure buffers (EBUs)
F) It is possible to write to the 192 prefetch buffer location. Preferred Architecture 100
Then, MBUF188, TBUF190 or EBUF
Instruction sets located at any of the prefetch buffer locations in 192 can be transferred to the prefetch buffer output bus 196. Furthermore, direct fall through (fall through)
h) Instruction set bus 194 connects MBUF 188, TBUF 190 and EBUF by connecting instruction bus 114 directly to prefetch buffer output bus 196.
This is for bypassing the BUF192.

In the preferred architecture 100, the MBUF
188 is used to buffer the instruction set in the nominal or main instruction stream. TBUF190
Is used to buffer the instruction set prefetched from the trial target branch instruction stream. As a result, through the prefetch buffer unit 260, both instruction streams that may be located after the conditional branch instruction can be prefetched. With this function, even if the waiting time of the MAU 112 becomes longer, at least the CCU 112
The subsequent access latency to the conditional branch instruction is eliminated, so the correct next instruction set after the conditional branch instruction is obtained regardless of which instruction stream is ultimately selected when resolving the conditional branch instruction. And can be implemented. In the preferred architecture 100 of the present invention, M
Because of the BUF 188 and the TBUF 190, the instruction fetch unit 102 can prefetch both possible instruction streams and is assumed to be correct, as described below in connection with the instruction execution unit 104. Instruction stream can continue to be executed. When the conditional branch instruction is resolved, the correct instruction stream is prefetched and the MBUF1
If entered at 88, the instruction set remaining in TBUF 190 is only invalidated. On the other hand, if the instruction set for the correct instruction stream is present in TBUF 190, instruction prefetch buffer unit 260
Through these buffer sets directly from the TBUF 190, in parallel, with each buffer in the MBUF 188.
Transferred to location. Before that, MBUF188
Are effectively invalidated by overwriting the instruction set transferred from the TBUF 190. TBU to be transferred to MBUF location
Without the F instruction set, the location would simply be marked invalid.

Similarly, EBUF 192 provides another alternative prefetch path via prefetch buffer 260. EBUF192 preferably comprises M
It is used in prefetching a single instruction appearing in the BUF 188 instruction stream, an alternative instruction stream used to implement the operation specified in the "procedure" instruction. In this way, complex or extended instructions can be implemented through software routines or procedures and processed through the prefetch buffer unit 260 without disturbing the instruction stream already prefetched and placed in the MBUF 188. be able to. In general,
In accordance with the present invention, procedural instructions that first appear in TBUF 190 can be processed, but prefetching of the procedural instruction stream is suspended and any previously encountered pending conditional branch instruction streams are resolved. This ensures that conditional branch instructions that appear in the procedure instruction stream are processed consistently through the use of TBUF 190. Therefore, if a branch is taken in the procedure stream, the target instruction set is already prefetched and the TBUF
190, the data can be transferred to the EBUF 192 in parallel.

Finally, MBUF188, TBUF190
And EBUF 192 are each connected to a prefetch buffer output bus 196 for sending the instruction set stored by the prefetch unit onto output bus 196. Further, the flow through bus 194 is for transferring the instruction set directly from instruction bus 114 to output bus 196.

In the preferred architecture 100, the MBUF
The prefetch buffers in 188, TBUF 190, and EBUF 192 do not directly constitute a FIFO structure. Instead, since any buffer location is connected to the output bus 196, there is a great deal of flexibility in the prefetch order of instruction sets fetched from the instruction cache 132. That is, the instruction fetch unit 102 generally determines and requests an instruction set in the order of instructions arranged in an instruction stream in a fixed order. However, if the instruction set is IFU10
The order when returned to 2 is such that certain instruction sets requested are available and accessible only by CCU 106, while other instruction sets appear out of order, such as when access to MAU 102 is required. It is also possible.

Although the instruction set may not be returned to the prefetch buffer unit 260 in a certain order,
The sequence of instruction sets output on output bus 196 must generally follow the order of the instruction set requests issued by IFU 102. In-order
This is because the instruction stream sequence of r) is affected by trial execution of the target branch stream, for example.

The I decode unit 262 has an IFIF
As long as space in O-unit 264 allows, instruction sets are received from prefetch buffer output bus 196, typically at a rate of one per cycle. Each set of four instructions that make up one instruction set is an I-decode
Decoded in parallel by unit 262. While the relevant control flow information is being pulled out of line 318 for the control path portion of IFU 102, the contents of the instruction set are not modified by I-decode unit 262.

The instruction set from the I decode unit 162 is sent out on the 128-bit wide input bus 198 of the IFIFO unit 264. Internally, the IFIFO unit 264 stores the master / slave registers 200, 2
04, 208, 212, 216, 220, and 224. Each register is connected to its successor register so that the contents of the master registers 200, 208, 216 are populated during the first half of the internal processor cycle of the FIFO operation.
0 and then during the second half cycle of operation, the next subsequent master register 208, 216, 224
To be forwarded to An input bus 198 is connected to the input of each of the master registers 200, 208, 216, 224 so that the instruction set is loaded directly from the I decode unit 262 to the master register during the second half cycle of the FIFO operation. I have. However, loading the master register from input bus 198 need not be done simultaneously with FIFO shifting the data in the FIFO unit 264. As a result, regardless of the current depth of the instruction set stored in the instruction FIFO unit 264,
Independently from the FIFO shifting of data within the O unit 264, the input bus 198 continuously
It can go into unit 264.

Master / slave registers 200, 20
4, 208, 212, 216, 220, 224 can store all bits of the 128-bit wide instruction set in parallel and also store some bits of control information in their respective control registers 202, 206, 210, 214. , 2
18, 222, 226. Preferably, the set of control bits is an exception mismatch
option) and exception correction (exception)
n modify) (VMU), no memory (MC
U), branch bias, stream, and offset (IFU). This control information
The IFO master register is loaded from the input bus 198 with a new instruction set, and simultaneously originates from the control path portion of the IFU 102. Thereafter, the control register information is shifted in parallel in the IFIFO unit 263 in parallel with the instruction set.

Finally, in the preferred architecture 100,
The output of the instruction set from the IFIFO unit 264 is obtained simultaneously from the last two master registers 216, 224, and the I_Bucket 0 and I Bucket It is sent out on one instruction set output bus 278,280. Further, the corresponding control register information is IBASV0 and IBAV.
Delivered on the SV1 control field bus 282,284. These output buses 278, 282, 280, 28
4 are all instruction stream buses 124 leading to the IEU 104.

B) IFU Control Path The IFU 102 control path includes a prefetch buffer unit 260, an I decode unit 262, and an IF
It directly supports the operation of the IFO unit 264. The prefetch control logic unit 266 mainly manages the operation of the prefetch buffer unit 260. Prefetch control logic unit 266 and IFU 102 typically receive a system clock signal from clock line 290 and
The operation of the FU is synchronized with the operation of the IEU 104, the CCU 106, and the VMU 108. Select the instruction set and select MBUF188,
Control signals for writing to TBUF 190 and EBUF 192 are sent on control line 304.

A number of control signals are sent on control line 316 to control the prefetch control logic unit 26.
Sent to 6. Specifically, a fetch request control signal is sent to initiate a prefetch operation. Other control signals transmitted on control line 316 include whether the requested prefetch operation is targeted at MBUF 188 or TBUF 190,
EBUF192 is specified. In response to the prefetch request, the prefetch control logic unit 2
66 generates an ID value and sends a prefetch request to the CCU 10
6 is notified. The generation of the ID value is
This is done using a rotating 4-bit counter.

The use of a 4-bit counter is important in three ways: First, the prefetch buffer unit 260 can activate up to nine instruction sets at a time. That is, MBUF188
4 instruction sets, 2 instruction sets in TBUF190,
Instruction set in EBUF 192 and I decode unit 262 directly via flow through bus 194
Is one instruction set passed to. Second, the instruction set consists of four instructions, each four bytes. As a result, any address that selects the instruction to be fetched has the least significant four bits extra. Lastly, the prefetch request ID can be easily associated with the prefetch request by inserting it as the least significant 4 bits of the prefetch request address. This allows CC
The total number of addresses needed to interface with U106 will be reduced.

To ensure that the instruction set is returned from the CCU 106 out of order relative to the order of the prefetch requests issued by the IFU 102, the architecture 100
Then, along with the return of the instruction set from the CCU 106,
The D request value is returned. However, according to the out-of-order instruction set return function, 16 unique IDs may be used up. If the combination of conditional instructions is executed out of order, there is an additional prefetch and instruction set that was requested but not yet returned, so the ID
The value can be reused. Therefore, 4 bits
It is preferable to keep the counter, so that a subsequent instruction set prefetch request will not be issued, in which case the next ID value will be the fetch request remaining unprocessed or the prefetch request at that time. It is associated with another instruction set held in the buffer 260.

Prefetch control logic unit 26
6 directly manages an array of status registers 268, which consists of status storage locations that logically correspond to each instruction set prefetch buffer location in MBUF 188, TBUF 190 and EBUF 192. Prefetch control logic unit 266 can scan, read, and write data to status register array 268 via select and data line 306. In the array 268, the main buffer register 308 has four 4-bit ID values (MBID), four 1-bit reservation flags (MB RES) and four 1-bit valid flags (M
B VAL), each of which is associated with a respective instruction set storage location in MBUF 180 by logical bit position. Similarly, the target buffer register 310 and the extension buffer register 312 have two 4-bit ID values (TB ID, EBID), two 1-bit reservation flags (TB RES, EB RES) and two 1-bit valid flag (TB VAL, EB VAL)
Is to be stored. Finally, the flow
The through status register 314 stores one 4-bit ID value (F
T TD), one reserved flag bit (FT RE
S) and one valid flag bit (FT VAL)
Is to be stored.

The status register array 268 is scanned first, and if applicable, the prefetch request is
6 is updated by the prefetch control logic unit 266 each time it is issued, and then scanned and updated each time the instruction set is returned. More specifically, upon receiving a prefetch request signal from the control line 316, the prefetch control logic unit 2
66 increments the current cyclic counter generated ID value and scans the status register array 268 to determine if there is an available ID value, and if a prefetch buffer location of the type specified in the prefetch request signal is available. Judge whether there is, and CCUIBUSY
The status of the control line 300 is checked to determine whether the CCU 106 can accept the prefetch request, and if so, the CCU on the control line 298
The IREAD control signal is asserted and the incremented I
CCU ID output bus 2 with D value connected to CCU 106
94. The prefetch storage location is
It can be used when the corresponding reservation status flag and valid status flag are both false. The prefetch ID is set in parallel with the request being issued to the CCU 106.
8, status register array 2 corresponding to the target storage location in TBUF 190 or EBUF 192
68 is written to the ID storage location. Further, the corresponding reservation status flag is set to true.

When the CCU 106 can return the previously requested instruction set to the IFU 102, the CCU IRE
The ADY signal is asserted on control line 302 and the corresponding instruction set ID is sent out on CCU ID control line 296. Prefetch control logic unit 266
Scans the ID value and the reservation flag in the status register array 268 to read the prefetch buffer unit 260
Determine the target destination of the instruction set in. Only one match is possible. If determined, the instruction set is written via bus 114 to the appropriate location in prefetch buffer unit 260 and, if determined to be a flow-through request, passed directly to I-decode unit 262. In either case, the valid status flags in the corresponding status register array 268 are set to true.

The PC logic unit 270 examines the entire IFU 102, as described in detail below, and
Locate the virtual address of the BUF 188, TBUF 190 and EBUF 192 instruction streams. In performing this function, PC logic block 270 controls and operates from I-decode unit 262. Specifically, the instruction portion that is decoded by the I decode unit 262 and that may be associated with a change in the flow of the instruction stream of the program is
To the control flow detection unit 274 and directly to the PC logic block 270. The control flow detection unit 274 converts the instructions that make up the control flow instructions, including conditional and unconditional branch instructions, call-type instructions, software trap procedure instructions and various return instructions, into the decoded instruction set. Judge from inside. Control flow detection unit 274 sends a control signal to PC logic unit 270 via line 322. This control signal indicates the location and type of control flow instruction in the instruction set residing in I decode unit 262. In response, the PC logic unit 270
Typically, P is inserted into the instruction via line 318
The target address of the control flow instruction is determined from the data transferred to the C logic unit. For example, if a branch logic bias was selected to execute first for a conditional branch instruction, PC logic unit 270 would indicate to prefetch the instruction set from the conditional branch instruction target address. Start tracking separately. Thus, the next affirmation of the prefetch request on control line 316:
PC logic unit 270 also asserts the control signal via line 316 and assumes the prefetch instruction set has been sent to MBUF 188 or EBUF 192 and sets the prefetch destination to TBUF1.
Select as 90. Prefetch request to CCU 106
If the prefetch control logic unit 266 determines that the prefetch control logic
Unit 266 again provides an enable signal via line 316 to PC logic unit 27.
0 to allow the page offset portion of the target address (CCU PADDR [13: 4]) to be passed directly to the CCU 106 via the address line 324. At the same time, when a conversion from a new virtual page to a physical page is required, the PC logic unit 270 further transmits a VMU request signal via the control line 328 to the virtualized portion (VMU VADDR) of the target address. [13:14])
The data is passed to the VMU 108 via the line 326 and is converted into a physical address. If no page conversion is needed, V
No operation by the MU 108 is required. Instead, the previous conversion result is stored in an output latch connected to bus 122 and is used immediately by CCU 106.

If an operation error occurs in the VMU 108 during the virtual to physical conversion requested by the PC logic unit 270, the VMU exception and VMU mismatch control (miss control) lines 332, 33
Reported through 4. VMU mismatch control line 334
Is a translation index buffering mechanism (translation loop)
report a mismatch buffer (TLB) mismatch. The VMU exception control signal on VMU exception line 332 occurs when another exception occurs. In either case, P
The C logic unit stores the current location of execution in the instruction stream, and then receives it, as if an unconditional branch, was taken to diagnose and handle the error condition. Exception handling routines Handle error conditions by prefetching the instruction stream. Since the VMU exception and mismatch control signals indicate the type of exception that has occurred, the PC logic unit 2
70 can determine the prefetch address of the corresponding exception handling routine.

IFIFO control logic unit 272
Is for directly supporting the IFIFO unit 264. Specifically, PC logic unit 2
70 outputs a control signal via a control line 336,
Notifies IFIFO control logic unit 272 that the instruction set is available from I decode unit 262 via input bus 198. The IFIFO control unit 272 is configured to receive the instruction set by using the innermost available master registers 200, 208, 216, 2
24. Master register 2
02, 210, 218, 226 are passed to IFIFO control unit 272 via control bus 338. The control bit stored by each master control register is a 2-bit buffer address (IF_Bx_
ADR), a single stream indicator bit (I
F_Bx_STRM) and a single valid bit (IF_
Bx_VLD). 2-bit buffer
The address specifies the first valid instruction in the corresponding instruction set. That is, the instruction set returned from the CCU 106 may not be aligned, for example, such that the target instruction of the branch operation is located at the first instruction location in the instruction set. Thus, the buffer address value is provided to uniquely indicate the first instruction in the instruction set to be considered for execution.

The stream bits indicate the location of the instruction set containing the conditional control flow instruction;
It is based on being used as a marker to cause a potential control flow change in the stream of instructions through the IFIFO unit 264. The main instruction stream is generally processed through MBUF 188 when the stream bit value is zero. For example, when a relative conditional branch instruction appears, the corresponding instruction set is marked,
The stream bit value becomes 1. The conditional instruction set is detected by the I decode unit 262. Up to four conditional control flow instructions can be in the instruction set. Thereafter, it is stored in the deepest available master register of the IFO unit 264 at the time of instruction setting.

To determine the target address of the conditional branch instruction, the current execution point address (DPC) of the IEU 104, the relative location of the instruction set containing the conditional instruction specified by the stream bits, the control flow The conditional instruction location offset in the instruction set obtained from the detection unit 274 is combined with the relative branch offset value obtained from the corresponding branch instruction field via the control line 318. The result is the virtual address of the branch target, which is stored by PC logic unit 270. The first instruction set of the target instruction stream can be prefetched into TBUF 190 using this address. Depending on the pre-selected branch bias for PC logic unit 270, IFI
FO unit 264 is MBUF188 or TBUF1
Loading continues from 90. When a second instruction set appears that contains one or more conditional flow instructions, the instruction set is marked with a zero stream bit value. Since the second target stream cannot be fetched, the target address is calculated and stored by PC logic unit 270, but no prefetch is performed. Further, subsequent instruction sets cannot be processed through the I-decode unit 262. At least none of the instruction sets found to contain conditional flow control instructions are processed.

In the preferred embodiment of the present invention, the PC logic
Unit 270 can manage up to eight conditional flow instructions that appear in up to two instruction sets. 2 marked by stream bit change
The target address of each of the instruction sets is stored in an array of four address registers, and the target addresses are logically located with respect to the location of the corresponding conditional flow instruction in the instruction set.

Once the branch result of the first in-order conditional flow instruction is resolved, PC logic unit 270
Transfers the contents of TBUF 190 to MBUF 188 if a branch is taken, and instructs prefetch control unit 260 by a control signal on line 316 to mark the contents of TBUF 190 as invalid. The instruction set from the incorrect instruction stream, i.e., from the target stream if the branch is not taken, or from the main instruction stream if the branch is taken, is cleared from the IFIFO unit 264, if present. If a second or subsequent conditional flow control instruction is present in the instruction set marked with the first stream bit, the instruction is processed in a unified manner. That is, the instruction set from the target stream is prefetched and the MBU
The instruction set from the F188 or TBUF 190 is processed through the I-decode unit 262 in response to a branch bias, and when the conditional flow instruction is finally resolved, the incorrect stream instruction set is
Cleared from unit 264.

When an incorrect stream instruction is cleared from the IFIFO unit 264, a second conditional flow instruction remains in the IFIFO unit 264,
If the first conditional flow instruction set does not include any subsequent conditional flow instructions, the target address of the instruction set marked with the second stream bit is promoted to the first array in the address register. . In either case, the next instruction set containing the conditional flow instruction can be evaluated through I-decode unit 262. Thus, using stream bits as toggles, the branch target
For the purpose of calculating addresses, and to mark instruction set locations above which branch bias should be cleared if it is later determined to be incorrect for a particular conditional flow control instruction For this purpose, potential control flow changes can be marked and tracked through the IFIFO unit 264.

Rather than actually clearing the instruction set from the master register, the IFIFO control logic unit 272 uses the valid bit
It just resets the flag. This clear operation is initiated by PC logic unit 270 with a control signal sent on line 336. The inputs of each of the master control registers 202, 210, 218, 226
Unit 272 has direct access. In the preferred embodiment architecture 100, the bits in these master control registers 202, 210, 218, 226 are controlled by the IFIFO in parallel or independently of the data shift operation by
It can be set by the control unit 272. This function allows the instruction set to be stored in the master registers 200, 20 asynchronously with the operation of the IEU 104.
8, 216, 224, and the corresponding status information is written in the master control registers 202, 210, 218, 2
26 can be written.

Finally, an additional control line on the control and status bus 230 is
Enable and indicate O operation. The IFIFO shift is performed by the IFIFO unit 264 in response to the shift request control signal output from the PC logic unit 270 via the control line 336. IFIF
The O control unit 272 sends a control signal via line 316 to the prefetch control unit 266 when the master registers 200, 208, 216, 224 that accept the instruction set are available, and Request to transfer the corresponding instruction set. When the instruction set is transferred, the corresponding valid bit in array 266 is reset.

C) IFU / IEU Control Interface A control interface between IFU 102 and IEU 104 is provided by control bus 126. The control bus 126 is connected to the PC logic unit 270 and comprises a plurality of control, address and special data lines. By passing the interrupt request and the acknowledgment control signal via the control line 340, the IFU 102 can notify the interrupt operation and synchronize with the IEU 104. An externally generated interrupt signal is sent to logic unit 270 via line 292. In response, when an interrupt request control signal is sent out on line 340, IEU 104 cancels the trially executed instruction. Information about the contents of the interrupt is exchanged via an interrupt information line 341. IEU10
4 is ready to begin receiving instructions prefetched from the address of the interrupt service routine determined by PC logic unit 270, the IEU
104 asserts the interrupt acknowledgment control signal on line 340. The interrupt service routine prefetched by the IFU 102 is then started.

An IFIFO Read (IFIFO RD) control signal is output from IEU 104 on control line 342, indicating that the instruction set residing in innermost master register 224 has completed execution and that the next instruction set is required. Notify. When receiving this control signal, the PC
Logic unit 270 is an IFIFO unit 264
Instructs the IFIFO control logic unit 272 to perform an IFIFO shift operation.

The PC increment request and the size value (PC
INC / SIZE) is sent on control line 344 to update the PC logic unit 27 to update the current program counter value by the corresponding size number of instructions.
Indicate 0. Thereby, the PC logic unit 2
70 may maintain an execution program counter (DPC) at the exact location of the first in-order execution instruction in the current program instruction stream.

The target address (TARGET A)
DDR) is returned to PC logic unit 270 via address line 346. This target address is the virtual target address of the branch instruction determined by the data stored in the IEU 104 register file. Therefore, operation of the IEU 104 is required to calculate the target address.

The control flow result (CF RESULT) control signal is sent via control line 348 to the PC logic unit 270 to determine whether the currently pending conditional branch instruction has been resolved, and whether the result depends on the branch. , Or not depending on the branch. Based on these control signals, the PC logic unit 270 determines whether the prefetch buffer 260 and the IFIFO
It can be determined which instruction set located in unit 264 needs to be canceled.

Several IEU instruction return type control signals (IEU returns) are sent on control line 350 to notify IEU 102 that an instruction has been executed by IEU 104. These instructions include returns from procedure instructions, returns from traps, and returns from subroutine calls. The return instruction from the trap is used in the same way in the hardware interrupt handling routine and the software trap handling routine. Returns from subroutine calls are also used with jumps and linked calls. In each case, a return control signal is sent to notify IFU 102 to resume the instruction fetch operation for the previously interrupted instruction stream. By issuing these signals from the IEU 104, accurate operation of the system 100 can be maintained. Resume of the "interrupted" instruction stream occurs from the point of execution of the return instruction.

Current instruction execution PC address (current IF_PC)
Are sent to the IEU 104 via the address bus 352. This address value (DPC) specifies the exact instruction to be executed by IEU 104. That is, IE
U104 is the current IF During pre-trial execution of instructions that have passed the PC address, this address is used by the architecture 100 for the occurrence of interrupts, exceptions, and other events that require accurate machine state knowledge.
Must be maintained for precise control. If the IEU 104 determines that it is possible to advance the exact machine state in the currently executing instruction stream, a PC Inc / Size signal is sent to the IFU 102 and immediately reflected in the current IF_PC address value.

Finally, the address and bidirectional data bus 354 is for transferring the data of the special register. This data is transmitted to IFU10 by IEU104.
2 can be programmed to be placed in or read from special registers. Special register data is generally loaded or calculated by IEU 104 for use by IFU 102.

D) Details of PC Logic Unit PC control unit 362, interrupt control unit 363,
PC logic unit 270 including prefetch PC control unit 364 and execute PC control unit 366
Is shown in FIG. PC control unit 36
2 receives control signals from prefetch control unit 266, IFIFO control logic unit 272, and IEU 104 through interface bus 126,
Prefetch and execution PC control units 364, 36
6 is subjected to timing control. The interrupt control unit 363 is responsible for the precise management of interrupts and exceptions, including determining the prefetch trap address offset and selecting the appropriate processing routine to handle each trap type. The prefetch / PC control unit 364, in particular, performs trap processing and procedure
Prefetch buffer 18 includes storing the return address for the flow of routine instructions.
It is responsible for managing the program counters needed to support 8, 190, 192. To support this operation, the prefetch PC control unit 364 uses the CC on physical address bus line 324 to
Responsible for generating a prefetch virtual address that includes the U PADDER address and the VMU VMADDR address on address line 326. As a result, the prefetch PC control unit 364 is responsible for maintaining the current prefetch PC virtual address value.

The prefetch operation is generally performed by an IFI through a control signal transmitted on control line 316.
Initiated by FO control logic unit 272. In response, the PC control unit 362 generates and outputs a number of control signals on the control line 372 and operates the prefetch PC control unit 364 to generate the PADDR address on the address lines 324 and 326 and the necessary address. Generates a VMADDR address in accordance with. An increment signal having a value of 0 to 4 is also supplied to the control line 37.
4, which may be due to the PC control unit 362 re-executing the instruction set fetch from the current prefetch address, or to the second request in the series of prefetch requests. It depends on whether alignment is performed or the next full sequential instruction set is selected for prefetch. Finally, the current prefetch address PF_PC is sent out on the bus 370 and passed to the execution PC control unit 366.

[0062] New prefetch addresses originate from several sources. The primary source of addresses is
The current IF sent from the execution PC control unit 366 via the bus 352 PC address. In principle,
The IF_PC address gives the return address, which, when an initial call, trap or procedural instruction appears, the prefetch PC control unit 36
4 will be used later. The IF_PC address is stored in a register in the prefetch PC control unit 364 each time these instructions appear.
Thus, when the PC control unit 362 receives the IEU return signal via the control line 350, it only needs to select the return address register in the prefetch PC control unit 364 and retrieve the new prefetch virtual address, Restart the original program instruction stream.

Another source of prefetch addresses is from execution PC control unit 366 via relative target address bus 382 or the IEU1
04 is the target address value sent via the absolute target address bus 346. The relative target address is the execution PC control unit 366.
Is an address that can be calculated directly by Absolute target addresses are those target addresses
It depends on the data contained in the EU register file and must be generated by the IEU 104. The target address is sent to the prefetch PC control unit 364 via the target address bus 384 and is used as a prefetch virtual address. When calculating the relative target address, the operand portion of the corresponding branch instruction is also sent from I decode unit 262 via the operand displacement portion of bus 318.

Another source of prefetch virtual addresses is the execution PC control unit 366. Return address bus 352 'provides the current IF_PC value (D
PC) to the prefetch PC control unit 364. This address is used as the return address where control flow instructions such as interrupts, traps, and other calls appear in the instruction stream. Prefetch PC control unit 364 is released to prefetch a new instruction stream.
When the corresponding interrupt or trap processing routine or subroutine is executed, the PC control unit 362 executes
An IEU return signal is received from the IEU 104 via line 350. On the other hand, the PC control unit 362 selects the register containing the current return virtual address through one of the PFPC signals on line 372 and based on the ID of the executed return instruction sent over line 350 I do. This address is then used to continue the prefetch operation by PC logic unit 270.

Finally, another source from which the prefetch virtual address is retrieved is the special register address and data bus 354. The address value calculated or loaded by the IEU 104, or at least the base address value, is transferred as data to the prefetch PC control unit 364 via the bus 354. The base address includes the addresses of the trap address table, the fast trap table, and the base procedure instruction dispatch table. Many of the registers in the prefetch and PC control units 364, 366 can also be read through the bus 354, so that the corresponding aspects of the state of the machine are IE
It is possible to process through U104.

The execution PC control unit 366 receives the current IF under the control of the PC control unit 362. The main role is to calculate the PC address value. In this role, the execution PC control unit 366 receives the control signal sent from the PC control unit 362 via the ExPC control line 378 and the increment / size control signal sent via the control line 380. ,
Adjust the IF_PC address. These control signals are
It is mainly generated when receiving the IFIFO read control signal transmitted via the line 342 and the PC increment / size value transmitted via the control line 344 from the IEU 104.

1) Details of PF and ExPC control / data unit FIG.
It is a detailed block diagram of 4,366. These units mainly consist of registers, incrementers and other similar parts, selectors and adder blocks. Controls for managing data transfer between these blocks include a PFPC control line 372, an ExPC control line 378, and increment control lines 374, 380.
Through the PC control unit 362. For simplicity, the block diagram of FIG.
These individual control lines are not shown. But,
Of course, these control signals are sent to these blocks as described below.

The center of the prefetch PC control unit 364 is a prefetch selector (PF_PC
SEL), which acts as a central selector for the current prefetch virtual address. This current prefetch address is sent from the prefetch selector via output bus 392 to incrementer unit 394 to generate the next prefetch address. This next prefetch address is passed through the incrementer output bus 396 to the registers MBUF PFnPC 398, TBUF
PFnPC400 and EBUF PFnPC402
Sent to the parallel array. These registers 398, 40
Although 0, 402 effectively stores the next instruction prefetch address, according to a preferred embodiment of the present invention,
Separate prefetch addresses are MBUF188, TB
It is held in the UF 190 and the EBUF 192.
The prefetch addresses stored in the MBUF, TBUF and EBUF PFnPC registers 398, 400, 402 are stored on the address buses 404, 408, 410.
To the prefetch selector 390. Thus, the PC control unit 362 can indicate immediate switching of the prefetch instruction stream simply by indicating that the prefetch selector selects another one of the prefetch registers 398, 400, 402. When the address value is incremented by incrementer 394 to prefetch the next set of instructions in the stream, the value is prefetched.
The address 398, 400, or 402 is returned to the corresponding register. Another parallel register array is shown as a single special register block 412 for simplicity, but this array is for storing some special addresses. Register block 412 includes a trap return address register, a procedure instruction return address register, a procedure instruction dispatch table base address register, a trap routine dispatch table base address register, and a fast trap. -Consists of a routine base address register. Under the control of PC control unit 362, these return address registers can accept the current IF_PC execution address over bus 352. The address value stored in the return and base address registers in register block 412 is IEU1
04 can be read and written independently. The register is selected and the value is transferred via the special register address and data bus 354.

The selector in the special register block 412 is controlled by the PC control unit 362, and sends the address stored in the register of the register block 412 onto the special register output bus 416 and passes it to the prefetch selector 390. Can be. return·
The address is passed directly to prefetch selector 390. The base address value is set in the interrupt control unit 363.
From the interrupt offset bus 373 from the CPU. The special address passed to the prefetch selector 390 from the source via the bus 373 is used as the initial address of the new prefetch instruction stream, and then the address of the address passing through the incrementer 394 and one of the prefetch registers 398, 400, 402. The increment loop can continue.

Another source of addresses sent to prefetch selector 390 is the register array in target address register block 414.
In the target register in block 414, according to the preferred embodiment, eight potential branch target addresses are stored. These eight storage locations logically correspond to the eight potentially executable instructions held in the least significant two master registers 216, 224 of the IFIFO unit 264. Since any and potentially all of these instructions can be conditional branch instructions, the target register block 414 stores the pre-computed target address, so that the target instruction stream through the TBUF 190 Can be made to wait for use to prefetch. In particular, when the conditional branch bias is set such that the PC control unit 362 immediately begins prefetching the target instruction stream, the target address is prefetched from the target register block 414 via the address bus 418. -Sent to selector 390. After being incremented by the incrementer 394,
The address is stored back into the TBUF PFnPC 400 for use in operations that prefetch the target instruction stream later. When another branch instruction appears in the target instruction stream, the target address of the second branch is calculated, and until the first conditional branch instruction is resolved and used.
It is stored in the target register array 414.

The calculated target address stored in the target register block 414 is:
From the target address calculation unit in the execution PC control unit 366 via the address line 382,
Alternatively, the absolute target address from the IEU 104
The data is transferred via the bus 346.

The address value transferred through the prefetch PF_PC selector 390 is a complete 32-bit virtual address value. The page size is fixed at 16K bytes in the preferred embodiment of the present invention, and the maximum page size is
It corresponds to the offset address value [13: 0].
Therefore, the current prefetch virtual page address [27:
14], there is no need to convert the VMU page. The comparator in the prefetch selector 390 detects this. VMU conversion request signal (VMXL
AT) sends to the PC control unit 362 via line 372 when the virtual page address changes, either because the increment has been made across a page boundary or because the control flow has branched to another page address. Can be On the other hand, the PC control unit 362 sends the VM VADDR address on the line 326 from the buffer unit 420 in addition to the CCU PADDR on the line 324, and sends the corresponding control signal to the VMU control line 326, 32.
8, 330 to instruct it to get the conversion from VMU virtual pages to physical pages. If no page translation is required, the current physical page address [31:14]
Is held by a latch on the output side of the VMU unit 108 on the bus 122.

The virtual address transmitted on the bus 370 is incremented by the incrementer 394 in response to the signal transmitted from the increment control line 374. Incrementer 394 provides a value representing the instruction set (4 instructions or 1) to select the next instruction set.
6 bytes). CCU unit 1
The lower 4 bits of the prefetch address passed to 06 are zero. Thus, the actual target address instruction in the first branch target instruction set may not be located at the first instruction location.
However, the lower 4 bits of the address are stored in the PC control unit 3
As sent to 62, IFU 102 can determine the location of the first branch instruction. The detection and processing to return the low order bits [3: 2] of the target address as a 2-bit buffer address and to select the correct first instruction to execute from the unaligned target instruction set is a new instruction stream,
That is, it occurs only during the first prefetch of the first non-sequential instruction set address in the instruction stream.
The unaligned relationship between the address of the first instruction in the instruction set and the prefetch address used in prefetching the instruction set can be ignored during the life of the current sequential instruction stream. It is neglected.

The remaining part of the functional blocks shown in FIG. 4 constitutes the execution PC control unit 366. According to a preferred embodiment of the present invention, the execution PC control unit 366 has its own independently functioning program counter incrementer. At the center of this function is the execution selector (DPC SEL) 430. Execution Seleta 43
0 on address bus 352 'is the current execution address of architecture 100 (DP
C). This execution address is sent to the addition unit 434. The increment / size control signal sent on line 380 specifies an instruction increment value from one to four, which is added by adder unit 434 to the address obtained from selector 430. Each time the add unit 434 performs the output latch function, the next incremented execution address is returned directly to the execution selector 430 via the address line 436 and used in the next instruction increment cycle.

The initial execution address and all subsequent new stream addresses are obtained from new stream register unit 438 via address line 440. New stream register unit 438
Can pass the new current prefetch address sent from the prefetch selector 390 via the PFPC address bus 370 directly to the address bus 440 or store it for later use. That is, if the prefetch PC control unit 364 determines to start prefetching from a new virtual address, the new stream address is temporarily stored by the new stream register unit 438. The PC control unit 363 participates in both the prefetch and execution increment cycles, and thereby stores the new stream address in the new stream register until the execution address reaches the program execution point corresponding to the control flow instruction that started the new instruction stream. 4
38. The new stream address is then output from the new stream register unit 438 and sent to the execution selector 430 to begin independently generating execution addresses in the new instruction stream.

According to a preferred embodiment of the present invention, the new stream register unit 438 has the ability to buffer two control flow instruction target addresses. By immediately retrieving the new stream address, the execution PC control unit 36 has almost no waiting time.
6 can be switched from the generation of the current execution address sequence to the generation of a new execution address stream sequence.

Finally, IF_PC seleta (IF_PC
SEL) is to finally send the current IF_PC address onto the address bus 352 and send it to the IEU 104. The input to IF_PC selector 442 is the output address obtained from execution selector 430 or new stream register unit 438. In most cases, IF
The _PC selector 442 receives the instruction from the PC control unit 262 and selects the execution address output from the execution selector 430. However, to further reduce the latency when switching to a new virtual address used to start execution of a new instruction stream, the selected address from new stream register unit 438 is bypassed via bus 440. Directly with the IF_PC selector 44
2 and can be obtained as the current IF_PC execution address.

The execution PC control unit 366 has a function of calculating all relative branch target addresses. The current execution point address and the address obtained from the new stream register unit 438 are passed to the control flow selector (CF_PC) 446 via the address bus 352 ', 440. As a result, the PC control unit 362 has great flexibility and
The correct initial address on which to calculate the address can be selected. This initial address, the base address, is sent to the target bus via address bus 454.
Sent to address ALU 450. Target ALU4
Another value to be input to 50 is sent from the control flow displacement calculation unit 452 via the bus 458.
The relative branch instruction, according to the preferred embodiment of the architecture 100, includes a displacement value in the form of an immediate mode constant specifying a new relative target address. The control flow displacement calculation unit 452 receives the first operand displacement value from the I decode unit operand output bus 318. Finally, the offset register value is sent via line 456 to the target address ALU 45
Sent to 0. Offset register 448 receives an offset value from PC control unit 362 via control line 378 '. The magnitude of the offset value is based on the address offset from the base address sent on address line 454 to the address of the current branch instruction when calculating the relative target address.
It is determined by the control unit 362. That is, PC
The control unit 362 controls the IFO control logic unit 272 so that the instruction at the current execution point address (required by CP_PC) and the I decode unit 262 are currently being processed, and thus are being processed by the PC logic unit 270. By tracking the number of instructions that separate the instruction in the
Determine the address.

If the relative target address is the target
As calculated by address ALU 450, the target address is written to corresponding target register 414 via address bus 382.

2) Details of PC control algorithm Main instruction stream processing: MBUF PFnP
Cl. The address of the primary main flow prefetch instruction is stored in MBUF PFnPC.

1.2 When there is no control flow instruction, 3
The 2-bit incrementer adjusts the address value contained in the MBUF PFnPC by 16 bytes (x16) for each prefetch cycle.

1.3 When an unconditional control flow instruction is I-decoded, all prefetch data fetched following the instruction set is flushed and the MBUF
PFnPC has a target register unit, P
F The new main instruction stream address is loaded through the PC selector and incrementer. The new address is also stored in the new stream register.

1.3.1 The target address of the relative unconditional control flow is obtained from the register data held by the IFU and the operand address placed after the control flow instruction.
Calculated by IFU from data.

1.3.2 The target address of the absolute unconditional control flow is finally calculated by the IEU from the register reference value, base register value, and index register value.

1.3.2.1 The instruction prefetch cycle stops until the target address is returned from the IEU for an absolute address control flow instruction. The instruction execution cycle continues.

1.4 The address of the next main flow prefetch instruction obtained from the unconditional control flow instruction is bypassed and sent via the target address register unit, the PF_PC selector and the incrementer, and the final Is stored in MBUFPFnPC,
Prefetching continues from 1.2. 2. Processing of procedure instruction stream: EBUF P
FnPC 2.1 procedural instructions are prefetched in the main or branch target instruction stream. If fetched in the target stream, stop prefetching the procedure stream until the conditional control flow instruction is resolved and the procedure instruction is transferred to the MBUF. This allows TBUF to be used in processing conditional control flows that appear in the procedure instruction stream.

2.1.1 Procedure instructions must not be placed in the procedure instruction stream. That is,
Procedure instructions must not be nested. Upon return from the procedural instruction, execution returns to the main instruction stream. To enable nesting, another dedicated return from the nested procedure instruction is needed. Although the architecture can easily support this type of instruction, the ability to nest procedural instructions is unlikely to improve the performance of the architecture.

2.1.2 In the main instruction stream, a procedural instruction stream containing an instruction set containing first and second conditional control flow instructions is:
Stop prefetching for the second conditional control flow instruction set until the conditional control flow instruction in the first instruction set resolves and the second conditional control flow instruction set is transferred to the MBUF.

2.2 Procedure Instructions indicate the start address of a procedure routine by a relative offset included as an immediate mode operand field of the instruction.

2.2.1 The offset value obtained from the procedure instruction is combined with the value contained in the procedure base address (PBR) register maintained in the IFU. When the move instruction of the special register is executed, the special address and data
It is readable and writable through the bus.

2.3 When a procedure instruction appears, the next main instruction stream IF The PC address is stored in the DPC return address register and the procedure-in-progress bit in the processor status register (PSR).
ss bit) is set.

2.4 The starting address of the procedure stream is sent from the PBR register (plus the procedure instruction operand offset value) to the PF_PC selector.

2.5 The start address of the procedure stream is sent to the new stream register unit and increment at the same time, and is incremented by (x16). The incremented address is then EB
Stored in UF PFnPC.

2.6 In the absence of a control flow instruction, the 32-bit incrementer adjusts the address value contained in EBUF PFnPC by (x16) every procedure instruction prefetch cycle.

2.7 When the unconditional control flow instruction is I-decoded, all prefetched data fetched after the branch instruction is flushed and the EBUF
PFnPC has a new procedure instruction stream
The address is loaded.

2.7.1 The target address of the relative unconditional control flow instruction is obtained from the register data held in the IFU and from the operand data contained in the immediate mode operand field of the control flow instruction. Is calculated by

2.7.2 The target address of the absolute unconditional branch is calculated by the IEU from the register reference, base and index register values.

2.7.2.1 The instruction prefetch cycle stops until the target address for the absolute address branch is returned from the IEU. The execution cycle continues.

2.8 The address of the next procedure prefetch instruction set is stored in EBUFPFnPC and prefetching continues from 1.2.

2.9 When the return from the procedural instruction is I-decoded, prefetching is continued from the address stored in the uPC register, then incremented by (x16), and the MBUF PFnPC register for later prefetching. Is returned to. 3. Processing of branch instruction stream: TBUF PFn
When the conditional control flow instruction that appears in the first instruction set in the PC 3.1 MBUF instruction stream is I-decoded, the target address is determined by the IFU if the target address is relative to the current address, and the absolute address. Then it is determined by the IFU.

3.2 For "Bias to Branch": 3.2.1 If a branch is taken to an absolute address, stop the instruction prefetch cycle until the target address is returned from the IEU. The execution cycle continues.

3.2.2 PF The branch target address is loaded into the TBUF PFnPC by transferring via the PC selector and the incrementer.

3.2.3 After the target instruction stream is prefetched and placed in the TBUF, it is sent to the IFIFO for execution. IFIFO and TB
When the UF becomes full, the prefetch stops.

3.2.4 32-bit incrementer TBUF PFnPC for each prefetch cycle
The address value contained therein is adjusted by (x16).

3.2.5 Conditional control flow instructions appearing in the second instruction set in the target instruction stream are I-decoded to prefetch operations, and all conditional access instructions in the first (main) set Stop until the branch instruction is resolved (but go ahead and
Compute the relative target address and store it in the target register).

3.2.6 If the conditional branch in the first instruction set is interpreted as "taken": 3.2.6.1 the source of the branch is the EBUF instruction set determined from the procedure in progress bit If so, flush the instruction set placed after the first conditional flow instruction set in the MBUF or EBUF.

3.2.6.2 Based on the state of the Procedure In Progress bit, the TBUFPFnPC value is
Transfer to PFnPC or EBUF.

3.2.6.3 Transfer the prefetched TBUF instruction to MBUF or EBUF based on the state of the procedure in progress bit.

3.2.6.4 If the second conditional branch instruction set has not been I-decoded, MBUF or E based on the state of the procedure-in-progress bit
Continue the BUF prefetch operation.

3.2.6.5 If the second conditional branch instruction has been I-decoded, the processing of that instruction is started (go to step 3.3.1).

3.2.7 If conditional control for instructions in the first conditional instruction set is interpreted as "do not perform": 3.2.7.1 Instruction set and instruction from target instruction stream Flush the IFIFO and IEU.

3.2.7.2 MBUF or EBUF
Continue the prefetch operation.

3.3 For "Bias without Branching": 3.3.1 Stop prefetching instructions into MBUF. Continue the run cycle.

3.3.1.1 If the conditional control flow instruction in the first set of conditional instructions is relative, calculate the target address and store it in the target register.

3.3.1.2 If the conditional control flow instruction in the first set of conditional instructions is absolute, the IEU
Calculates the target address and waits for the address to be returned to the target register.

3.3.1.3 When I-decoding of a conditional control flow instruction in the second instruction set is performed,
Stop the prefetch operation until the conditional control flow instruction in the first set of conditional instructions is resolved.

3.3.2 Once the target address of the first conditional branch is calculated, TBUF PFn
Load into the PC and begin prefetching instructions into the TBUF in parallel with execution of the main instruction stream. The target instruction set is not loaded (therefore, a branch target instruction is provided when each conditional control flow instruction in the first instruction set is resolved).

3.3.3 If the conditional control flow instruction in the first set is interpreted as "taken": 3.3.3.1 Procedure in progress if source of branch is EBUF instruction stream Flush the MBUF or EBUF as determined by the state of the bit,
Flush the IFIFO and IEU of instructions from the main instruction stream placed after the first conditional branch instruction set.

3.3.3.2 Transfer the TBUF PFnPC value to the MBUF or EBUF as determined by the state of the Procedure In Progress bit.

3.3.3.3 Prefetched TBU as determined from the state of the procedure in progress bit
Transfer the F instruction to MBUF or EBUF.

3.3.3.4 MBUF or EBUF as determined from the state of the procedure in progress bit
Continue the prefetch operation.

3.3.4 If Conditional Control Flow Instructions in First Set Are Analyzed as "Not Performed": 3.3.4.1 Flush Instruction Set TBUF from Target Instruction Stream.

3.3.4.2 If the second conditional branch instruction was not I-decoded, continue the MBUF or EBUF prefetch operation as determined by the state of the procedure in progress bit.

3.3.4.3 If the second conditional branch instruction has been I-decoded, processing of that instruction is started (go to step 3.4.1). 4. Interrupt, Exception and Trap Instructions 4.1 Traps are broadly defined as follows.

4.1.1 Hardware Interrupt 4.1.1.1 Asynchronous (External) Occurring Event, Internal or External.

4.1.1.2 Generates and persists at any time.

4.1.1.3 Receive service among atomic (normal) instructions in priority order and suspend procedure instructions.

4.1.1.4 The start address of the interrupt handler is determined as a vector number offset to a predefined table at the entry point of the trap handler.

4.1.2 Software Trap Instruction 4.1.2.1 Asynchronous (External) Generated Instruction

4.1.2.2 Software instructions executed as exceptions.

4.1.2.3 The starting address of the trap handler is determined from the trap number offset combined with the base address value stored in the TBR or FTB register.

4.1.3 Exceptions 4.1.3.1 Events that occur in synchronization with an instruction.

4.1.3.2 Processed when an instruction is executed.

4.1.3.3 The instruction expected by the result of the exception and all subsequently executed instructions are cancelled.

4.1.3.4 The starting address of the exception handler is determined from the trap number offset to the predefined table at the trap handler entry point.

4.2 Trap Instruction Stream Operations are performed inline with the currently executing instruction stream.

4.3 Traps can be nested, provided that the trap handling routine saves the xPC address before the next interruptible trap. Otherwise, if a trap appears before the completion of the current trap operation, the state of the machine will be corrupted. 5. Processing the Trap Instruction Stream: xPC 5.1 When a Trap Appears: 5.1.1 When an asynchronous interrupt occurs, execution of the instruction currently executing is suspended.

5.1.2 When a synchronous exception occurs, the trap is processed when the instruction that caused the exception is executed.

5.2 When a trap is processed: 5.2.1 Interrupts are disabled.

5.2.2 Current IF The PC address is stored in the xPC trap status return address register.

5.2.3 The IF_PC address and the IFIFO and MBUF prefetch buffer at the address following it are flushed.

5.2.4 The executed instruction at address IF_PC and the subsequent address and the result of the instruction are IE
Flushed from U

5.2.5 MBUF PFnPC is loaded with the address of the trap handler routine.

5.2.5.1 The source of the trap is addressing the TBR or FTB register, depending on the trap type as determined by the trap number contained in the special register group.

5.2.6 Instructions are prefetched and put into IFIFO for normal execution.

5.2.7 The instructions of the trap routine are then executed.

5.2.7.1 The trap processing routine has the function of saving the xPC address to a predetermined location, and enables the interrupt again. The xPC registers are read and written by special register move instructions and through the special register address and data bus.

5.2.8 It is necessary to exit the trap state by executing a return from the trap instruction.

5.2.8.1 If previously saved, the xPC address must be restored from its pre-defined location before returning from the trap instruction.

5.3 When a return from a trap instruction is executed: 5.3.1 Interrupts are enabled.

5.3.2 As determined from the state of the procedure-in-progress bit, the xPC address is the current instruction stream register MBUF or EBUF P
Returned to FnPC, prefetching continues from that address.

5.3.3 The xPC address is restored to the IF_PC register through the new stream register.

E) Handling of Interrupts and Exceptions 1) Overview Interrupts and exceptions, as long as they are enabled, indicate whether the processor is executing from the main instruction stream,
Processed regardless of whether it is being executed from the procedural instruction stream. Interrupts and exceptions are serviced in priority order and persist until cleared. trap·
The start address of the handler is determined as a vector number offset to the trap handler's predefined table, as described below.

In this embodiment, there are basically two types of interrupts and exceptions. That is, those that are triggered synchronously with specific instructions in the instruction stream and those that are triggered asynchronously with specific instructions in the instruction stream. Interrupts, exceptions, traps and faults (f
The term “ult” is used interchangeably herein. Asynchronous interrupts are caused by on-chip or off-chip hardware that is not operating synchronously with the instruction stream. For example, an interrupt caused by an on-chip timer / counter may be a hardware interrupt or a non-maskable interrupt caused by an off-chip.
Like asynchronous (NMI), it is asynchronous. When an asynchronous interrupt is triggered, the processor context is frozen, all traps are disabled, some processor status information is stored, and the processor sends a vector to the interrupt handler corresponding to the particular interrupt received. Turn. When the interrupt handler has completed its processing, program execution continues with the instruction following the last completed instruction in the stream being executed at the time of the interrupt.

A synchronous exception is an exception that is caused in synchronization with an instruction in an instruction stream. These exceptions are raised in connection with a particular instruction and are suspended until the instruction in question is executed. In the preferred embodiment, the synchronization exception is raised during prefetch, instruction decode, or instruction execution. For prefetch exceptions, for example, TLB
There are mismatches and other VMU exceptions. The decode exception is
For example, the instruction being decoded is an illegal instruction, or the current privilege level of the processor (privilege level).
If it does not match l), it is triggered. Execution exceptions are caused, for example, by arithmetic errors such as division by zero. When these exceptions occur, the preferred embodiment associates the particular instruction that caused the exception with the exception and maintains that state until the instruction is retired. At that point, all previously completed instructions are saved and any trial results from the instruction that caused the exception are flushed, as are the trial results of subsequent trial-executed instructions. Thereafter, control is passed to the exception handler corresponding to the highest priority exception caused by the instruction.

The software trap instruction is CF_DE
It is detected in the I decode stage by T274 (FIG. 2) and is processed like an unconditional call instruction or other synchronous trap. That is, the target address is calculated and the prefetch continues to the current prefetch queue (EBUF or MBUF). At the same time, the exception is recorded in association with the instruction and processed when the instruction is saved. All other types of synchronous exceptions are only recorded and accumulated in association with the specific instruction that caused the exception, and are handled at runtime.

2) Asynchronous Interrupt Asynchronous interrupt is notified to the PC logic unit 270 through the interrupt line 292. As shown in FIG. 3, these lines are for notifying the interrupt logic unit 363 in the PC logic unit 270, and include an NMI line, an IRQ line, and a set of interrupt level lines (LVL). I have. The NMI line reports a non-maskable interrupt and originates from an external source. This is the highest priority interrupt except for a hardware reset. The IRQ line also originates from an external source and signals when an external device has requested a hardware interrupt. In the preferred embodiment, up to 32 externally generated hardware interrupts can be defined by the user, and the specific external device that requested the interrupt has the interrupt number (0-3) on the interrupt level line (LVL).
Send out 1). Memory error line is MCU11
Activated by 0 to signal various types of memory errors. Other asynchronous interrupt lines (not shown) are also provided to notify the interrupt logic unit 363. These include timers /
Counter interrupt, memory input / output (I / O) error interrupt, machine check interrupt, and performance
There is a line to request a monitor interrupt. Each of the asynchronous interrupts is associated with a corresponding predefined trap number, similar to the synchronous exceptions described below. Thirty-two of these trap numbers are associated with thirty-two hardware interrupt levels. A table of these trap numbers is maintained in the interrupt logic unit 363. Generally, the higher the trap number, the higher the priority of the trap.

When one of the asynchronous interrupts is notified to the interrupt logic unit 363, the interrupt control unit 36
3 sends an interrupt request to the INT REQ / ACK line 340
To the IEU 104 via. Also, the interrupt control unit 363 sends a prefetch suspend signal to line 3
43 and transmitted to the PC control unit 262 via the PC.
Causes control unit 262 to stop prefetching instructions. The IEU 104 cancels all currently executing instructions, aborts all trial results, or completes some or all instructions. In a preferred embodiment,
The response to the asynchronous interrupt is speeded up by canceling all the instructions being executed at that time. In any case, the DPC in the execution PC control unit 366
Is updated to correspond to the last completed and saved instruction before the IEU 104 acknowledges receipt of the interrupt. Prefetched and MBUF, EBUF, TBUF
And all other instructions located in IFIFO 264 are also canceled.

The IEU 104 sends an interrupt acknowledgment signal back to the interrupt control unit 363 via the INT REQ / ACK line 340 only when it is ready to receive an interrupt from the interrupt handler. Upon receiving this signal, the interrupt control unit 363 dispatches to the appropriate trap handler, as described below.

3) Synchronous Exception In the case of a synchronous exception, the interrupt control unit 363 sets four internal exception bits (not shown) for each instruction set.
And each bit is associated with each instruction in the set. The interrupt control unit 363 also maintains the trap number to be notified when found in each instruction.

If the VMU reports a TLB mismatch or another VMU exception while a particular instruction set is being prefetched, this information is used by the PC logic unit 27.
0, especially to the interrupt control unit 334 via the VMU control lines 332, 334. Upon receiving this signal, the interrupt control unit 363 transmits the signal via the line 343 to the PC so as to suspend the subsequent prefetch.
The control unit 362 is notified. At the same time, the interrupt control unit 363 sends the VM associated with the prefetch buffer to which the instruction set is sent. Miss or V
Set the corresponding one of the M_Excp bits. Thereafter, the interrupt control unit 363 sets all four internal exception indicator bits corresponding to the instruction set, since none of the instructions in the instruction set are valid,
Store the trap number of the particular exception received for each of the four instructions in the offending instruction set. Shifting and execution of instructions prior to the offending instruction continue as usual until the offending instruction set reaches the lowest level in the IFIFO 264.

Similarly, the prefetch buffer 260,
If another synchronization exception is detected while shifting an instruction through the I decode unit 262 or IFIFO 264, this information is also sent to the interrupt control unit 363, and the unit 363 sends the information to the internal control corresponding to the instruction that caused the exception. Set the exception indicator bit and store the trap number corresponding to the exception. As with the prefetch synchronous exception, shifting and executing the instruction prior to the offending instruction will cause the instruction set in question to
Will continue as usual until the lowest level is reached.

In the preferred embodiment, the prefetch buffer 260, I decode unit 262 or IFIFO
The only exception detected while shifting instructions through H.264 is one type of software trap instruction. The software trap instruction is detected by the CF_DET unit 274 at the I decode stage. In some embodiments, other forms of synchronization exceptions are detected in the I decode stage, but detection of other synchronization exceptions
It is preferable to wait until the instruction arrives at the execution unit 104. This prevents certain exceptions, such as those that occur when processing privileged instructions, from being signaled based on processor states that may change before the instructions are effectively executed in order. You. Exceptions that are not dependent on processor state, such as illegal instructions, can be detected in the I decode stage, but if all pre-execution synchronization exceptions (apart from VMU exceptions) are detected in the same logic, at a minimum, Hardware. Also, the handling of such exceptions is rarely time-critical, so there is no time wasted waiting for instructions to reach execution unit 104.

As described above, the software trap instruction is detected by the CF_DET unit 274 at the I decode stage. Interrupt logic unit 3
The internal exception indicator bit corresponding to the instruction in 63 is set, and the software trap number, which is a number from 0 to 127 and can be specified in the immediate mode field of the software trap instruction, is stored in association with the trap instruction. You. However, unlike the prefetch synchronous exception, the software trap is treated not only as a control flow instruction but also as a synchronous exception. The control unit 362 is not notified. Instead, the instruction is IFIF
At the same time as shifting through O264, IFU10
2 prefetches the trap handler into the MBUF instruction stream buffer.

When the instruction set reaches the lowest level of the IFIFO 264, the interrupt logic unit 363 sets the exception indicator bits of the instruction set to SYNCH as a 4-bit vector. INT The command is sent to the IEU 104 via the INFO line 341 to notify the IEU 104 of the instruction set, if any, which has been determined to be the source of the synchronous exception. The IEU 104 does not respond immediately,
Ensure that all instructions in the instruction set are scheduled in the usual way. Other exceptions, such as the integer arithmetic exception, may be raised at run time. Exceptions that depend on the current state of the machine, such as exceptions caused by the execution of privileged instructions, are also detected at this point, ensuring that the state of the machine is current for all previous instructions in the instruction stream. To do so, all instructions that can affect the PSR (such as special moves and returns from trap instructions) are forced to execute in order. The interrupt logic unit 363 is notified that an exception has occurred only immediately before the instruction that caused the source of any synchronous instruction is saved.

The IEU 104 is executed on a trial basis, saving all instructions that appear in the instruction stream preceding the first instruction that caused the synchronization exception, and executing from the instruction that was executed on a trial basis and appeared later in the instruction stream. Flush the trial results of The specific instruction that caused the exception is
Since it is normal to re-execute when returning from the trap,
This instruction is also flushed. After that, the IF_PC in the execution PC control unit 366 is updated to correspond to the last instruction actually saved, and the exception is notified to the interrupt control unit 363.

When the instruction which is the source of the exception is saved,
The IEU 104 stores the saved instruction set (register 22
If there is an instruction that caused a synchronous exception in 4), a new 4-bit vector indicating which instruction was used, together with information indicating the source of the first exception in the instruction set, is set to S.
Return to the interrupt logic unit 363 via the YNCH_INT_INFO line 341. IEU10
The information contained in the 4-bit exception vector returned from 4 is transmitted from the interrupt logic unit 363 to the IEU 10
4 is the accumulation of the 4-bit exception vector passed to 4 and the exceptions raised in the IEU 104. If there is information already stored in the interrupt control unit 363 due to an exception detected at the time of prefetching or I-decoding, the rest of the information returned from the IEU 104 to the interrupt control unit 363 together with the information is the interrupt control unit. Sufficient for unit 363 to determine the contents of the highest priority synchronization exception and its trap number.

4) Handler dispatch and return An interrupt acknowledgment signal is sent via line 340 to the IEU 104
Or a non-zero exception vector is received via line 341 and the current DPC is temporarily stored as the return address in the xPC register, one of the special registers 412 (FIG. 4). You. The current processor status register (PSR) stores the previous PSR (PPS).
R) register, and the current state comparison register (CSR) is saved in the old state comparison register (PCSR) in the special register 412.

The address of the trap handler is calculated as the trap base register address plus an offset. PC logic unit 270 has two base registers for traps, both of which are part of special register 412 (FIG. 4) and are initialized by a previously executed special move instruction. For most traps, the base register used to calculate the address of the handler is the trap base register TBR.

The interrupt control unit 363 determines the highest priority interrupt or exception that is currently pending and
-Up) Through the table, determine the trap number associated with it. This is a set of INT_OFFSE as an offset to the selected base register.
The data is passed to the prefetch PC control unit 364 via the T line 373. The vector address has the advantage that it can be obtained simply by concatenating the offset bit as the lower bit with the upper bit obtained from the TBR register. Therefore, a delay of the adder is prevented. (In this specification, the 2 'bit is the i'th bit.) For example, if the trap number is 0 to 255,
Expressing this as an 8-bit value, the handler address is determined by concatenating the 8-bit trap number to the end of the 22-bit TBR store value. Adding the two least significant bits to the trap number will cause the trap handler address to always be on a word boundary. The concatenated handler address thus created is used as one of the inputs 373 as the prefetch selector PF. PCSel390
(FIG. 4) and is selected as the next address from which the instruction is prefetched. All vector handler addresses for traps using the TBR register are one word apart. Therefore, the instruction at the trap handler address must be a preliminary branch instruction to the longer trap handling routine. However, there are some traps that need to be handled with care to prevent degradation of system performance. For example, the TLB trap needs to be executed at high speed. For that reason, the preferred embodiment incorporates a fast trap mechanism that allows a small trap handler to be invoked without the expense of a spare branch. In addition, the fast trap handler can be independently located in memory, for example, in an on-chip ROM, eliminating memory system problems associated with RAM locations.

In the preferred embodiment, the only traps that result in fast traps are the VMU exceptions described above. Fast trap numbers are distinguished from other traps and range from 0-7. However, the priority is the same as the MMU exception. The interrupt control unit 363, upon recognizing that the fast trap is the highest priority then pending, a special register (FT
Select the fast trap base register (FTB) from B) and send out on line 416 to combine with the trap offset. Prefetch Seleta PF via line 373 ' The resulting vector address sent to PC Sel 390 is the upper two bits from the FTB register.
A concatenation of two bits, followed by three bits representing the fast trap number, followed by seven zero bits. Thus, each fast trap address is 128 bytes, or 32 words apart.
When called, the processor branches to the start word and causes the program to execute in the block or branch out of it. Execution of a small program, such as a standard TLB processing routine that can be implemented with 32 or fewer instructions, is faster than a normal trap because a preliminary branch to the actual execution routine is avoided. .

In the preferred embodiment, all instructions are the same four bytes long (ie, occupy four address locations), but it should be noted that even in microprocessors where instructions are of variable length, A fast trap mechanism is available. In this case, of course, there is sufficient space between the fast trap vector addresses to accept at least two, and preferably 32, average size instructions available in the microprocessor. . Of course, if the microprocessor has a return from trap instruction, there must be enough space between the vector addresses to place at least one other instruction in the handler at that instruction. There is.

When dispatching to the trap handler, the processor enters a kernel mode and an interrupt state. In parallel, a copy of the status comparison register (CSR) is placed in the previous carry status register (PCSR) and a copy of the PSR is stored in the previous PSR (PPSR). Kernel and interrupt state modes are represented by bits in the processor status register (PSR). Current PS
When the interrupt status bit of R is set, the shadow or trap registers RT [24] -RT
[31] becomes visible as described above and as shown in FIG. 7 (B). The interrupt handler can exit kernel mode simply by writing the new mode to the PSR, but the only way to exit the interrupt state is to execute a return from trap (RTT) instruction.

When the IEU 104 executes the RTT instruction,
The interrupt status bits in the PSR are automatically cleared because the PCSR is restored to the CSR register and the PPSR register is restored to the PSR register. PF_PC S
EL selector 390 selects special register xPC in special register set 412 as the next address to prefetch therefrom. xPC is the incrementer 39
4 and the bus 396, the data is restored to MBUF PFnPC or EBUF PFnPC, whichever is applicable. The decision whether to restore the xPC to EBUF PFnPC or MBUFPFnPC is made according to the “procedure in progress” bit of the restored PSR.

It should be noted that the processor does not use the same special register xPC to store the return address for both trap and procedure instructions. The return address of the trap is stored in the special register xPC as described above, but the address to which the return is made after the procedure instruction is stored in another special register uPC. Thus, the interrupt state remains available while the processor is executing the emulation stream called with procedural instructions. On the other hand, the exception handling routine has no special register to store the address to return to the exception handler after the emulation stream has completed,
Must not contain any procedural instructions.

5) Nest Certain processor status information includes trap handlers,
In particular, CSR, PSR, return PC and, in a sense, "A" register sets ra [64] -ra [31]
It is automatically backed up when dispatching, but other context information is not protected. For example, the contents of the floating point status register (FSR) are not automatically backed up. In order for the trap handler to change these registers, it must perform its own backup.

The nesting of traps is not automatic because of the limited backups that are automatically performed when dispatching to the trap handler. The trap handler must back up necessary registers, clear interrupt conditions, read information required for trap processing from system registers, and process the information appropriately. Interrupts are automatically disabled when dispatched to a trap handler. When finished, the handler can restore the backed up registers, enable interrupts again, and execute the RTT instruction to return from the interrupt.

To enable nested traps,
The trap handler needs to be split into a first part and a second part. The first part requires that the xPC be copied using a special register move instruction and pushed onto the stack maintained by the trap handler while interrupts are disabled. Next, the start address of the second part of the trap handler must be moved to the xPC using a special register move instruction and a return from trap (RTT) instruction must be executed. The RTT removes the interrupt state (by restoring the PPSR to the PSR) and transfers control to the address in the xPC. xPC has
Contains the address of the second part of the handler. The second part can enable interrupts at this point and continue processing the exception in interrupt enabled mode. It should be noted that the shadow registers RT [24] -RT [31] are only visible in the first part of this handler and not in the second part. Thus, in the second part, the handler needs to reserve the value of the "A" register, if the value can be changed by the handler. When the trap processing routine is completed, all registers backed up are restored and the original xPC
Must be popped out of the trap handler stap and returned to the xPC special register using a move special register instruction to perform another RTT. This returns control to the corresponding instruction in the main or emulation instruction stream.

6) Trap List The following Table 1 shows the trap numbers, priorities and processing modes of the traps recognized in the preferred embodiment.

[Table 1] Asynchronous / Trap Number Processing Mode Synchronous Trap Name 0-127 Normal Synchronous Trap Instruction 128 Normal Synchronous FP Exception 129 Normal Synchronous Integer Arithmetic Exception 130 Normal Synchronous MMU (excluding TLB mismatch or correction) 135 Normal Synchronous Unaligned memory address 136 Normal synchronous Illegal instruction 137 Normal synchronous Privileged instruction 138 Normal synchronous Debug exception 144 Normal asynchronous Performance monitor 145 Normal asynchronous Timer / counter 146 Normal asynchronous memory I / O error 160-191 Normal asynchronous Hardware interrupt 192-253 Reserved 254 Normal asynchronous machine check 255 Normal asynchronous NMI 0 High-speed trap synchronization High-speed MMU TLB mismatch 1 High-speed trap synchronization High-speed MMU TLB correction 2-3 High-speed track synchronization High-speed Reserved) 4-7 fast trap synchronous high-speed (reserved) III. Instruction execution unit Figure 5 illustrates a control path portion and a data path portion of IEU104. The main data path is IFU102
From the instruction / operand data bus. As a data bus, the immediate operand is passed to the operand alignment unit 470 and passed to the register file (REG ARRAY) 472. Register data is passed from the register file 472 via the register file output bus 476 to the bypass unit 4.
74, via a distribution bus 480 to a parallel array of functional computing elements (FU _0-n ). The data generated by the functional units 478 _0-n is
It is sent back via 82 to the bypass unit 474 or the register array 472 or both.

The load / store unit 484 completes the data path portion of the IEU 104. Road/
Store unit 484 consists of IEU 104 and CCU 106
Responsible for managing data transfer between Specifically, CCU
The load data retrieved from the data cache 134 of the register 106 is transferred to the register array 4 via the load data bus 486 by the load / store unit 484.
72. Data stored in the data cache of the CCU 106 is allocated to the functional unit distribution bus 480.
Received from.

The control path portion of the IEU 104 is responsible for sending, managing, and processing information passing through the IEU data path. In a preferred embodiment of the invention, the IEU control path has the function of managing the concurrent execution of multiple instructions,
The EU data path has the function of independently performing multiple data transfers between almost all data path elements of the IEU 104. The IEU control path is an instruction / operand
When a command is received via the bus 124, it operates accordingly. Specifically, the instruction set is received by E-decode unit 490. In the preferred embodiment of the present invention, E decode unit 490 includes an IFIFO master unit.
It receives and decodes both instruction sets held in registers 216 and 224. The result of decoding all eight instructions is the carry checker (CRY CHKR).
Unit 492, Dependency Checker (DEP CHKR)
Unit 494, Register Renaming Unit (REG RE
NAME) 496, an instruction issue (ISSUER) unit 498, and an evacuation control unit (RETIRE CL)
T) 500.

Carry checker unit 492 is E
Decode information is received from decode unit 490 via control line 502 for the eight pending pending instructions. The function of the carry checker 492 is to identify the pending instructions that affect the carry bit of the processor status word or that are dependent on the state of the carry bit. This control information is sent to the instruction issuing unit 498 via the control line 504.

Decoding information indicating the registers in the register file 472 used by the eight pending instructions is sent directly to the register rename unit 496 via the control line 506. This information is also sent to the dependency checker unit 494. The function of the dependency checker unit 494 is to determine which of the pending instructions refer to a register as a data destination,
The determination, if any, of which instruction depends on any of these destination registers. Register dependent instructions are identified by control signals sent to register rename unit 496 via control line 508.

Finally, the E decode unit 490 sends control information identifying the specific contents and function of each of the eight pending instructions to the instruction issuing unit 498 via the control line 510. The instruction issuing unit 498 is responsible for determining data path resources, in particular, which functional units are available for execution of pending instructions. According to a preferred embodiment of architecture 100, instruction issuance unit 498 executes any of the eight pending instructions out of order, subject to data path resources being available and constraints on carry and register dependencies. It can be so. The register renaming unit 496 sends the bit map of the appropriately unrestricted instruction to be executed to the instruction issuing unit 498 via the control line 512.
Instructions that have already been executed (completed) and instructions that depend on registers or carry are logically removed from the bit map.

The instruction issuing unit 498 depends on whether the required functional units 478 _0-n are available.
Can start executing multiple instructions in each system clock cycle. The status of the functional units 478 _0-n is transmitted via the status bus 514 to the instruction issuing unit 498.
Sent to A control signal for starting the execution of the instruction and performing the execution management after the start is sent from the instruction issuing unit 498 to the register renaming unit 496 via the control line 516, and selectively to the functional units 478 _0-n . Sent. Upon receiving the control signal, the register renaming unit 496
Sends a register select signal on the register file access control bus 518. Which register is enabled by the control signal sent on bus 518 is determined by selecting the instruction being executed and by register renaming unit 496 determining the register referenced by that particular instruction. Is done.

The bypass control unit (BYPASS C)
TL) 520 is generally controlled on control line 524.
Control signal to bypass data routing unit.
The operation of the toto 474 is controlled. Bypass control unit 5
20 is a functional unit 478_{0- n}Monitor each situation of
And register rename unit via control line 522.
Data related to the register reference sent from 496
Data from the register file 472 to the functional unit 478
_0-nWhether to send to or functional unit 478
_0-nThe data output from is bypass unit 474
Immediately to the functional unit destination bus 480 via
Newly issued instruction selected by instruction issuing unit 498
To determine if it can be used for execution. Which
In this case, the instruction issuing unit 498 is
8_0-nSelective use of specific register data for each
By enabling it, the destination
478_0-nDirect control over sending data.

The remaining units on the IEU control path include an evacuation control unit 500 and a control flow control (CF CT
L) Unit 528 and completion control (DONE CT)
L) There is a unit 536. The evacuation control unit 500 operates to invalidate or confirm execution of instructions executed out of order. When an instruction is executed out of order, the instruction can be acknowledged or saved if all preceding instructions have also been saved. 8 of pending status in the current set
The identification information of which of the instructions was executed is stored in the control line 53.
2, the evacuation control unit 500 sends a control signal on a control line 534 connected to the bus 518 based on the identification information, and
Is effectively confirmed as a result of pre-execution of an instruction executed out of order.

The save control unit 500 sends a PC increment / size control signal to the IFU 102 via the control line 344 when saving each instruction. Since multiple instructions can be executed out of order, and thus can be placed in a ready state to be saved simultaneously, the save control unit 500 determines the size value based on the number of instructions saved at the same time. Finally, when all the instructions of the IFIFO master register 224 have been executed and saved, the save control unit 500 sends the IFIFO read control signal to the control line 3.
By sending to IFU 102 via 42 and initiating the shift operation of IFIFO unit 264, E decode unit 490 is given four additional instructions as execution pending instructions.

The control flow control unit 528 has a specialized function of detecting a logical branch result of each conditional branch instruction. The control flow control unit 528 determines which of the currently pending conditional branch instructions
The bit vector ID is received from the E decode unit 490 via the control line 510. An 8-bit vector instruction completion control signal is similarly received from completion control unit 540 via control line 538.
By the completion control signal, the control flow control unit 5
28 can determine when a conditional branch instruction has completed to a point sufficient to determine a conditional control flow status. The control flow status result of the pending conditional branch instruction is stored by the control flow control unit 528 during its execution. The data required to determine the result of the conditional control flow instruction is obtained from the temporary status register in register array 472 from control line 5.
Obtained via 20. As each conditional control flow instruction is executed, control flow control unit 528 outputs a new control flow result signal via control line 348 to the IF.
Send to U102. In the preferred embodiment, the control flow result signal includes two 8-bit vectors, which are the status results for each of the eight potentially pending control flow instructions by bit position. Are defined, and the corresponding status result states obtained by the bit position mapping.

Finally, the completion control unit 540 is a function unit.
Knit 478_0-nExecution for each operation of
It is for monitoring the situation. Function unit 47
8_{0- n}Either of
Upon completion, the completion control unit 540 determines the corresponding completion control
A signal is sent out on the control line 542 to change the register
Unit 496, instruction issuing unit 498, evacuation control unit
Alarm to the cut unit 500 and the bypass control unit 520.
(Warning).

By making the functional units 478 _on in a parallel array configuration, the control consistency of the IEU 104 is improved. In order to correctly recognize an instruction and schedule it for execution, it is necessary to inform the instruction issuing unit 498 of the characteristics of the individual functional units 478 _on . The functional unit 478 _on determines the specific control flow operation required to perform the required function,
Responsible for performing. Therefore, the instruction issuing unit 4
Other than 98, the IEU control unit need not be independently informed of the control flow processing of instructions. The instruction issuing unit 498 and the functional unit 478 _{on work} together to form the remaining control flow management units 496, 500, 520, 52
8 and 540 are notified of the function to be executed by a prompt of a necessary control signal. Therefore, a change in the specific control flow operation of the functional unit 478 _on is
4 does not affect the control operation. Furthermore, when enhancing the function of the existing functional unit 478 _on , the extended precision floating point multiplication unit and the extended precision floating point AL
U, a fast Fourier calculation function unit, a trigonometric function calculation unit, etc., even if one or more additional function units 478 _on are added, the instruction issuing unit 498
Only needs to be changed slightly. To make the necessary changes,
Based on the corresponding instruction field isolated by the E-decode unit 490, it is necessary to recognize a particular instruction and associate that instruction with the required functional unit 478 _on . The control of register data selection, data routing, instruction completion and saving are performed by the functional unit 47.
8 _on is compatible with the processing of all other instructions executed for all other functional units.

A) Details of the IEU data path The element at the center of the IEU data path is a register
File 472. However, according to the present invention, the IE
Within the U data path, there are several parallel data paths that are optimized for individual functions. There are two main data paths, integer and floating point. Within each parallel data path, a portion of the register file 472 is adapted to support data operations performed within that data path.

1) Details of Register File FIG. 6A is a schematic diagram of a preferred architecture of the data path register file 550. The data path register file 550 contains a temporary buffer 552, a register
It includes a file array 564, an input selector 559, and an output selector 556. Finally register array 5
64 is coupled to the combined data input bus 558 '.
Is received first by the temporary buffer 552 via the. That is, all data sent to data path register file 550 is input selector 5
And multiplexed by 59 on a plurality of input buses 558 (preferably two) on input bus 558 '. The register select and enable control signals provided on control bus 518 select the register location of the received data in temporary buffer 552. When the instruction that generated the data stored in the temporary buffer is saved,
The control signal transmitted again on the control bus 518 permits the transfer of data from the temporary buffer 552 to the logically associated registers in the register file array 564 via the data bus 560. However, before the instruction is saved, the data stored in the temporary buffer 552 is the same as the data stored in the temporary buffer.
By sending it to the output data selector 556 via the bypass portion of the bus 560, it can be used when executing subsequent instructions. The selector 556 controlled by a control signal sent via the control bus 518 selects either data from a register in the temporary buffer 552 or data from a register in the register file array 564. The resulting data is sent out on register file output bus 554. If the instruction being executed is saved simultaneously with completion, that is, if the instruction is executed in order, the result data is transferred to the bypass extension 55.
It can be instructed to send directly to register array 564 via 8 ".

According to a preferred embodiment of the present invention, each datapath register file 550 is capable of performing two register operations simultaneously. Therefore, the input bus 558
Through the temporary buffer 5
52. Internally, since the temporary buffer 552 has a multiplexer arrangement, input data can be sent to any two registers in the temporary buffer 552 at the same time. Similarly, any five registers of the temporary buffer 552 can be selected by the internal multiplexer to output data on the bus 560. Since register file array 564 also has a human output multiplexer, two registers can be selected to receive their respective data simultaneously from bus 560, or five registers can be selected via bus 562. You can also send it. Finally, the register file output selector 556 receives the 10
Preferably, any five of the register data values are output simultaneously on register file output bus 554.

The register set in the temporary buffer is shown in FIG.
(B) shows the outline. Register set 5
52 'are eight single word (32 bit) registers I0RD, I1RD. . . It consists of I7RD. Register set 552 'comprises four double word registers I0RD, I0RD + 1 (I0RD4), I
1RD, I1RD + 1 (ISRD ... I3RD, I3
It is also possible to use it as a set of RD + 1 (I7RD).

According to a preferred embodiment of the present invention, the register
The cost of providing duplicate registers in the file array 564
Instead, the buffer in temporary buffer register set 552
The register has two IFIFO master registers 216, 2
Based on the relative location of each instruction in 24
And referenced by the register rename unit 496.
Each instruction implemented in the architecture 100 has a maximum of two instructions.
Up to one register or one double-word register
Data generated by the execution of the instruction, referring to the
Data destination. A typical example is life
The instruction references only one output register. Therefore,
As shown in FIG. 6 (C), eight pending lives
Instruction 2 (I_Two)
In the case of, the data destination register I2RD is selected and
Accept the data generated by the execution of the instruction. life
Ordinance I_TwoThe data generated by the
If I _FiveIf used by the I2RD register
The data stored in the bus is transferred via the bus 560.
And the resulting data is sent back to temporary buffer 552.
And stored in the register indicated by I5RD. In particular,
Instruction I_FiveIs the instruction I_TwoInstruction I_FiveIs
I_TwoCan be executed until the result data from
Can not. However, as will be appreciated, instruction I_FiveIs necessary
Of the temporary buffer 552 '_Twoof
Given the data location, instruction I_TwoBefore evacuation of
It is possible to do.

Finally, when the instruction I ₂ is saved, the data from the register I ₂ RD is written to the register location in the register file array 564, as determined from the logical position of the instruction at the save location. That is, the save control unit 560 determines the address of the destination register in the register file array from the register reference field data provided from the E decode unit 490 via the control line 510. When instruction I _0-3 is saved, I
The value contained in the 4RD-I7RD is shifted simultaneously with the shift of the IFIFO unit 264, so that the I0RD-I
Moved to 3RD.

[0199] If a double word result value is obtained from the instruction I ₂ is further complicated. According to a preferred embodiment of the present invention, location I2RD a combination of I6RD is either the instruction I ₂ is retracted, or otherwise until canceled, is used to keep stores the result data from the instruction You. In the preferred embodiment, execution of instructions I _4-7 is suspended if a reference to the double word output by any of instructions I _0-3 is detected by register rename unit 496. Thereby, the temporary buffer 55
The entire 2 'can be used as a single rank of double word register. When instructions I _0-3 are evacuated, temporary buffer 552 'becomes single word
It can be used again as two ranks of registers. Furthermore, the execution of any instruction I _4-7 depends on whether the instruction corresponds to the corresponding I _0-3 if a double word output register is required.
Held until shifted to.

The logical organization of the register file array 564 is shown in FIGS. According to a preferred embodiment of the present invention, the register file array 564 for the integer data path is comprised of 40 32-bit wide registers. This register set constitutes register set “A” and base register set ra
[0. . 23] 565, general-purpose register ra [24. . 3
1] 566, and eight general-purpose trap registers ra [24. . 31] as a shadow register set. In normal operation, the general-purpose register ra [0. . 31]
Reference numerals 565 and 566 constitute an active "A" register set of the register file array for the integer data path.

As shown in FIG. 7B, the trap register ra [24. . 31] If 567 is swapped and moved to the active register set “A”, the register ra [0. . 23] 565 with the active base set. This configuration of the "A" register set is selected upon receipt of an interrupt or execution of an exception trap handling routine. This state of register set "A" is maintained until it explicitly returns to the state shown in FIG. 7A by execution of an interrupt enable instruction or execution of a return instruction from a trap.

In the preferred embodiment of the present invention implemented by architecture 100, the floating point data path is shown in FIG.
The extended precision register file array 572 is used as shown in FIG. Register file array 572
Are 32 registers rf, each 64 bits wide
[0. . 31]. The floating-point register file 572 stores the integer register rb [0. . 31]
Can be logically referred to as the “B” set. In architecture 100, this "B" set of registers is a floating point register rf [0. . 31], respectively, corresponding to the lower 32 bits.

A Boolean operator register set 574 is provided to represent the third data path, as shown in FIG. It stores the logical result of a Boolean operation. This "C" register set 574 contains 32 1
Bit register rc [0. . 31]. The operation of Boolean register set 574 stores the result of the Boolean operation in Boolean register set 574.
4 is unique in that it can be sent to any instruction select register. This is equal, unequal, greater,
1 bit that represents a condition such as other simple Boolean status values
A single processor status word that stores the flag
In contrast to using registers.

The floating point register set 572 and the Boolean register set 574 are both complemented by a temporary buffer of the same architecture as the integer temporary buffer 552 shown in FIG. The basic difference is that the width of the temporary buffer register is defined to be the same as the width of the complemented register file arrays 572,574. In the preferred embodiment, the widths are 64
Bit and 1 bit.

A number of additional special registers are at least logically present in register array 472. FIG.
As shown in (C), a register physically present in the register array 472 is a kernel stack pointer (ke).
renstackpointer) 568, a processor status register (PSR) 569, an old processor status register (PPSR) 570, and an array of eight temporary processor status registers (tPSR [0.7]) 571. The remaining special registers are architecture 1
00 are distributed in each place. The special address and data bus 354 is for selecting and transferring data between the special registers and the "A" and "B" register sets. Special register move instruction is “A” or “B”
This is for selecting a register from a register set, selecting a transfer direction, and specifying an address ID of a special register.

The kernel stack pointer register and the processor status register are different from other special registers. The kernel stack pointer, when in kernel state, is accessible by executing standard inter-register move instructions. The temporary processor status register cannot be accessed directly. Instead, this register array propagates the value of the processor status register and makes it available to out-of-order instructions for use by an inheritance mechanism.
used to implement the mechanism. The initial propagation value is the value of the processor status register. That is, the value obtained from the last saved instruction. This initial value is propagated forward from the temporary processor status register to allow an out-of-order instruction to access the value in the corresponding temporary processor status register. The condition code bits on which an instruction depends and which can be changed are defined by the characteristics of the instruction. That the instruction is not constrained by a dependency, register or condition code, the register dependency checker unit 494
Are determined by the carry dependency checker 492, the instructions can be executed out of order. Changes in the condition code bits of the processor status register are indicated in the logically corresponding temporary processor status register.
In particular, only bits that may change are applied to the value in the temporary processor status register and propagated to all higher order temporary processor status registers. As a result, all instructions executed out of order will have
It is executed from the processor state register value appropriately changed by the SR change instruction. When an instruction is evacuated,
Only the corresponding temporary processor status register value is transferred to PSR register 569.

The other special registers are described in [Table 2].

Table 2 Special Registers Special Move Register R / W Description PC R Program Counter: Generally, the PC stores the next address of the currently executing program instruction stream. IF_PC R / W IFU program counter: IF The PC stores the exact next execution address. PFnPC R Prefetch Program Counters: MBUF, TBUF, and EBUFPFnPC store the next prefetch instruction address of each prefetch instruction stream. uPC R / W Micro program counter: Stores the address of the instruction following the procedure instruction. This is the address of the first instruction to be executed when the procedure instruction returns. xPC R / W Interrupt / Exception Program Counter: Stores interrupt or exception (or both) return addresses. The return address is the address of IF_PC at the time of occurrence of the trap. TBR W Trap Base Address: The base address of the vector table used when dispatching to the trap handling routine. Each entry is one word long. The trap number provided by the interrupt logic unit 363 is used as an index to the table pointed to by this address. FTB W fast trap base register: base register for immediate trap processing routine table. Each table entry is 32 words and is used to directly execute a trap handling routine. The value obtained by multiplying the trap number given by the interrupt logic unit 363 by 32 is used as an offset to the table pointed to by this address. PBR W Procedure Base Register: Base address of the vector table used when dispatching to the procedure routine. Each entry is one word long and is aligned on a four word boundary. The procedure number given as the procedure instruction field is used as an index to the table pointed to by this address. PSR R / W Processor status register: Stores the processor status word. Status data bits include carry, overflow, zero, negative, processor mode, current interrupt level, running procedure routine, divide by zero, overflow exception, hardware function interrupt enabled, procedure interrupt enabled, and interrupt enabled. And so on. PPSR R / W Old Processor Status Register: Loaded from PSR when an instruction completes successfully or an interrupt or trap is triggered. CSR R / W State Compare (Boolean) Register: A set of Boolean registers accessible as a single word. PCSR R / W Old State Compare Register: Loaded from CSR when an instruction completes successfully or an interrupt or trap is triggered.

2) Details of the Integer Data Path The integer data path of the IEU 104 constructed in accordance with the preferred embodiment of the present invention is shown in FIG. For convenience of explanation, a number of control paths connected to the integer data path 580 are not shown. These connection relationships are as described with reference to FIG.

The input data on data path 580 is aligned with alignment units 582, 584 and integer load / store
Obtained from unit 586. Integer immediate (integer
The limited data value is initially provided as an instruction embedded data field and is obtained from the operand unit 470 via bus 588. Alignment unit 582 isolates the integer data value and the resulting value is sent to multiplexer 592 via output bus 590. Another input to multiplexer 592 is a special register address and data bus 354.
It is.

The immediate value (imm
edit) operands are also obtained from operand unit 570 via data bus 594. These values are right justified again by the alignment unit 584 before being sent out on the output bus 596.

[0212] The integer load / store unit 586 interacts with the CCU 106 via the external data bus 598 in both directions. Inbound data to IEU 104 is transferred from integer load / store unit 586 via input data bus 600 to input latch 602. The output data from multiplexer 592 and latch 602 is provided on multiplexer input buses 604,606 of multiplexer 608. Data from the functional unit output bus 482 'is also sent to the multiplexer 608. The multiplexer 608 has the architecture 10
In the preferred embodiment, there are two paths to send data to the output multiplexer bus 610 simultaneously. Further, the data transfer through multiplexer 608 can be completed within each half cycle of the system clock. Most instructions implemented in the present architecture 100 utilize one destination register, so up to four instructions can send data to the temporary buffer 612 during each system clock cycle.

Data from the temporary buffer 612 can be transferred to the integer register file array 614 via the temporary register output bus 616 or to the output multiplexer 620 via the alternative temporary buffer register bus 618. Integer register array output bus 622
Can transfer integer register data to multiplexer 620. Output buses connected to the temporary buffer 612 and the integer register file array 614 each allow the simultaneous output of five register values. That is, two instructions referring to a total of up to five source registers can be issued simultaneously. Temporary buffer 612, register file array 614, and multiplexer 620 enable the transfer of outbound register data to occur every half system clock cycle. Thus, up to four integer and floating point instructions can be issued during each clock cycle.

Multiplexer 620 is an outbound
It serves to select register data values directly from the register file array 614 or from the temporary buffer 612. This allows the IEU 104 to execute out-of-order execution instructions that depend on previously executed out-of-order instructions. This maximizes the execution throughput capability of the IEU integer data path by executing pending instructions out-of-order, while accurately resolving out-of-order data results from data results obtained from executed and evacuated instructions. The two goals of separation can be easily achieved. When an interrupt or other exceptional condition occurs that requires the correct state of the machine to be restored, the present invention allows the data values present in temporary buffer 612 to be easily cleared. Thus, the register file array 614 has completed prior to the occurrence of the interrupt or other exceptional condition, and remains accurately populated with data values obtained only by execution of the saved instruction.

During each half-system cycle operation of multiplexer 620, up to five selected register data values are sent to integer bypass unit 626 via multiplexer output bus 624. The bypass unit 626 basically consists of a parallel arrangement of multiplexers, which can send data appearing at any of its inputs to any of its outputs. The input of the bypass unit 626 is
2 to special register addressing data value or immediate integer value via output bus 604; up to five register data values sent out on bus 624; double integer bus 600 from integer load / store unit 586.
, The immediate operand value obtained from the alignment unit 584 via its output bus 596, and finally the functional unit output bus 482
From the bypass data path. This bypass path and data bus 482 are connected to the system clock
Four register values can be transferred simultaneously in each cycle.

Data is output from the bypass unit 626 onto an integer bypass bus 628 connected to the floating point data bus for two operands having the ability to transfer up to five register data values simultaneously. A data bus and a store data bus 6 used to send data to the integer load / store unit 586.
32.

The functional unit distribution bus 480 is implemented through the operation of the router unit 634. Router unit 634 is also implemented by a parallel multiplexer arrangement that allows the five register values received from its input to be sent to functional units provided in the integer data path. Specifically, the router unit 634 sends the bus 63 from the bypass unit 626 to the bus 63.
5 register data values sent via 0,
Current IF sent via address bus 352
The PC address value, determined by the PC control unit 362, receives the control flow offset value sent on line 378 '. The router unit 634 transmits the operand data value extracted from the bypass unit provided in the floating-point data path to the data bus 6.
It is also possible to receive the data via an optional (optional).

The register data values received by the router unit 634 are transferred over the special register address and data bus 354 to the functional unit 6
40, 642, 644. In particular, router unit 634 has the ability to send up to three register operand values to each of functional units 640, 642, 644 via router output buses 646, 648, 650. According to the general architecture of the present architecture 100, up to two instructions can be issued to functional units 640, 642, 644 simultaneously. According to a preferred embodiment of the present invention, the three dedicated integer functional units can each have a programmable shift function and two arithmetic logic unit functions.

The ALU0 function unit 644, ALU1 function unit 642 and shifter function unit 640 transfer their output register data to the function unit bus 4
Send on 82I. ALU0 and shifter function unit 6
Output data from 44, 640 is also provided on a shared integer functional unit bus 650 connected to the floating point data path. A similar floating point functional unit output value data bus 652 is provided from the floating point data path to functional unit output bus 482 '.

ALU0 functional unit 644 is IFU10
It is also used when generating virtual address values to support both prefetch operations of 2 and data operations of the integer load / store unit 586. The virtual address value calculated by ALU0 functional unit 644 is I
FU102 target address bus 346 and CC
It is sent out on the output bus 654 connected to both of the U106, and the physical address of the execution unit (EXPADDR)
Is obtained. The latch 656 is connected to the ALU0 functional unit 6
44 to store the virtualized portion of the address generated by 44. This virtualized portion of the address is sent out on output bus 658 and sent to VMU 108.

3) Details of the floating point data path FIG. 11 shows the floating point data path. The initial data is again the immediate integer operand
Received from multiple sources, including bus 588, immediate operand bus 594, and special register address data bus 354. The ultimate source of external data is a floating point load / store unit 622 connected to CCU 106 via external data bus 598.

[0222] The immediate integer operand is received by the alignment unit 664, which serves to right justify the integer data field before passing to the multiplexer 666 via the alignment output data bus 668. Multiplexer 666 also receives special register address data bus 354. The immediate operand is sent to second alignment unit 670, right justified, and sent out on output bus 672. Inbound data (inbou) from floating point load / store unit 662
nd data) is received by the latch 674 from the load data bus 676. Multiplexer 66
6, latch 674 and data from functional unit data return bus 482 "
Is received from the input. Multiplexer 678 has a selectable data path and allows two register data values to be written to temporary buffer 680 via multiplexer output bus 682 every half cycle of the system clock. The temporary buffer 680 is shown in FIG.
It has the same register set as the temporary buffer 552 'shown in FIG. Temporary buffer 680 also reads up to five register data values from temporary buffer 680 and outputs via floating-point register file array 684 via data bus 686 and output data bus 690. To the multiplexer 688. Multiplexer 688 provides a data
Floating point file array 684 via bus 692
And up to five register data values are also received at the same time. Multiplexer 688 has up to five registers
It serves to select data values and simultaneously transfer them to bypass unit 694 via data bus 696.
The bypass unit 694 is connected to the alignment unit via the data bus 672, the output data bus 698 from the multiplexer 666, the load data bus 676, and the bypass extension of the functional unit data return bus 482 ″. It also receives the immediate operand value provided from 670. Bypass unit 694 simultaneously selects up to five register operand data values and provides them to bypass unit output bus 700 and floating point load / store unit 662. It serves to output on the connected store data bus 702 and the floating point bypass bus 636 connected to the router unit 634 of the integer data path 580.

The floating point router unit 704 includes a bypass unit output bus 700, an integer data path bypass bus 628, and respective functional units 712,7.
14, 716 connected to the functional unit input bus 70
6, 708, and 710. Each of the input buses 706, 708, 710 according to the preferred embodiment of the architecture 100 includes:
Up to three register operand data values can be transferred simultaneously to each of the functional units 712, 714, 716. These functional units 712, 7
14, 716 are coupled to the functional unit data return bus 482 "for returning data to the register file input multiplexer 678. The integer data path functional unit output bus 650 is connected to the functional unit data return bus 482". It may be provided for connection to the data return bus 482 ". According to the architecture 100 of the present invention, the multiplexer function unit 71
2 and the functional unit output bus of the floating point ALU 714 can be connected to the functional unit data return bus 482 "of the integer data path 500 via the floating point data path functional unit bus 652".

4) Boolean Register Data Path Details The Boolean operation data path 720 is shown in FIG.
This data path 720 is basically used to support the execution of two types of instructions. The first type is an operand compare instruction, which uses an integer register
Set and floating-point register set,
Alternatively, two operands, provided as immediate operands, are compared by subtracting the integer and floating point data paths in one of the ALU functional units. This comparison is made between ALU functional units 642, 644, 714, 7
The subtraction by any of sixteen results in the sign and zero status bits being sent to the input selector and comparison operator combining unit 722. When the unit 722 receives an instruction designating a control signal from the E-decode unit 490, the ALU function unit 642, 644, 71
4, the output of 716 is selected, the sign and the zero bit are combined, and the Boolean comparison result value is extracted. Output bus 723
, The result of the comparison operation can be transferred to the input multiplexer 726 and the bypass unit 742 at the same time. As with the integer and floating point data paths, the bypass unit 742 is implemented as a parallel multiplexer array, which allows multiple data paths between the inputs of the bypass unit 742 to connect to multiple outputs. . Another input of the bypass unit 742 is a Boolean operation result return data bus 724 and a data bus 7.
44 consists of two Boolean operands. The bypass unit 742 converts the Boolean operands representing up to two concurrently executing Boolean instructions to the Boolean operation unit 7 via the operand bus 748.
46. Also, the bypass unit 746 has up to two single-bit Boolean
Operand bits (CF0, CF1) can be transferred simultaneously via control flow result control lines 750, 752.

The remainder of the Boolean data path includes an input multiplexer 726 that receives as input its comparison and Boolean result values output on comparison result bus 723 and Boolean result bus 724. This bus 7
24 can transfer up to two Boolean result bits to multiplexer 726 simultaneously. Further, up to two comparison result bits can be transferred to the multiplexer 726 via the bus 723. Multiplexer 726 is an optional 2x that appears at the input of the multiplexer.
Via the output of the multiplexer
Each half cycle of the system clock can be transferred to a Boolean temporary buffer 728. The temporary buffer 728 differs from FIG. 6 except that two important points are different.
This is logically the same as the temporary buffer 752 'shown in FIG. The first difference is that each register entry in temporary buffer 728 consists of a single bit. The second difference is that only one register is provided for each of the eight pending instruction slots. This is because the entire result of a Boolean operation is defined by one result bit by definition.

The temporary buffer 728 simultaneously outputs up to four output operand values. This allows two Boolean instructions each requiring access to two source registers to be executed simultaneously. The four Boolean register values are sent out on operand bus 736 every half cycle of the system clock, and are output to Boolean register file array 73 to multiplexer 738 or via Boolean operand data bus 734.
2 can be forwarded. The Boolean register file array 732 contains one 3's, as logically shown in FIG.
A 2-bit wide data register that stores up to four single bit locations in any combination.
Corrected by the data from the temporary buffer 728, the system
Each half cycle of the clock can be read from the Boolean register file array 732 and output on the output bus 740. Multiplexer 738 is connected to bus 73
Any pair of Boolean operands received from its output via 6, 740 is sent out on operand output bus 744 for transfer to bypass unit 742.

The Boolean operation function unit 746 has a function of performing a wide range of Boolean operations on two source values. In the case of a compare instruction, the source value is a pair of operands from either the integer and floating point register set and any immediate operand sent to the IEU 104; Any two. [Table 3] and [Table 4]
4 illustrates a logical comparison operation in a preferred embodiment of the architecture 100 of the present invention. Table 5 illustrates direct Boolean operations in the preferred embodiment of the architecture 100 of the present invention. The instruction condition codes and function codes shown in [Table 2]-[Table 5] represent the corresponding instruction segments. The instruction also specifies a pair of source operand registers and a destination Boolean register for storing the corresponding Boolean result.

[Table 3] Comparison of Integer Instruction Condition * Symbol Condition Code rs1 is greater than rs2> 0000 rs1 is greater than rs2 ≧≧ 0001 equal rs1 is smaller than rs2 <0010 rs1 is smaller than rs2 ≦≦ 0011 rs1 is equal to Not equal to rg2! = 0100 rs1 is equal to rs2 == 0101 Reserved 0110 unconditional 1111 * rs = register source [Table 4] Floating point comparison Instruction Condition Symbol Condition code rs1 is greater than rs2> 0000 rs1 is greater than or equal to rs2 ≧ 0001 rs1 is smaller than rs2 <0010 rs1 is smaller than or equal to rs2 ≦ 0011 rs1 is not equal to rs2! = 0100 rs1 is equal to rs2 == 0101 unordered? 1000 Unordered or rs1 greater than rs2? > 1001 unordered, is rs1 greater than rs2? ≧ 1010 equal unordered or rs1 less than rs2? <1011 Unordered, is rs1 smaller than rs2? ≦ 1100 equal unordered or rs1 equals rs2? = 1101 Preliminary 1110-1111 Table 5] Boolean instruction operations * Symbol Conditions Code 0 Zero 0000 bs1 & bs2 AND 0001 bs1 & -bs2 ANN2 0010 bs1 bs1 0011 -bs1 & bs2 ANN1 0100 bs2 bs2 0101 bs1 bs2 XOR 0110 bs1 bs2 OR 0111 -bs1 & - bs2 NOR 1000 -bs1 bs2 XNOR 1001 -bs2 NOT2 1010 bs1 -bs2 ORN2 1011 -bs1 NOT1 1100 -bs1 bs2 ORN1 1101 -bs1 -bs2 NAND register 1101 * 1 ONE * 1 Boolean

B) Load / Store Control Unit FIG. 13 shows an example of the load / store unit 760. Although shown separately in data paths 580, 660, load / store units 586, 662 are preferably implemented as one shared load / store unit 760. Each data path 580, 66
Interfaces from address 0 include address bus 762 and load and store data bus 764 (600, 67).
6), 766 (632, 702).

The addresses used by load / store unit 760 are the IFU 102 and IEU 10
4, as opposed to the virtual addresses used in the rest of
It is a physical address. IFU 102 operates at virtual addresses and generates physical addresses depending on coordination between CCU 106 and VMU 108, whereas IEU 104 requires load / store unit 760 to operate directly in physical address mode. This requirement is necessary if there are instructions that are executed out of order, causing physical address data and store operations to overlap, and load / load from CCU 106.
This is to maintain data integrity when there is an out-of-order data return to the store unit 760. Load / store unit 7 to maintain data integrity
60 stores the data obtained from the store instruction in a buffer until the store instruction is saved by the IEU 104. As a result, only one store data stored in the buffer by the load / store unit 760 can exist in the load / store unit 760. The execution of a load instruction that refers to the same physical address as the executed but not saved store instruction is delayed until the store instruction is actually saved. At that point, the store data is loaded from the load / store unit 760 to the CCU 10
6 and can be immediately loaded back by performing a CCU data load operation.

Specifically, the entire physical address is VMU1
08 on the load / store address bus 762. The load address is generally
Stored in address register 768 _0-3 . Store address is latched into store address registers 770 _3-0. The load / store control unit 774 operates in response to the control signal received from the instruction issuing unit 498, and adjusts the latch of the load address and the store address into the registers 768 _3-0 and 770 _3-0 .
The load / store control unit 774 sends a control signal for latching a load address on a control line 778, and sends a control signal for latching a store address on a control line 780. Store data is latched at the same time that the store address is latched into the logically corresponding slot of the store data register set 782 _3-0 . The 4x4x32 bit width address comparison unit 772 includes load and store address
Each of the addresses in the registers 7683 _3-0 and 770 _3-0 is input simultaneously. The execution of a full matrix address comparison during each half cycle of the system clock is controlled by load / store control unit 774 via control line 776. The presence and logical location of the load address that matches the store address is
It is sent to the load / store control unit 774 via the control line 776.

If a load address is provided by the VMU 108 and there are no pending stores, the load address is bypassed directly from the bus 762 to the address selector 786 at the beginning of the CCU load operation. However, if store data is pending, the load address is latched into the available load address latches 768 _0-3 . Corresponding store
Upon receiving a control signal from the save control unit 500 that the data instruction is saved, the load / store control unit 774 starts the CCU data transfer operation, and
Arbitrate access to CCU 106 through 84.
When the CCU 106 signals ready, the load / store control unit 774 instructs the selector 786 to send the CCU physical address on the CCUPADDR address bus 788. This address can be obtained from the store register 770 _3-0 corresponding via the address bus 790. Data from the corresponding store data register 782 _3-0 is transferred to the CCU data bus 7
92.

When a load instruction is issued from instruction issue unit 498, load / store control unit 774 allows one of load address latches 768 _3-0 to latch the requested load address. The particular latch 768 _0-3 selected logically corresponds to the location of the load instruction in the relevant instruction set. Instruction issue unit 498 passes to load / store control unit 774 a 5-bit vector indicating a load instruction in either of the two potentially pending instruction sets. If comparator 772 does not indicate a matching store address, the load address is sent to selector 786 via address bus 794 and output on CCU PADDR address bus 788. The provision of the address is performed according to a CCU request and a ready control signal exchanged between the load / store control unit 774 and the CCU 106. An execution ID value (ExID value) is also prepared by the load / store control unit 774 and issued to the CCU 106 to identify the load request when the CCU 106 subsequently returns request data containing the ExID value. This ID value consists of a 4-bit vector, and each load address latch 768 _0-3 that issued the current load request.
Is specified by a unique bit. The fifth bit is used to identify the instruction set containing the load instruction. This ID value is therefore the same as the bit vector sent with the load request from the instruction issue unit 498.

When the CCU 106 notifies the load / store control unit 774 that the preceding requested load data is available, the load / store control unit 774 receives the data from the alignment unit and loads it. -Allow sending on data bus 764. Alignment unit 798 serves to right justify the load data.

At the same time that the data is returned from the CCU 106, the load / store control unit 774
6 receives the ExID value. On the other hand, the load / store control unit 774 stores the load data in the load data
A control signal is sent to the instruction issuing unit 498 indicating that the load data is to be sent out on the bus 764, and further, a bit vector indicating which load instruction is to return the load data is returned.

C) Details of the IEU Control Path Referring to FIG. 5 again, the operation of the IEU control path will be described with reference to the timing chart shown in FIG. The execution timing of the instruction shown in FIG. 14 is an example of the operation of the present invention, and it is needless to say that the execution timing can be changed to various modes.

The timing diagram of FIG. 14 shows the sequence of the processor system clock cycle _P0-6 . Each processor cycle is an internal T cycle T. start from. Architecture 1 according to preferred embodiment of the present invention
At 00, each processor cycle consists of two T cycles.

In processor cycle 0, IFU
102 and VMU 108 operate to generate physical addresses. This physical address is sent to the CCU 106,
An instruction cache access operation is initiated. The requested instruction set is the instruction cache 132
, The instruction set is returned to the IFU 102 approximately halfway through processor cycle 1. After that, IFU10
2 is a prefetch unit 260 and an IFIFO 264
, And the transferred instruction set is first passed to the IEU 104 for execution.

1) Details of the E Decode Unit The E decode unit 490 receives the entire instruction set in parallel and decodes it before processor cycle 1 is completed. The E-decode unit 490 is implemented in the preferred architecture 100 as a logic block based on permutation combination theory with the ability to directly decode all valid instructions received via the bus 124 in parallel. The instructions recognized by the architecture 100 are listed in Table 6 for each type, along with instructions, register requirements and required resource specifications.

[Table 6] Instruction / Specification Instruction Control and operand information * Move between registers Logical / arithmetic operation function code: Addition, subtraction, multiplication, shift and other designations.

Destination register Set only PSR Source register 1 Source register 2 or immediate constant value Select register set A / B Select immediate to register destination register Move immediate integer or floating-point constant value Select register set A / B Load / Store • Register operation function code: Load or store specification, immediate, base and immediate, or use of base and offset Source / destination register Base register Index register or immediate constant value Register set A / B selection Immediate call Signed immediate Displacement control flow Operation function code: Specification of branch type and trigger condition Base register Index register, immediate constant displacement value, or trap number Register set A / B selection Special register move e Operation function code: Specification of transfer to / from special / integer register Special register / address identifier Source / destination register Register set A / B selection Integer conversion move Operation function code: Specification of conversion type from floating point to integer Source / destination register Register set A / B selection Boolean function Boolean function code: Specification of AND, OR, etc. Destination Boolean register Source register 1 Source register 2 Register set A / B selection Extended procedure Broker specifier: Procedure Specifying the address offset from the base value Operation: Pass the value to the procedure routine Atomic procedure Procedure specifier: Specifying the address value *-The instruction is decoded and identifies the instruction. These fields are included.

E decode unit 490 decodes each instruction in the instruction set in parallel. The resulting instruction identification, instruction function, register references and functional requirements are available from the output of E-decode unit 490. This information is regenerated and latched by the E decode unit 490 during each half cycle of the processor cycle until all instructions in the instruction set have been evacuated. Therefore,
The information on all eight pending instructions is
It is continuously obtained from the output of the unit 490. This information is represented in the form of an 8-element bit vector, with the bits or subfields of each vector logically corresponding to the physical location of the corresponding instruction in the two pending instruction sets. Thus, eight vectors are sent to carry checker 492 via control line 502. In this case, each vector specifies whether the corresponding instruction affects or depends on the carry bit of the processor status word. Eight vectors are sent via control line 510 to indicate the specific content and functional unit requirements of each instruction. Eight vectors are sent via control line 506, specifying the register references used by each of the eight pending instructions. These vectors are sent before the end of processor cycle 1.

2) Carry Checker Unit Details Carry checker unit 492 operates in parallel with dependency check unit 494 during the data dependency phase of the operation shown in FIG. carry·
The checker unit 492 includes the preferred architecture 100
Is implemented as logic based on permutation combination theory. Thus, at each iteration of the operation by carry checker unit 492, all eight instructions are considered as to whether the instruction has changed the carry flag in the processor status register. This is required because the carry and
This is to allow instructions that depend on the status of the bits to be executed out of order. The control signal transmitted on the control line 504 causes the carry-checker unit 49
2 can identify a particular instruction that depends on the execution of the preceding instruction on the carry flag.

Further, carry checker unit 4
92 has a temporary copy of the carry bit for each of the eight pending instructions. For instructions that have not changed the carry bit, carry checker unit 492 passes the carry bit to the next instruction in the order of the program instruction stream. Thus, it is possible to cause an instruction that is executed out of order to change the carry bit to be executed, and that subsequent instructions that depend on the instruction being executed out of order also execute instructions that change the carry bit. It can be executed even if it is placed after. In addition, because the carry bit is maintained by carry checker unit 492, the carry checker unit only needs to clear the internal temporary carry bit register when an exception occurs before these instructions are saved. The good news is that it is easy to run out of order. As a result, the processor status register is unaffected by the execution of instructions executed out of order. The temporary carry bit register maintained by carry checker unit 492 is updated as each instruction executed out of order is completed. When an instruction executed out of order is saved, the carry bit corresponding to the last saved instruction in the program instruction stream is transferred to the carry bit location of the processor status register.

3) Details of the data dependency checker unit The data dependency checker unit 494 receives eight register reference identification vectors from the E decode unit 490 via the control line 506. Each register reference identifies a 5-bit value suitable for identifying one of the 32 registers at a time, and a register bank located within an "A", "B", or Boolean register set. Is indicated by a two-bit value. The floating point register set is also called "B" register set.
Each instruction can have up to three register reference fields. Two source register fields and one destination register field. Even though certain instructions, particularly inter-register move instructions, may specify a destination register, the instruction bit field recognized by E-decode unit 490 has no output data actually created. May mean. Rather, execution of the instruction is only intended to determine a change in the value of the processor status register.

The data dependency checker 494 is also a pure combinational logic (p
urecombinatorial logic, which simultaneously determines the dependencies between the source register reference of an instruction appearing later in the program instruction stream and the destination register reference of an earlier instruction. Works. The bit array is created by a data dependency checker 494 that identifies not only which instructions depend on other instructions, but also on which register each dependency originated.

The dependencies between carry and register data are determined immediately after the start of the second processor cycle.

4) Details of Register Renaming Unit The register renaming unit 496 receives the IDs of the register references of all eight pending instructions via the control line 506 and the register dependencies via the control line 508. Matrices from the eight elements are also received via control line 542. These elements indicate which instruction in the current set of pending instructions has been executed (completed). From this information, the register rename unit 496 sends an eight element array of control signals to the instruction issuing unit 498 via the control line 512. The control information sent in this manner provides a register renaming unit 496 that indicates which of the currently pending instructions that have not been executed can be executed when the data dependency of the current set is determined. Reflects the decisions made. Register renaming unit 496 receives via line 516 a select control signal identifying up to six instructions issued simultaneously for execution. That is, two integer instructions, two floating point instructions and two Boolean instructions.

The register renaming unit 496 is connected to the bus 518.
Through the control signal sent to the register file array 472 via the... To select the source register to be accessed when executing the identified instruction. The out-of-order executed instruction destination registers are stored in the corresponding data path temporary buffers 612, 68.
0,728. Instructions executed in sequence are saved upon completion, and the resulting data is stored in register files 614, 684, 732. The choice of source register depends on whether the register was previously selected as the destination and the corresponding previous instruction has not yet been saved. In such a case, the source register is selected from the corresponding temporary buffer 612, 680, 728. If the previous instruction was saved, the corresponding register file 6
14, 684 and 732 registers are selected. As a result, register rename unit 496 operates to effectively replace references to register file registers with references to temporary buffer registers in the case of instructions executed out of order.

According to the architecture 100, the temporary buffers 612, 680, 728 do not overlap with the register structure of the corresponding register file array. Rather, 8
One destination register slot is provided for each of the pending instructions. As a result, the replacement of the temporary buffer destination register reference is determined by the location of the corresponding instruction in the pending register set. Subsequent source register references are identified by the data dependency checker 494 for the instruction in which the source dependency occurred. Accordingly, the destination slot in the temporary buffer register can be easily determined by the register renaming unit 496.

5) Details of Instruction Issuing Unit The instruction issuing unit 498 determines the set of instructions that can be issued based on the output of the register rename unit 496 and the functional requirements of the instruction identified by the E decode unit 490. The instruction issuing unit 498 controls the control line 514.
This determination is made based on the status of each of the functional units 478 _0-n reported via. Accordingly, instruction issuance unit 498 begins operation upon receiving a usable instruction set to be issued from register renaming unit 496. Assuming that access to the register file is required to execute each instruction, instruction issuance unit 498 causes functional units 498 _0-n that are currently executing the instruction to execute.
Expect to be usable. In order to minimize a delay in determining an instruction to be issued to the register renaming unit 496, the instruction issuing unit 498 is realized by a dedicated combination logic.

Upon determining the instruction to be issued, register rename unit 496 begins accessing the register file, which access is in the third processor cycle P ₂
Is continued until it ends. Processor cycle P ₃
Is started, the instruction issuing unit 498 outputs “Exec”
The operation by one or more functional units 478 _0-n is started, as indicated by “ute 0”, and the source data sent from the register file array 472 is received and processed.

Typically, most instructions processed in architecture 100 are executed through functional units in one processor cycle. However, some instructions
As shown by "Execute 1", multiple processor cycles are required to complete a simultaneously issued instruction. The Execute 0 instruction and the Execute 1 instruction can be executed by, for example, the ALU and the floating-point multiplication function unit, respectively. ALU functional unit, as shown in FIG. 14, 1 generates output data at the processor cycle, the output data just previously latched when executing another instruction during the fifth processor cycle P ₄ Can be used for Preferably, the floating point multiplication function unit is an internal pipelined function unit. Thus, another floating point instruction can be issued in the next processor cycle. However, the result of the first instruction is not available for a data-dependent number of processor cycles. The instruction shown in FIG. 14 requires three processor cycles to complete processing in a functional unit.

During each processor cycle, the function of instruction issue unit 498 is repeated. As a result, the current pending instruction set status and functional units 478 _0-n
Are reevaluated during each processor cycle. Thus, under optimal conditions, the preferred architecture 100 may have up to six per processor cycle.
Up to instructions can be executed. However, the total average number of executed instructions from a typical instruction mix is between 1.5 and 2.0 per processor cycle.

The last consideration in the function of the instruction issuing unit 498 is that it is involved in processing trap conditions and executing specific instructions. In order to generate a trap condition, it is necessary to clear from the IEU 104 all instructions that have not been saved yet. Such a situation may occur when the functional unit 478 responds to the arithmetic error.
_An external interrupt was received from E-decode unit 490 from either _0-n or, for example, when an illegal instruction was decoded, which was relayed to IEU 104 via interrupt request / acknowledgement control line 340. May happen in response to When a trap condition occurs, instruction issue unit 498 is responsible for aborting or invalidating all non-evacuated instructions currently pending in IEU 104. All instructions that cannot be saved at the same time are invalidated. This result is essential for accurately generating interrupts over conventional schemes of executing the program instruction stream in order. When the IEU 104 is ready to begin execution of the trap processing program routine, the instruction issuing unit 498 acknowledges receipt of the interrupt by a return control signal via control line 340. Also, in order to prevent the possibility that an exception condition for an instruction will be recognized based on the changed processor state bits before the execution of the instruction in a conventional purely in-order routine, the instruction issue unit 498 will PS
Responsible for ensuring that all instructions that can change R (such as special moves and returns from traps) are executed in strict order.

Certain instructions that alter the flow of program control are not identified by I-decode unit 262. Such instructions include subroutine return, procedure instruction return, and trap return. The instruction issuing unit 498 outputs the discrimination control signal to I
IFU 102 via EU return control line 350
Send to The corresponding one of the special registers 412 is selected, and outputs the IF_PC execution address existing at the time of execution of the call instruction, occurrence of the trap, or appearance of the procedure instruction.

6) Details of Completion Control Unit Completion control unit 540 monitors functional units 478 _0-n to check the completion status of the current operation.
In the preferred architecture 100, the completion control unit 54
0 predicts the completion of the operation by each functional unit, and sets the completion vector indicating the execution status of each instruction in the currently pending instruction set to about half the completion of the instruction execution by the functional units 478 _0-n. Register Renaming Unit 496, Bypass Control Unit 5 Before Processor Cycle
20 and the evacuation control unit 500. As a result, the instruction issuing unit 498 causes the register renaming unit 4
Through 96, functional units that complete execution can be considered as available resources for the next instruction issue cycle. The bypass control unit 520 converts the data output from the functional unit into a bypass unit 474.
Preparations can be made to bypass it. Finally, the evacuation control unit 500 includes the function unit 478.
At the same time as transferring data from _0-n to the register file array 472, the corresponding instruction is saved.

7) Details of the Evacuation Control Unit In addition to the instruction completion vector sent from the completion control unit 540, the evacuation control unit 500 monitors the oldest instruction set output from the E decode unit 490. When each instruction in the instruction stream order is marked complete by the completion control unit 540, the evacuation control unit 500 causes the temporary buffer slot to register from the temporary buffer slot via a control signal sent on the control line 534. The corresponding instruction in file array 472 directs the transfer of data to the specified file register location. When one or more instructions are saved at the same time, a PC Inc / Size control signal is sent out on control line 344. Up to four instructions can be saved in each processor cycle. When the entire instruction set has been retired, an IFIFO read control signal is sent out on control line 342 to
264 is advanced.

8) Control Flow Control Unit Details The control flow control unit 528 provides information specifying whether the control flow instructions in the current pending instruction set have been resolved, and whether the resulting branch has taken place. It operates to constantly supply the IFU 102. The control flow control unit 528 includes the E decode unit 4
The identification information of the control flow branch instruction by 90 is obtained via the control line 510. The current set of register dependencies is sent from the data dependency checker unit 494 to the control flow control unit 528 via the control line 536, so that the control flow control unit 528 ties the result of the branch instruction to the dependency. Can be determined whether it is known or known. Register rename unit 496 to bus 5
Register references sent via 18 are monitored by control flow control unit 528 to determine the Boolean registers that define branch decisions. Therefore, the branch decision can be determined even before execution of the out-of-order control flow instruction.

Simultaneously with the execution of the control flow instruction, the bypass unit 472 transmits the result of the control flow to the control flow control unit 52 via the control line 530 including the control lines 750 and 752 of the control flow 1 and the control flow 2.
8 is sent. Finally, the control flow control unit 528 continuously sends two vectors, each of 8 bits, to the IFU 102 via the control line 348.
These vectors define whether the instruction located at the logical location corresponding to the bit in the vector has been resolved, and whether a branch has taken place as a result.

In the preferred architecture 100, the control flow control unit 528 is implemented as a combinational logic that operates continuously upon receiving input control signals to the control unit 528.

9) Details of the bypass control unit The instruction issuing unit 498 includes the bypass control unit 520.
In close cooperation with the control of the routing of data between the register file array 472 and the functional units 4780 _-n . The bypass control unit 520 is configured as shown in FIG.
4 operates in conjunction with the register file access, output and store phases of the operation shown in FIG.
During a register file access, the bypass control unit 520 causes the register file array 472 to be written during the output phase of execution of the instruction.
The access of the destination register within can be recognized through control line 522. In this case, the bypass control unit 520 bypasses the functional unit distribution bus 4
Instructing to select the data sent on functional unit output bus 482 to return to 80. bypass·
Control over unit 520 is provided by instruction issuing unit 498 via control line 542.

IV. The interface definition of the virtual memory control unit VMU 108 is shown in FIG. The VMU 108 mainly includes a VMU control logic unit 800 and a content address (content address).
ssable) memory (CAM) 802. The general function of the VMU 108 is shown in a block diagram in FIG. In the figure, the expression of the virtual address is
Space ID (sID [31:28]), virtual page number (VADDR [27:14]), page offset (PADDR [13: 4]), and request ID (rID)
[3: 0]). The algorithm for generating the physical address uses the space ID,
1 from 16 registers in space table 842
To choose one. The contents of the selected space register and the virtual page number are combined and used as an address when accessing the table look-up buffer (TLB) 844. The 34-bit address serves as a content address tag and is used to specify the corresponding buffer register in buffer 844. If a match is found for the tag, the 18-bit wide register value is obtained as the upper 18 bits of the physical address 846. The page offset and request ID are obtained as the lower 14 bits of the physical address 846.

If no tag match is found in table index buffer 844, a VMU mismatch is reported.
In this case, it is necessary to execute a VMU fast trap processing routine employing the conventional hash algorithm 848 for accessing the complete page table data structure maintained in the MAU 112. This page table 850 contains entries for all memory pages currently being used by the architecture 100. Hash algorithm 848 determines the page table entries needed to satisfy the current virtual page translation operation. These page table entries are M
The data is loaded from the AU 112 to the trap register of the register set “A”, and then transferred to the table look-up buffer 844 by a special register move instruction. On return from the exception handling routine, the instruction that caused the VMU mismatch exception is re-executed by the IEU 104. The translation operation from virtual address to physical address should complete without raising an exception.

[0265] The VMU control logic 800
And a dual interface with the IEU 104. The preparation signal is transmitted via the control line 822 to the IEU10
4 to inform that the VMU 108 is available for address translation. In the preferred embodiment, VMU1
08 is always ready to accept a conversion request from the IFU 102. IFU 102 and IEU 104 can both submit requests via control lines 328 and 804. In the preferred architecture 100, the IFU
Can access the VMU 108 with priority.
As a result, only one busy (busy) control line 820 is output to the IEU 104.

Both IFU 102 and IEU 104
The space ID and virtual page number fields are sent to VMU control logic 800 via control lines 326 and 808, respectively. Further, the IEU 104 outputs a read / write control signal on a control line 806. This control signal defines, as necessary, whether the address should be used for a load operation or a store operation to change the memory access protection attribute of the referenced virtual memory. The space ID of the virtual address and the virtual page field are passed to the CAM unit 802, where the actual conversion operation is performed. The page offset and ExID fields will eventually be
Sent directly from the 104 to the CCU 106. The physical page and request ID fields are sent to CAM unit 802 via address line 836. When a match is found in the table look-up buffer, the VMU control logic
The unit 800 is notified. The resulting 18-bit physical address is output on address output line 824.

The VMU control logic unit 800
Upon receiving a hit and control output control signal from line 830, it outputs a virtual memory mismatch and a virtual memory exception control signal on lines 334,332. The virtual memory conversion mismatch means that the page table ID in the table index buffer 844 does not match. All other translation errors are reported as virtual memory exceptions.

Finally, the data table in the CAM unit 802 can be changed by executing a special register move instruction by the IEU 104. Read / write, register select, reset, load and clear control signals are sent from IEU 104 to control lines 810, 812, 8
14, 816, and 818. Data to be written to the CAM unit registers is received by the VMU control logic unit 800 from the IEU 104 via an address bus 808 connected to the special address data bus 354. This data is the default setting,
At the same time as the control signal for controlling the register selection and the read / write control signal, the CAM unit 80 via the bus 836
2 As a result, the data registers in the CAM unit 802 are dynamically operated by the architecture 100, including reads for stores required when processing context switches defined in higher level operating systems. Can be exported immediately if needed.

V. The control over the data interface of the cache control unit CCU 106 is shown in FIG. Again, IFU 102 and I
A separate interface is provided for EU 104. In addition, a logically separate interface is
MCU11 for command and data transfer
Connected to 0.

The IFU interface includes a physical page address sent on address line 324, a VMU translated page address sent on address line 824, and a request ID transferred separately on control lines 294 and 296. Consists of The unidirectional data transfer bus 114 is for transferring the entire instruction set in parallel with the IFU 102. Finally, the read / busy and ready control signals are sent to CCU 106 via control lines 298, 300, 302.

Similarly, the entire physical address is sent to IEU 102 via physical address bus 788. The request ExID is passed separately to and from the load / store unit of the IEU 104 via the control line 796.
The 80-bit wide unidirectional data bus is
Output to the EU 104. However, architecture 10
0, only the lower 64 bits are IEU1
Used by 04. The full 80-bit data transfer bus is made available and supported in the CCU 106 to support subsequent execution of the architecture 100 and by changing the floating point data path 660, IEEE Standard 754
Supports floating-point operations that conform to.

The IEU control interface is established through request, busy, prepare, read / write, and through control signal 784, and is substantially the same as the corresponding control signal used by IFU 102. The exception is that a read / write control signal is provided to distinguish between a load operation and a store operation. The width control signal specifies the number of bytes to be transferred when the IEU 104 accesses each CCU 106. In contrast, all accesses to the instruction cache 132 are fixed 128-bit wide data fetch operations.

The CCU 106 has almost the same cache control function as the conventional one for the instruction cache 132 and the data cache 134. Preferred Architecture 10
At 0, the instruction cache 132 is a high-speed memory having the function of storing 256 128-bit instruction sets. The data cache 134 has a function of storing 1024 32-bit words of data. Instruction requests and data requests that cannot be immediately satisfied from the contents of the instruction cache 132 and the data cache 134 are passed to the MCU 110. If the instruction cache misses, the 28-bit wide physical address is
It is passed to the MCU 110 via the bus 860. Request I
D and additional control signals for coordinating the operation of CCU 106 and MCU 110 are provided on control line 862. When the MCU 110 coordinates the required read access of the MAU 112, two consecutive 64-bit wide data transfers are made directly from the MAU 112 to the instruction cache 132. Two transfers are required because the data bus 136 is a 64-bit wide bus in the preferred architecture 100. When the requested data is returned through the MCU 110, the request ID maintained during the pending request operation is also returned to the control line 86.
2 and is returned to the CCU 106.

Data Cache 134 and MCU 110
The data transfer operation between the two is almost the same as the transfer operation of the instruction cache. Since data load and store operations can reference a single byte, the full 32-bit wide physical address is sent to MCU 110 via address bus 864. The interface control signal and the request ExID are transferred via the control line 866. The bidirectional 64-bit data transfer is performed via the data cache bus 138.

VI. SUMMARY AND CONCLUSION The high performance RISC based microprocessor architecture has been described above. The architecture of the present invention allows instructions to be executed out of order, provides separate prefetch instruction transfer paths for the main and target instruction streams, and provides procedural instruction recognition and dedicated prefetch paths.
Optimized instruction execution unit allows multiple optimized data processing paths to support integer, floating point and Boolean operations, and has a temporary register file for each Out-of-order execution and instruction cancellation can be easily performed while accurately maintaining the state of the machine state set to.

Therefore, although the above description discloses the preferred embodiment of the present invention, it is obvious that those skilled in the art can make various changes and improvements within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a simplified block diagram illustrating a microprocessor architecture of a preferred embodiment embodying the present invention.

FIG. 2 is a detailed block diagram illustrating an instruction fetch unit constructed in accordance with the present invention.

FIG. 3 is a block diagram illustrating a program counter logic unit constructed in accordance with the present invention.

FIG. 4 is another detailed block diagram illustrating program counter data and control path logic.

FIG. 5 is a simplified block diagram showing an instruction execution unit of the present invention.

FIG. 6A is a simplified block diagram illustrating the register file architecture used in the preferred embodiment of the present invention, and FIG. 6B is a temporary buffer register used in the preferred embodiment of the present invention. FIG. 3C is a diagram showing the format of a file storage register, and FIG.
FIG. 7 is a diagram showing the primary and secondary instruction sets in the last two stages of the IFO unit in graphic form.

FIG. 7 graphically illustrates a reconfigurable state of a primary integer register set provided in accordance with a preferred embodiment of the present invention.

FIG. 8 graphically illustrates a reconfigurable floating point and secondary integer register set provided in accordance with a preferred embodiment of the present invention.

FIG. 9 graphically illustrates a tertiary Boolean register set provided in a preferred embodiment of the present invention.

FIG. 10 is a detailed block diagram illustrating a primary integer processing data path portion of an instruction execution unit configured in accordance with a preferred embodiment of the present invention.

FIG. 11 is a detailed block diagram illustrating a primary floating point data path portion of an instruction execution unit constructed in accordance with a preferred embodiment of the present invention.

FIG. 12 is a detailed block diagram illustrating a Boolean operation data transmission portion of an instruction execution unit configured according to a preferred embodiment of the present invention.

FIG. 13 is a detailed block diagram illustrating a load / store unit configured in accordance with a preferred embodiment of the present invention.

FIG. 14 is a timing diagram illustrating a preferred operation sequence of a preferred embodiment of the present invention when executing instructions in accordance with the present invention.

FIG. 15 is a simplified block diagram illustrating a virtual memory control unit configured in accordance with a preferred embodiment of the present invention.

FIG. 16 graphically illustrates a virtual memory control algorithm used in a preferred embodiment of the present invention.

FIG. 17 is a simplified block diagram illustrating a cache control unit used in a preferred embodiment of the present invention.

[Explanation of symbols]

100 architecture, 102 instruction fetch unit (IFU), 104 instruction execution unit (IE)
U), 106: Cache control unit (CUU), 1
08: virtual memory unit (VMU), 112: memory array unit (MAU)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 9/46 310 G06F 9/46 310H (72) Inventor Miyayama, Yoshiyuki United States 95050 Santa Clara Rancho Macomi, California California Boulevard 2171 (72) Inventor Garc, Sanjib United States 94539 Fremont Sentinel Drive, California 46820 (72) Inventor Hagiwara, Yasaki United States 95050 Santa Clara Monroe Street, California 2250 Apartment 274 (72) Inventor One, Johannes United States 94062 Redwood City, California King Street 25 (72) Inventor Trang, Kwan H. USA 95130 San Jose, Mayfield Avenue, California 2045

Claims (11)

[Claims] 1. A trap processing method for processing traps in a microprocessor, comprising: a main buffer portion, a target buffer portion, and a procedure buffer.
Multiple prefetches with groups of buffer parts
Prefetching instructions from an instruction stream into any one of the buffers for subsequent execution by the microprocessor; and prefetching the prefetched instructions from one of the buffer portions for execution during execution time. Prior to a step of transferring to an output bus and a predetermined execution time being an execution time for a predetermined one of the prefetch instructions, the predetermined one of the instructions included any of a first class of synchronous exceptions. Detecting whether or not the instruction includes a synchronous exception, and invoking an exception handler during the predetermined execution time if the predetermined one of the instructions includes a synchronous exception. 2. The trap processing method according to claim 1, wherein said prefetching step includes a step of prefetching a plurality of instructions at a time. 3. The trap processing method according to claim 1, wherein the first class exception is a fault that occurs during the step of prefetching. 4. The method according to claim 1, further comprising the step of detecting whether said predetermined one of said instructions includes any of an execution class synchronization exception during said predetermined execution time. 2. The trap processing method according to 1. 5. The trap processing method according to claim 1, further comprising the step of executing an instruction out of order in the order in the stream. 6. The trap processing method according to claim 1, further comprising the step of executing a plurality of instructions during said execution time and during a subsequent execution time. 7. The microprocessor can execute a plurality of instructions from a series of instructions during a single execution time, and further schedules a plurality of predetermined instructions for execution during the predetermined execution time. Setting, and determining the predetermined one of the instructions as the first instruction from the order among the plurality of instructions including a synchronization exception. Item 7. The trap processing method according to Item 1. 8. The method according to claim 8, further comprising the step of detecting whether each of the plurality of instructions includes an exception of an execution class during the predetermined execution time and before the determining step. 8. The trap processing method according to claim 7, wherein: 9. The execution class exception has a second exception type that depends on a state of at least one processor status bit during the predetermined execution time, wherein the microprocessor does not follow the instruction order. Further comprising the step of scheduling all instructions capable of changing the processor state bits to execute in the same order with respect to the order of the instructions. Item 10. The trap processing method according to Item 8. 10. The execution step further includes: temporarily executing a plurality of instructions scheduled for execution, and storing a result of the temporary execution in a temporary register; Copying the result from the temporary register to a permanent register, further comprising rejecting all instructions in the predetermined plurality of instructions that precede the predetermined instruction in order.
Canceling all instructions in said predetermined plurality of instructions following said first instruction in said order. 11. The method according to claim 10, further comprising a step of canceling a first instruction in the order.
The trap processing method as described.