JP2000029698A - Super scalar processing system and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a super scalar processing system and a data processing system easily reinforcing an architecture function. SOLUTION: This system is provided with an instruction fetch unit 102 for fetching an instruction set and an execution unit 104 provided with a function for simultaneously and parallelly executing plural instructions through the parallel array of function units. The instruction fetch unit 102 holds the prescribed number of the instructions in an instruction buffer and the execution unit 104 is provided with an instruction selection unit connected to the instruction buffer for selecting the instruction to be executed and the plural function units for executing an operation specified by the instruction. The instruction selection unit is provided with an instruction scheduler connected to an instruction decoder for judging whether or not the instruction to be executed is usable, relating logic and the function unit for judging respective execution statuses respectively, for scheduling the start of processing of the instruction through the function unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the design of RISC-type microprocessor architectures, and in particular, adds functional computing elements to the architecture, including those tuned for specific computing functions. The present invention relates to a superscalar processing system and a data processing method which can be easily expanded to improve a calculation throughput.

[0002] The U.S. patent applications listed below are filed and pending at the same time as the present patent application,
The matters disclosed in these U.S. patent applications and in correspondingly filed patent applications in Japan are hereby incorporated by reference in their entirety with their application numbers. Shall be constituted. (1) Title of invention "High-Performance RISC Microprocess"
or Architecture) SMOS 7984 MCF / GBR, U.S. Patent Application No.
07 / 727,006, filed on July 8, 1991, inventor Le T. Nguye
n Others and corresponding Japanese Patent Application No. 5-502150 (Japanese Patent Application Publication No. 6-501122). (2) “RISC Microprocessor Architecture with Isolated Architectural Dependencies” (RISC Micropro
cessor Architecture with IsolatedArchitectural Dep
endencies) SMOS 7987 MCF / GBR, U.S. Patent Application No. 07/72
6,744, filed July 8, 1991, inventor Le T. Nguyen
Others and corresponding Japanese Patent Application No. 5-502152 (Japanese Patent Application Publication No. 6-502034). (3) Title of the invention "Use of multiple register sets"
RISC Microprocessor Architecture "(RISC Mi
croprocessor Architecture ImplementingMultiple Typ
ed Register Sets) SMOS 7988 MCF / GBR / RCC, U.S. Patent Application No. 07 / 726,773, filed July 8, 1991, inventor Sanjiv
Garg et al. And corresponding Japanese Patent Application No. 5-502403.
No. (Japanese Patent Publication No. Hei 6-501805). (4) Title of the invention "RISC microprocessor architecture that implements fast traps and exception states"
(RISC Microprocessor ArchitectureImplementing Fa
st Trap and Exception State) SMOS 7989 MCF / GBR / WS
W, U.S. patent application Ser. No. 07 / 726,942, filed on Jul. 8, 1991, inventor Le T. Nguyen et al. (5) Title of invention "Single Chip Page Program"
Linta Contra '' (Single Chip Page Printer Cont
roller) SMOS 7991 MCF / GBR, U.S. Patent Application No. 07 / 726,929
, Filed on July 8, 1991, inventor Derek J. Lentz et al., And corresponding Japanese Patent Application No. 5-502149 (Japanese Patent Application No.
-501586). (6) Title of the invention "Microprocessor Architecture Capable of Suppor"
ting Multiple Heterogeneous Processors) SMOS 7992
MCF / WMB, U.S. patent application Ser. No. 07 / 726,893, filed Jul. 8, 1991, inventor Derek J. Lentz et al. ).

[0003] The description in this specification is based on the description in the specification of US Patent Application No. 07 / 727,058, which is the priority of the present application. The contents of the description of the United States patent application are incorporated herein by reference.

[0004]

2. Description of the Related Art Recently, microprocessor architectures have been designed using complex instruction set computers (Compl.
ex Instruction Set Computer-Reduced Instruction Set Computer (Reduced)
It has matured by the Instruction Set Computer-RISC) architecture. A feature of the CISC architecture is that it implements an instruction execution pipeline and is largely supported in hardware. A typical prior art pipeline structure includes an instruction fetch stage, an instruction decode stage, a data load stage, an instruction execution stage and a data store stage in a certain order. Having different portions of the instruction set execute concurrently through respective stages of the pipeline results in improved performance. The longer the pipeline, the more execution stages available,
In addition, the number of instructions that can be executed concurrently increases.

[0005] There are two general problems that limit the efficiency of the CISC pipeline architecture. The first problem is that the conditional branch instruction cannot be evaluated until the preceding set condition code instruction has substantially completed execution through the pipeline. Thus, some pipeline stages remain inactive for multiple processor cycles, as subsequent execution of the conditional instruction is delayed or stalled. Typically, the condition code is written to a condition code register, also called a processor status register (PSR), only when the processing of the instruction has completed through the execution stage. Therefore, the pipeline must be stopped while the conditional branch instruction remains in the decode stage for a plurality of processor cycles until the branch condition code is determined. If the pipeline goes down, there will be a significant loss in throughput. In addition, the average throughput of a computer depends on how many times a conditional branch instruction appears closely after a set condition code instruction in the program instruction stream.

Another problem stems from the fact that instructions appearing closely in the program instruction stream tend to refer to the same register in the processor register file. Data registers are often used as the destination or source of data in the store and load stages of sequential instructions. In general, an instruction that stores data in a register file must have completed at least the execution stage before the load stage processing of the next instruction can access the register file. Since many instructions require multiple processor cycles in one execution stage to obtain store data, the entire pipeline is halted while the operation of the execution stage is sustained. Is typical. As a result, the execution throughput of a computer is substantially dependent on the internal order of the instruction stream being executed.

The third problem is not caused by the execution of the instruction itself, but by the instruction execution environment supported by the hardware of the microprocessor itself, that is, the state of the machine (s
This is a problem that arises from maintaining the tate-of-the machine). Current CISC microprocessor hardware subsystems can detect the appearance of a trap condition during the execution of an instruction. Traps include hardware interrupts, software traps, and exceptions. When each trap appears, the processor must execute the corresponding trap handling routine. When a trap is detected, the execution pipeline must be cleared to allow immediate execution of the trap handling routine.
At the same time, at the exact point at which the trap occurred, that is, when the first instruction currently executing terminated due to an interrupt and trap, and immediately before the instruction that failed due to the exception. It is necessary to set the state of the machine at that point. The machine status and
Also in this case, it is necessary to restore the executing instruction itself at the completion of the processing routine, according to the contents of the trap. As a result, the occurrence of each trap or related event creates latency by clearing the pipeline both at the beginning and end of the processing routine, and at the time of storing and returning the exact machine state, resulting in processor throughput. Will decrease accordingly.

[0008] In order to solve these problems, various attempts have been made to improve the static throughput of the CISC architecture. Assuming that the conditional branch instruction has been executed correctly, the pipeline execution can proceed tentatively before the branch condition code is finally determined. Also, by making an assumption as to whether or not the register will be changed, the subsequent instruction can be provisionally executed. Finally, the number of exceptions that interrupt (interrupt) the processing of the program instruction stream can be minimized by substantially adding hardware to minimize the occurrence of exceptions that require execution of processing routines. Can be reduced.

Clearly, these solutions further substantially complicate the hardware, but the solutions themselves have their own problems. To continue execution of the instruction before either the branch condition or the register file store access finally resolves, one of several points in the program instruction stream containing the location of the conditional branch, For each change in the register file and any exceptions,
It is necessary to be able to restore the state of the machine to a point before the execution of the last few instructions is completely finished. As a result, additional hardware is required to support this and must be specifically designed to not significantly increase the cycle time of any pipeline stage.

[0010] The RISC architecture attempts to greatly simplify the hardware realities of microprocessor architectures in order to avoid many of the problems described above. In the extreme case, each RISC instruction is executed only in three pipelined program cycles, including a load cycle, an execute cycle, and a store cycle. In the known RISC architecture,
The use of load and store data bypassing techniques allows one instruction to be executed per cycle in a three stage pipeline.

Where possible, hardware support in the RISC architecture is minimized to favor software routines to perform the required functions. As a result, the RISC architecture offers the hope that significant flexibility and speed will be gained by using a simple set of load / store instructions executed by an optimally adapted pipeline. And, in fact, the RISC architecture balances the need for shorter high-performance pipelines with the need to execute with substantially more instructions to achieve all the functions you need. Advantages have been found to be obtained.

The design of the RISC architecture is generally
Avoid or minimize problems with the CISC architecture in terms of branches, register references and exceptions. The pipeline involved in the RISC architecture is short and optimized for speed. Shortening the pipeline minimizes the consequences of a pipeline stall or clear, and minimizes the problem of restoring the state of the machine to its previous execution.

[0013] However, significantly increasing throughput performance beyond the generally recognized current levels cannot be easily achieved with known RISC architectures. As a result, various alternative architectures called a so-called super-scaler have been proposed. These architectures typically attempt to increase processor throughput proportionally by executing multiple instructions concurrently. Unfortunately, these architectures have similar, but not identical, problems with conditional branching, register references, and exception handling to the CISC architecture.

A particular problem that arises with conventional superscalar architectures is that the architecture itself is generally inherently complex, so that architectural changes cannot be made without a major redesign of the underlying architecture. That is not possible. When processing the execution of multiple instructions that are executed concurrently, there are substantial control constraints on the architecture to ensure the correct execution of the instruction stream. In fact, certain instructions may complete their execution before execution of an instruction earlier in the program instruction stream. As a result, it is often not possible to make architectural changes that affect the execution flow of a particular instruction without redesigning even the control logic that manages the basic aspects of instruction execution.

[0015]

SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a superscalar processing system and a data processing method which can easily enhance the architectural functions by adding and changing functional units for enhancing computation. It is to be.

[0016]

SUMMARY OF THE INVENTION According to the present invention, there is provided an instruction fetch unit for fetching an instruction set from an instruction store.
nit) and an execution unit (execu) with the ability to execute multiple instructions in parallel through a parallel array of functional units.
This is achieved by providing a microprocessor architecture that includes an option unit. A fetch unit typically maintains a predetermined number of instructions in an instruction buffer. The execution unit is connected to the instruction buffer and includes an instruction selection unit for selecting an instruction to be executed, and a plurality of functional units for performing a functional operation specified by the instruction.

An instruction selection unit is coupled to the instruction buffer and is each of an instruction decoder and associated logic for determining whether an instruction to be executed is available, and a functional unit for determining a respective execution status. And preferably includes an instruction scheduler for scheduling the start of processing instructions through the functional unit. The instruction scheduler schedules the instructions that are determined to be available for execution and that the instruction scheduler determines that at least one of the functional units having the required computational functions is available.

As a result, an advantage of the present invention is that the execution units can be easily modified to make the desired changes to the functions performed by any or all of the functional units. This includes changes made due to changes in functions performed by a predetermined one of the functional units, and changes resulting from the provision of additional functional units. Changing or adding functional units basically requires only that the instruction scheduler be changed accordingly, taking into account the differences in the instructions executed by each changed or added functional unit. Is done.

Another advantage of the present invention is an architecture having multiple execution data paths through execution units, where each execution data path is a type of computational function that is performed on data, ie, , Which are generally optimized for integer, floating point, and Boolean types. Yet another advantage of the present invention is that the specific characteristics of the number, type and calculation of the functional units provided in each data path and between the data paths are independent of each other. Changing the function or increasing the number of functional units in the data path has no architectural impact on other data functional units. Further, another advantage of the present invention is that
Since the instruction scheduler is an integrated unit,
Scheduling instructions for all of the functional units, regardless of the number of data paths implemented in the execution units and the number or type of functions implemented in the data path that best fits the execution of a given instruction It is.

[0020]

Embodiments of the present invention will be described below. The description will be made sequentially according to the following table of contents.

Table of Contents I. Overview of Microprocessor Architecture II. Instruction fetch unit A) IFU data path B) IFU control path C) IFU / IEU control interface D) PC logic unit details 1) PF and ExPC control / data unit details 2) PC control algorithm details E) Interrupt And exception handling 1) Overview 2) Asynchronous interrupt 3) Synchronous exception 4) Handler dispatch and return 5) Nest 6) Trap list III. Instruction execution unit A) Details of IEU data path 1) Details of register file 2) Details of integer data path 3) Details of floating point data path 4) Details of Boolean register data path B) Load / store control unit C 1) Details of the IEU control path 1) Details of the E decode unit 2) Details of the carry checker unit 3) Details of the data dependency checker unit 4) Details of the register rename unit 5) Details of the instruction issue unit 6) Complete Details of control unit 7) Details of evacuation control unit 8) Details of control flow control unit 9) Details of bypass control unit IV. Virtual memory control unit Cache control unit VI. Summary and Conclusion The following is a description according to the table of contents. I. Overview of Microprocessor Architecture FIG. 1 provides an overview of the architecture 100 of the present invention. An instruction fetch unit (IFU) 102 and an instruction execution unit (IEU) 104 are the core functional elements of the architecture 100. Virtual memory unit (VMU) 108,
A cache control unit (CUU) 106 and a memory control unit (MCU) 110 are for directly supporting the functions of the IFU 102 and the IEU 104. The memory array unit (MAU) 112 is for operating the architecture 100 as a basic element. However, MAU 112 does not exist directly as one integral component of architecture 100. That is, in the preferred embodiment of the present invention, IFU 102, IEU 104, VMU 108,
The CCU 106 and MCU 110 are implemented on a single silicon chip using a conventional 0.8-micron design rule low-power CMOS process and consist of approximately 1,200,000 transistors. Clock speed of the standard processor or system architecture 100 is 40 MH _Z. However, according to a preferred embodiment of the present invention, the internal processor clock speed is 160 MH _Z. The basic role of IFU 102 is to fetch instructions, buffer the instructions while execution by IEU104 is pending, and generally compute the next virtual address used when fetching the next instruction It is to be.

In the preferred embodiment of the invention, each instruction is of length
32-bit has been fixed. The instruction set, or “bucket” of four instructions, is transferred from the instruction cache 132 in the CCU 106 to a 128-bit wide instruction bus 114.
Fetched simultaneously by IFU 102 via The transfer of the instruction set is adjusted between the IFU 102 and the CCU 106 by a control signal transmitted via the control line 116. The virtual address of the instruction set to be fetched is output from IFU 102 via IFU arbitration, control and address bus 118, and further to IEU 104 and VMU 108
The arbitration, control, and address sharing buses 120 connect between them. Arbitration of access to VMU 108 (arbitrati
on) is performed because both the IFU 102 and the IEU 104 use the VMU 108 as a common shared resource. In the preferred embodiment of the present invention, the lower bits defining the address in the physical page of the virtual address are transmitted from IFU 102 to control line 116.
Is transferred directly to the cache control unit 106 via The virtual upper bits of the virtual address provided from IFU 102 are
Where it is translated to the corresponding physical page address. In the IFU 102, this physical page address is transferred from the VMU 108 directly to the cache control unit 106 via the address control line 122 during half an internal processor clock cycle after the translation request is issued to the VMU 108. Transferred to

The instruction stream fetched by IFU 102 is transmitted via instruction stream bus 124 to IEU 104
Passed to. Control signals are sent to IFU via control line 126.
102 and IEU 104. In addition, certain instruction fetch addresses, such as those requiring access to a register file residing in IEU 104, are sent back to the IFU via the target address return bus in control line 126. It is.

The IEU 104 communicates with the data cache 134 provided in the CCU 106 for 80-bit wide bidirectional data.
Data is stored and retrieved through the bus 130. The entire physical address at which the IEU accesses data is passed to the CCU 106 by the address portion of the control bus 128. Further, a control signal for managing data transfer can be exchanged between the IEU 104 and the CCU 106 through the control bus 128. The IEU 104 uses the VMU 108 as a resource to change the virtual data address to a physical data address suitable for passing to the CCU 106. The virtualized portion of the data address is passed to VMU 108 via arbitration, control and address bus 120. IFU 10
Unlike the operation for 2, VMU 108 returns the corresponding physical address to IEU 140 via bus 120.
In the preferred embodiment of architecture 100, IEU 140 uses physical addresses to ensure that load / store operations are performed in the correct program stream order.

The CCU 106 sends a data request defined by a physical address to the instruction cache 132 and the data cache 13.
It has a conventional high-level function to judge whether it is satisfactory from either of the four. The access request is for the instruction cache 132 or data cache 134
If you can be satisfied with accessing the CCU106
Coordinates the data transfer via data buses 114 and 128 and performs that transfer.

If the data access request is an instruction cache
If it is not satisfied from 132 or data cache 134, CCU 106 passes the corresponding physical address to MCU 110, determines whether MAU 112 is requesting a read access or a write access, and CCU per
The IFU provides enough control information and request operations to identify the 106 source or destination caches 132,134.
Additional identifying information is also passed along to correlate with the final data request from 102 or IEU 104.

The MCU 110 preferably includes a port switch unit 142, which is connected by a unidirectional data bus 136 to the instruction cache of the CCU 106.
132, and to a data cache 134 by a bidirectional data bus 138. The port switch 142 is basically a large multiplexer, and transfers the physical address obtained from the control bus 140 to a plurality of ports PoPn.
146o-n, and allows bi-directional transfer of data from ports to data buses 136, 138. Each memory access request handled by MCU 110 is associated with one of ports 146o-n for the purpose of arbitrating access to main system memory bus 162 required when accessing MAU 112. When a connection for data transfer is established, the MCU passes control information to the CCU 106 via the control bus 140, and the instruction cache 132 or data cache via the corresponding one of the ports 141 and 146o-n. Initiate the transfer of data between 134 and MAU 112. architecture
In the preferred embodiment of 100, MCU 110 is actually
Do not store or latch data in the middle of a transfer between 6 and MAU112. This is done to minimize transfer latency and avoid having to track or manage data that is only one in MCU 110. II. Instruction Fetch Unit The main elements of the instruction fetch unit 102 are shown in FIG. In order to facilitate understanding of the operation and interrelationship of these elements, the following description is based on the case where these elements are involved in the IFU data path and control path. A) IFU data path The IFU data path is an instruction bus 11 that receives the instruction set and temporarily stores it in the prefetch buffer 260.
Starts with 4. The instruction set from prefetch buffer 260 is passed through I decode unit 262 to IFIFO unit 264. The instruction set stored in the last two stages of the instruction FIFO 264 is the data bus 278, 280
Through the IEU 104 for continuous use.

Prefetch buffer unit 260
Receives one instruction set from the instruction bus 114 at a time. The complete 128-bit wide instruction set is generally written in parallel to one of four 128-bit wide prefetch buffer locations in the main buffer (MBUF) 188 portion of the prefetch buffer 260. Up to four additional instruction sets, as well as two 128-bit wide target buffers (TBUFs) 190 prefetch buffer locations or two 128-bit wide procedure buffers (EBUFs) 192 prefetch buffer buffers It is possible to write to the location. In the preferred architecture 100, the instruction set located in any of the prefetch buffer locations in the MBUF 188, TBUF 190 or EBUF 192 can be transferred to the prefetch buffer output bus 196. In addition, a direct fall through instruction set bus 194
Connects the instruction bus 114 to the prefetch buffer output bus 19
6 and MBUF 188, TBUF 190
And to bypass EBUF 192.

In the preferred architecture 100, the MBUF 188 is used to buffer the instruction set in the nominal or main instruction stream. TBUF 190 is used to buffer the instruction set prefetched from the trial target branch instruction stream. As a result, through the prefetch buffer unit 260,
An instruction stream in a direction that may be located after a conditional branch instruction can be prefetched. This feature allows the MAU 112 to increase latency, but at least eliminates subsequent access latency to the CCU 112, regardless of which instruction stream is ultimately selected when resolving conditional branch instructions. ,
The correct next instruction set placed after the conditional branch instruction can be obtained and executed. In the preferred architecture 100 of the present invention, the presence of the MBUF 188 and MBUF 190 allows the instruction fetch unit 102 to prefetch both possible instruction streams, , The instruction stream assumed to be correct can be subsequently executed. When the conditional branch instruction is resolved, the correct instruction stream is prefetched,
When placed in MBUF 188, the instruction set remaining in TBUF 190 is only invalidated. On the other hand, if the correct instruction stream instruction set exists in TBUF 190,
Through the instruction prefetch buffer unit 260,
These instruction sets are directly in parallel from TBUF 190,
188 to each buffer location. The instruction set previously stored in MBUF 188 is
Overwriting the instruction set transferred from TBUF 190 is effectively overridden. Without a TBUF instruction set to transfer to an MBUF location, that location would simply be marked invalid.

Similarly, EBUF 192 provides another alternative prefetch path via prefetch buffer 260. EBUF 192 is preferably a single instruction that appeared in the MBUF 188 instruction stream, a "procedure"
It is used when prefetching an alternative instruction stream used to implement the operation specified by the instruction. In this way, complex or extended instructions can be implemented through software routines or procedures, which are already prefetched and
The instruction stream contained at 188 can be processed through the prefetch buffer unit 260 without disturbing it. Generally, according to the present invention, TBUF 1
The procedural instruction appearing at 90 can be processed, but prefetching of the procedural instruction stream is suspended and any previously encountered pending conditional branch instruction streams are resolved. This allows conditional branch instructions that appear in the procedure instruction stream to be
It will be handled consistently through the use of 190. Thus, if a branch is taken in the prosthetic stream, the target instruction set can be transferred to EBUF 192 in parallel since the target instruction set has already been prefetched and placed in TBUF 190.

Finally, MBUF 188, TBUF 190 and EBUF 1
Each of the 92 is connected to a prefetch buffer output bus 196 for sending the instruction set stored by the prefetch unit onto the output bus 196. Further, the flow through bus 194 is for transferring the instruction set directly from instruction bus 114 to output bus 196. In preferred architecture 100, MBUF 18
8. The prefetch buffers in TBUF 190 and EBUF 192 do not directly constitute a FIFO structure. Instead,
Since each buffer location is connected to the output bus 196, there is a great deal of flexibility in the prefetch order of instruction sets fetched from the instruction cache 132. In other words, the instruction fetch unit 102 generally determines and requests an instruction set in the order of instructions arranged in a fixed order in the instruction stream. However, the order in which the instruction sets are returned to the IFU 102 is such that some of the requested instruction sets are available, accessible only by the CCU 106, and other instruction sets require MAU 102 access. It is also possible to appear out of order according to.

Although the instruction sets may not be returned to the prefetch buffer unit 260 in a fixed order, the sequence of instruction sets output on the output bus 196 will generally be the instruction set output from the IFU 102. Must follow the order of the request. This is because the instruction stream sequence in-order is affected by trial execution of the target branch stream, for example.

The I decode unit 262 receives the instruction set from the prefetch buffer output bus 196, usually one per cycle, as space in the IFIFO unit 264 allows. Each set of four instructions that make up one instruction set is an I decode unit 26.
Decoded in parallel by 2. While the relevant control flow information is being pulled out of line 318 for the control path portion of IFU 102, the contents of the instruction set are
Unchanged by unit 262. The instruction set from the I decode unit 162 is 128
It is sent out on a bit width input bus 198. Internally, IF
IFO unit 264 has master / slave register 200,
It is composed of columns 204, 208, 212, 216, 220 and 224. Each register is connected to its subsequent registers, and the contents of master registers 200, 208, and 216 are transferred to slave registers 204, 212, and 220 during the first half of the internal processor cycle of the FIFO operation, and then during the second half of the operation. The data is transferred to the next succeeding master register 208, 216, 224. Input bus 198 is connected to master registers 200, 208, 216, 224
, So that during the second half cycle of the FIFO operation, the instruction set is loaded directly from the I decode unit 262 into the master register. However, loading the master register from input bus 198 need not be done concurrently with FIFO shifting the data in IFIFO unit 264. As a result, the instruction
Regardless of the current depth of the instruction set stored in the FIFO unit 264, and independently of the FIFO shifting of the data in the IFIFO unit 264, the input bus 198 continuously enters the IFIFO unit 264. I can go.

The master / slave registers 200, 204,
Each of 208, 212, 216, and 224 can store all bits of the 128-bit wide instruction set in parallel and store some bits of control information in respective control registers 202, 20.
6, 210, 214, 218, 222, 226. Preferably, the set of control bits is such that exception miss and exception modify (VM
U), no memory (MCU), branch bias, stream, and offset (IFU). This control information originates from the control path portion of IFU 102, as well as loading a new instruction set from input bus 198 into the IFIFO master register. Thereafter, the control register information is shifted in parallel within the IFIFO unit 263 in parallel with the instruction set.

Finally, in the preferred architecture 100, the IF
The output of the instruction set from IFO unit 264 is obtained simultaneously from the last two master registers 216 and 224, B
ucket 0 and I Bucket 1 instruction set output bus 278
, 280. In addition, the corresponding control register information is IBASV0 and IVASV1 control field buses 282, 28
4 Sent up. These output buses 278, 282, 280
, 284 are all instruction stream buses leading to IEU 104
124. B) IFU Control Path The IFU 102 control path directly supports the operation of the prefetch buffer unit 260, I decode unit 262 and IFIFO unit 264. The prefetch control logic unit 266 mainly manages the operation of the prefetch buffer unit 260. Prefetch control logic unit 266 and IFU 10
2 is generally connected to system line from clock line 290.
Receiving the clock signal, IFU operation and IEU
104, the operation of the CCU 106 and the operation of the VMU 108 are synchronized. Select the instruction set and select MBUF
Control signals for writing to 188, TBUF 190 and EBUF 192 are sent on control line 304.

A number of control signals are sent out on control line 316 to the prefetch control logic unit 266. Specifically, a fetch request control signal is sent to initiate a prefetch operation.
The other control signal sent on control line 316 is that the target destination of the requested prefetch operation is an MBUF
It specifies whether it is 188, TBUF 190, or EBUF 192. Upon receiving the prefetch request, the prefetch control logic unit 266 generates an ID value and determines whether the prefetch request can be notified to the CCU 106.
The generation of the ID value is performed using a rotating 4-bit counter.

The use of a 4-bit counter is important in three ways: First, up to nine instruction sets can be active in the prefetch buffer unit 260 at a time. Four instruction sets in the MBUF 188, two instruction sets in the TBUF 190, an instruction set in the EBUF 192, and one instruction set passed directly to the I-decode unit 262 via the flow-through bus 194. Second, the instruction set consists of four instructions, each four bytes. As a result, any address that selects the instruction to be fetched has the least significant four bits extra. Lastly, the prefetch request ID can be easily associated with the prefetch request by inserting it as the least significant 4 bits of the prefetch request address. This reduces the total number of addresses required to interface with the CCU 106.

To ensure that the instruction set is returned from CCU 106 out of order relative to the order of prefetch requests issued from IFU 102, architecture 100
The ID request value is returned together with the return of the instruction set from 106. However, according to the out-of-order instruction set return function, 16 unique IDs may be used up. When a combination of conditional instructions is executed out of order,
There are additional prefetches and instruction sets that have been requested but not yet returned, so that ID values can be reused. Therefore, it is preferable to hold the 4-bit counter, and no prefetch request for the instruction set will be issued thereafter, in which case the next ID value will be the fetch request remaining unprocessed. And at that time are associated with another instruction set held in the prefetch buffer 260.

Prefetch control logic unit 266
Directly manages a prefetch status array (array) 268, which consists of status storage locations that logically correspond to each instruction set prefetch buffer location in MBUF 188, TBUF 190 and EBUF 192. The prefetch control logic unit 266 can scan, read, and write data to the status register array 268 via the select and data lines 306. In array 268, main buffer register 308 contains four 4-bit ID values (MB ID), four 1-bit reserved flags (MBRES), and four 1-bit valid flags.
(MB VAL), each of which is associated with a respective instruction set storage location in MBUF 180 by logical bit position. Similarly, the target buffer register 310 and the extension buffer register 312 each have two 4-bit ID values (TB
ID, EBID) and two 1-bit reserved flags (TB RES, EB RE
S) and two 1-bit valid flags (TB VAL, EB VAL)
Is to be stored. Finally, the flow-through status register 314 stores one 4-bit ID value (FT T
D) This is for storing one reserved flag bit (FT RES) and one valid flag bit (FT VAL).

The status register array 268 is scanned first and, if applicable, the prefetch control logic unit 266 each time a prefetch request is issued to the CCU 266.
, And are scanned and updated each time the instruction set is returned. Specifically, upon receiving a prefetch request signal from control line 316, prefetch control logic unit 216 increments the current cyclic counter generated ID value and scans status register array 268 to determine if an available ID value is available. Determines whether a prefetch buffer location of the type specified by the prefetch request signal is available and checks the state of the CCU IBUSY control line 300 to determine if the CCU 106 can accept the prefetch request. Judge and if acceptable, control line
The CCU IREAD control signal on 298 is asserted and the incremented ID value is sent out on the CCU ID output bus 294 connected to the CCU 106. A prefetch storage location can be used if the corresponding reservation status flag and valid status flag are both false. The prefetch ID indicates that the request is CCU106
In parallel, the ID storage location in the status register array 268 corresponding to the target storage location in the MBUF 188, TBUF 190, or EBUF 192 is written. Further, the corresponding reservation status flag is set to true.

The CCU 106 stores the previously requested instruction set
If it can be returned to IFU 102, the CCUIREADY signal is asserted on control line 302 and the corresponding instruction set ID is the CCU ID
Dispatched on control line 296. The prefetch control logic unit 266 scans the ID value and the reservation flag in the status register array 268, and
The target destination of the instruction set in unit 260 is determined. Only one match is possible. If determined, the instruction set is written via bus 114 to the appropriate location in prefetch buffer unit 260, and if determined to be a flow-through request, the I
Passed to decode unit 262. In both cases,
The valid status flags in the corresponding status register array are set to true.

The PC logic unit 270 examines the entire IFU 102 and examines the MBUF 188,
Find the virtual address of the TBUF190 and EBUF 192 instruction streams. In performing this function, PC logic block 270 controls and operates from I-decode unit 262. Specifically, the instruction portion decoded by the I decode unit 262 and possibly associated with a change in the flow of the instruction stream of the program is transmitted via the bus 318 to the control flow detection unit 274.
And to the PC logic block 270 directly. The control flow detection unit 274 executes each instruction constituting the control flow instruction including conditional branch instruction and unconditional branch instruction, call type instruction, software trap procedure instruction and various return instructions.
Judge from the decoded instruction set. The control flow detection unit 274 sends the control signal via line 322.
Send to PC logic unit 270. This control signal is I
It shows the location and type of control flow instructions in the instruction set residing in decode unit 262. In response, PC logic unit 270 generally determines the target address of the control flow instruction from the data contained in the instruction and transferred to the PC logic unit via line 318. For example, if a branch logic bias was selected to execute first for a conditional branch instruction, PC logic unit 270 would indicate that the instruction set should be prefetched from the conditional branch instruction target address. Start tracking separately. Therefore, the next affirmation of the prefetch request on control line 316 causes the PC logic unit 270
Also asserts the control signal via line 316 and the preceding set of prefetch instructions causes the MBUF 188 or EBUF 192
Prefetch destination is TB
Select as UF 190. If the prefetch control logic unit 266 determines that the prefetch request can be passed to the CCU 106, the prefetch control logic unit 266 again sends an enable signal to the PC logic unit 270 via line 316. send,
Page offset portion of target address (CCU P
ADDR [13: 4]) directly via address line 324
Enables passing to CCU106. At the same time, when a conversion from a new virtual page to a physical page is required, the PC logic unit 270 further transmits a VMU request signal via the control line 328 to the virtualized portion (VMU) of the target address. VADDR [13:14]) to address line 326
To the VMU 108 to convert it to a physical address. If page conversion is not required, no operation by VMU 108 is required. Instead, the previous conversion result is stored in an output latch connected to bus 122 and is immediately used by CCU 106.

If an operation error occurs in the VMU 108 during the virtual to physical conversion requested by the PC logic unit 270, a VMU exception and VMU mismatch control (miss co
ntrol) reported through lines 332,334. The VMU mismatch control line 334 is a translation index buffer.
Report a mismatch in kaside buffer (TLB). The VMU exception control signal on VMU exception line 332 occurs when another exception occurs. In each case, the PC logic unit is
Store the current execution point in the instruction stream,
Thereafter, the error condition is handled by prefetching a dedicated exception handling routine instruction stream for diagnosing and handling the error condition, as if an unconditional branch was taken. The VMU exception and mismatch control signals indicate the type of exception that occurred,
PC logic unit 270 can determine the prefetch address of the corresponding exception handling routine.

The IFIFO control logic unit 272 is an IFIF
O To directly support unit 264.
You. Specifically, the PC logic unit 270
Control signal is output via the
Available from code unit 262 via input bus 198
Notify IFIFO control logic unit 272
I do. IFIFO control unit 272 receives instruction set
The innermost available master registers 200, 20
8, 216 and 224 are selected. Master·
The output of each of the registers 202, 210, 218, 226 is
Is passed to the IFIFO control unit 272 via the
Control bits stored by each master control register
Is the 2-bit buffer address (IF  Bx ADR), simply
One stream indicator bit (IF  Bx STR
M) and a single valid bit (IF Bx VLD)
You. The 2-bit buffer address is stored in the corresponding instruction set.
Specifies the first valid instruction set in the list. That is,
The instruction set returned by CCU 106 is, for example, the branch
・ The target instruction of the operation is the
Aligned to be in the first instruction location
May not. Therefore, the buffer address value
Is the first in the instruction set to be considered for execution
Is given to uniquely identify the instruction.

The stream bits indicate the location of the instruction set containing the conditional control flow instruction;
It is based on being used as a marker to cause a change in staying control flow in the stream of instructions through the IFIFO unit 264. The main instruction stream is generally processed through MBUF 188 when the stream bit value is zero. For example, when a relative conditional branch instruction appears,
The corresponding instruction set is marked and the stream
The bit value becomes 1. Conditional instruction set is I decode
Detected by unit 262. Up to four conditional control flow instructions can be in the instruction set.
Thereafter, the instruction set is stored in the innermost available master register of the IFIFO unit 264.

To determine the target address of the conditional branch instruction, the current IEU 104 execution point address
(DPC), the relative location of the instruction set containing the conditional instruction specified by the stream bits, and the conditional instruction location offset in the instruction set obtained from the control flow detection unit 274, are mapped through the control line 318. With the relative branch offset value obtained from the corresponding branch instruction field. The result is a branch
It becomes the virtual address of the target and is stored by PC logic unit 270. The first instruction set in the target instruction stream can be prefetched into TBUF 190 using this address. Branches preselected for PC logic unit 270
Depending on the bias, IFIFO unit 264 continues to load from MBUF 188 or TBUF 190. When a second instruction set appears that contains one or more conditional flow instructions, the instruction set is marked with a zero stream bit value. Since the second target stream cannot be fetched, the target address is
Calculated and stored by PC logic unit 270, but not prefetched. Further, subsequent instruction sets cannot be processed through I-decode unit 262. At least none of the instruction sets found to contain conditional flow control instructions are processed.

In a preferred embodiment of the present invention, PC logic unit 270 can manage up to eight conditional flow instructions that appear in up to two instruction sets.
The target address of each of the two instruction sets, marked by a stream bit change, is stored in an array of four address registers, where the target addresses are relative to the location of the corresponding conditional flow instruction in the instruction set. Be placed in a logical position.

Once the branch result of the first in-order conditional flow instruction has been resolved, PC logic unit 270 transfers the contents of TBUF 190 to MBUF 188 if the branch is taken and invalidates the contents of TBUF 190. A control signal on line 316 instructs prefetch control unit 260 to mark Incorrect instruction stream,
That is, if the IFIFO unit 264 has an instruction set from the target stream when the branch is not performed and from the main stream when the branch is performed, the instruction set is cleared from the IFIFO unit 264. If a second or subsequent conditional flow control instruction is present in the instruction set marked with the first stream bit, the instruction is processed in a unified manner. That is, the instruction set from the target stream is prefetched, and the instruction set from the MBUF 188 or TBUF 190 is
When the conditional flow instruction is processed through 2 and the conditional resolution is finally resolved, the incorrect stream instruction set
Cleared from unit 264.

When the incorrect stream instruction is cleared from IFIFO unit 264, a second conditional flow instruction remains in IFIFO unit 264, and the first conditional flow instruction set includes subsequent conditional flow instructions. Otherwise, the target address of the instruction set marked with the second stream bit is the address
Promoted to the first array of registers. In either case, the next set of instructions containing the conditional flow instruction will be available for evaluation through I-decode unit 262. Thus, using stream bits as toggles can be used for the purpose of calculating branch target addresses, and when branch bias is later determined to be incorrect for a particular conditional flow control instruction. Instruction set to clear above
For the purpose of marking locations, mark changes in the control flow of the stay-like control flow, and use the IFIFO unit
264 can be tracked.

Instead of actually clearing the instruction set from the master register, the IFIFO control logic unit
272 simply resets the valid bit plug in the control register of the corresponding master register of IFIFO unit 264. This clear operation is a control signal sent out on line 336 and the PC logic unit
Started by 270. Master control register 202, 21
Each of the inputs 0, 218, 226 is connected to the IF via status bus 230.
The IFO control logic unit 272 has direct access. In the preferred embodiment architecture 100,
The bits in these master control registers 202, 210, 218, 2262 can be set by IFIFO control unit 272 in parallel or independently of the data shift operation by IFIFO unit 264. This feature allows asynchronous operation with IEU 104 operations,
Instruction set to master registers 200, 208, 216, 224
, And corresponding status information can be written to the master control registers 202, 210, 218, 226.

Finally, additional control lines on the control and status bus 230 enable and direct IFIFO operation of the IFIFO unit 264. The IFIFO shift is performed by the IFIFO unit 264 in response to the shift request control signal output from the PC logic unit 270 via the control line 336. The IFIFO control unit 272 has master registers 200, 208, 216, 224 that accept the instruction set.
Is available, a control signal is sent via line 316 to the prefetch control unit 266 requesting that the next set of instructions be transferred from the prefetch buffer 260. When the instruction set is transferred, the corresponding valid bit in array 266 is reset. C) IFU / IEU Control Interface The control interface between IFU 102 and IEU 104 is provided by control bus 126. The control bus 126 is connected to the PC logic unit 270 and comprises a plurality of control, address and special data lines. By passing an interrupt request and an acknowledgment control signal via control line 340, IFU 102 can signal an interrupt operation and synchronize with IEU 104. The externally generated interrupt signal is sent to logic unit 270 via line 292. In response, when an interrupt request control signal is issued on line 340, IEU 104 cancels the trially executed instruction. Information about the contents of the interrupt is exchanged via an interrupt information line 341. When IEU 104 is ready to begin receiving instructions prefetched from the address of the interrupt service routine as determined by PC logic unit 270,
IEU 104 asserts the interrupt acknowledge control signal on line 340. The interrupt service routine prefetched by IFU 102 is then started.

The IFIFO read (IFIFO RD) control signal is IEU10
4 to indicate that the instruction set residing in the innermost master register 224 has completed execution and that the next instruction set is needed. Upon receiving this control signal, the PC logic unit 270 sends the IFIFO unit 264
Perform IFIFO shift operation on IFIF
O Instruct the control logic unit 272.

The PC increment request and the size value (PC INC /
SIZE) is sent on control line 344 to instruct PC logic unit 270 to update the current program counter value by the corresponding size number of instructions. This causes the PC logic unit 270 to place the execution program counter (DP) at the exact location of the first in-order execution instruction in the current program instruction stream.
C) can be maintained.

The target address (TARGET ADDR) is transmitted via the address line 346 to the PC logic unit 27.
Returned to 0. This target address is IEU 104
Is the virtual target address of the branch instruction determined by the data stored in the register file of FIG. Therefore, to calculate the target address IE
U104 operation required. Control flow result
The (CF RESULT) control signal is sent via control line 348 to the PC logic unit 270 to determine whether the currently pending conditional branch instruction has been resolved, whether the result was due to the branch, or not. It indicates that it is not a problem. Based on these control signals, the PC
Logic unit 270 can determine which of the instruction sets located in prefetch buffer 260 and IFIFO unit 264 need to be canceled as a result of execution of the conditional flow instruction.

Some IEU instruction return type control signals (I
(EU return) is sent out on control line 350 and
4 informs IEU 102 that an instruction has been executed. These instructions include returns from procedure instructions, returns from traps, and returns from subroutine calls. The return instruction from the trap is executed by the hardware interrupt processing routine and software
Used similarly in trap handling routines. Returns from subroutine calls are also used with jumps and linked calls. In each case, the return control signal
Sent to notify IFU 102 to restart the instruction fetch operation for a previously interrupted instruction stream. By issuing these signals from IEU 104, accurate operation of system 100 can be maintained. Resume of the "interrupted" instruction stream occurs from the point of execution of the return instruction.

The current instruction execution PC address (current IF PC) is sent to the IEU 104 via the address bus 352. This address value (DPC) specifies the exact instruction to be executed by IEU 104. In other words, IEU 104 is the current IF During the first trial execution of an instruction that has passed the PC address, this address is used for interrupts, exceptions, and other events that require a precise machine state to be known. Must be maintained for precise control. It is possible to advance the exact machine state in the currently executing instruction stream
When the IEU 104 determines, the PC Inc / Size signal is sent to the IFU 102 and the current IF Reflected in the PC address value.

Finally, the address and bi-directional data bus 354 is for transferring data of special registers. This data can be programmed by the IEU 104 into special registers within the IFU 102, or read from there. The data in the special registers is generally stored in IEU 104
Loaded or calculated by D) Details of PC logic unit PC control unit 362, interrupt control unit 363, prefetch PC control unit 364, and execution PC control unit 36
A detailed view of the PC logic unit 270, including 6 is shown in FIG. The PC control unit 362 has an interface
Prefetch control unit 266 via bus 126, IFIF
O Upon receiving control signals from the control logic unit 272 and the IEU 104, the prefetch and execution PC control units 364 and 366 are subjected to timing control. The interrupt control unit 363 is responsible for accurate management of interrupts and exceptions, including determining the prefetch trap address offset and selecting the appropriate processing routine to handle each trap type. The prefetch PC control unit 364 includes a prefetch buffer 188, which includes, among other things, storing return addresses for trap processing and the flow of procedure routine instructions.
, 190, and 192 are responsible for managing the program counters needed to support them. To support this operation, the prefetch PC control unit 364
Is responsible for generating a prefetch virtual address including the CCU PADDER address on physical address bus line 324 and the VMU VMADDR address on address line 326. As a result, the prefetch PC control unit 364
Responsible for retaining the current prefetch PC virtual address value.

The prefetch operation is generally initiated by IFIFO control logic unit 272 through control signals sent on control line 316. In response, the PC control unit 362 generates and outputs a number of control signals on the control line 372, activates the prefetch PC control unit, and sets the PADDR address on the address lines 324 and 326 and the necessary address. Generate a VMADDR address accordingly. An increment signal with a value of 0 to 4 may also be sent on control line 374, which indicates that PC control unit 362 is re-executing the instruction set fetch from the current prefetch address, or a series of It depends on whether the second request among the prefetch requests is aligned, or whether the next full sequential instruction set is selected for prefetch. Finally, the current prefetch address PF The PC is sent out on the bus 370 and passed to the execution PC control unit 366.

How many new prefetch addresses
Originating from that source. The primary source of addresses is
Sent from execution PC control unit 366 via bus 352
Current IF PC address. In principle, IF PC ad
Address gives the return address, which is
When a call, trap or procedure instruction appears
Used later by the prefetch PC control unit.
It is what is done. IF The PC address is
Each time the prefetch PC control unit 364
Stored in the star. In this way, the PC control unit
362 receives the IEU return signal via control line 350
Return in the prefetch PC control unit 364
-Select an address register to create a new prefetch temporary
All you need to do is retrieve the virtual address,
Restart the program instruction stream.

Another source of prefetch addresses is the target sent from the execution PC control unit 366 via the relative target address bus 382 or the IEU 104 via the absolute target address bus 346.・ It is an address value. The relative target address is an address that can be directly calculated by the execution PC control unit 366. Absolute target addresses must be generated by IEU104 because these target addresses depend on the data contained in the IEU register file. The target address is sent to the prefetch PC control unit 364 via the target address bus 384 and is used as a prefetch virtual address. When calculating the relative target address, the operand portion of the corresponding branch instruction is also sent from I decode unit 262 via the operand displacement portion of bus 318.

Another source of prefetch virtual addresses is the execution PC control unit 366. The return address bus 352 'is connected to the current IF This is for transferring the PC value (DPC) to the prefetch PC control unit 364.
This address is used as the return address where control flow instructions such as interrupts, traps, and other calls appear in the instruction stream. Prefetch PC
Control unit 364 is released to prefetch a new instruction stream. PC control unit 362 receives an IEU return signal from IEU 104 via line 350 when the corresponding interrupt or trap handling routine or subroutine is executed. On the other hand, PC control unit
362 selects the register containing the current return virtual address through one of the PFPC signals on line 372 and based on the ID of the executed return instruction sent over line 350. This address is then used to continue the prefetch operation by PC logic unit 270.

Finally, another source from which the prefetch virtual address is retrieved is the special register address and data bus 354. The address value calculated or loaded by the IEU 104, or at least the base address value, is transferred as data via the bus 354 to the prefetch PC control unit 364. The base address includes the addresses of the trap address table, the fast trap table, and the base procedure instruction dispatch table. Bus 35
4, through the procedure and PC control unit 364,
You can also read many of the registers in the 366,
Corresponding aspects of the state of the machine can be processed through IEU 104.

The execution PC control unit 366 is a PC control unit.
Under the control of 362 Calculate PC address value
The main role is to Perform in this role
PC control unit 366 is ExPC controlled from PC control unit 362
The control signal sent via line 378 and the control signal
Increment / size sent via in 380
Receiving the control signal, Adjust the PC address. this
These control signals were mainly sent via line 342
IFIFO read control signal and control line 344 from IEU 104
Receive PC increment / size value sent by
Is generated. 1) Details of PF and ExPC control / data unit Fig. 4 shows the prefetch and execution PC control unit 364,
366 is a detailed block diagram of FIG. These units are primarily
, Registers, incrementers and other similar
Components, selectors and adder blocks.
You. Control to manage data transfer between these blocks
PFPC control line 372, ExPC control line 378 and
PC control unit through increment control lines 374 and 380
Done by 362. To make the description easier to understand
For example, the block diagram of FIG.
Not shown. However, these control signals are
As explained in, what is sent to these blocks
Of course.

The center of the prefetch PC control unit 364 is a prefetch selector (PF). PC SEL), which acts as the central selector for the current prefetch virtual address. This current prefetch address is sent from the prefetch selector to the incrementer unit 394 via the output bus 392, and is sent to the next prefetch address.
Generate an address. This next prefetch address is passed to register MBUF P via incrementer output bus 396.
Sent to a parallel array of FnPC 398, TBUF PFnPC 400, and EBUF PFnPC402. These registers 398, 400, 402
Effectively stores the next instruction prefetch address, but according to the preferred embodiment of the present invention, the separate prefetch addresses are MBUF 188, TBUF190, and EBUF
Held at 192. Prefetch registers stored in MBUF, TBUF and EBUF PFnPC registers 398, 400, 402
The address is passed from address buses 404, 408, 410 to prefetch selector 390. Therefore, the PC control unit 362 determines the prefetch registers 398, 400, 402
By simply instructing the prefetch selector to select another one of the prefetch instruction streams, immediate switching of the prefetch instruction stream can be indicated. To prefetch the next set of instructions in the stream, the address value is incremented by incrementer 394, and the value is incremented by prefetch addresses 398, 400, 402.
Is returned to the corresponding register. Another parallel register array is shown as a single special register block 412 for simplicity, but this array is for storing some special addresses. Register block 412 contains the trap return address register, procedure instruction return address register, procedure instruction dispatch table base address register, trap routine dispatch table base address register, and fast trap. -Consists of a routine base address register. Under the control of the PC control unit 362, these return address registers
Current IF through 5 ' Can accept PC execution address. The address value stored in the return and base address registers in register block 412 is
Can read and write independently of IEU 104. The register is selected and the value is transferred via the special register address and data bus 354.

The selector in the special register block 412 is controlled by the PC control unit 362, and sends the address stored in the register of the register block 412 onto the special register output bus 416 and passes it to the prefetch selector 390. Can be. The return address is passed directly to the prefetch selector 390. base·
The address value is combined with the offset value sent from the interrupt control unit 363 via the interrupt offset bus 373. The special address passed to the prefetch selector 390 from the source via bus 373 'is used as the initial address for a new prefetch instruction stream, after which the incrementer 394 and prefetch register 398
, 400, 402, the address increment loop can continue.

Another source of addresses sent to the prefetch selector 390 is the target address
This is the register array in the register block 414. In the target register in block 414, according to the preferred embodiment, eight persistent branch target addresses are stored. These eight storage locations are
The lowest two master registers 216 of the IFO unit 264,
224 logically correspond to the eight permanently executable instructions. Since any of these instructions, and possibly all of them, can be conditional branch instructions, the target register block 414 stores the pre-computed target address so that the target instruction You can wait to use the stream to prefetch. In particular, if the conditional branch bias is set such that the PC control unit 362 immediately begins prefetching the target instruction stream, the target address is prefetched from the target register block 414 via the address bus 418.・ Selector 390
Sent to After being incremented by the incrementer 394, the address is stored back into the TBUF PFnPC 400 for use in operations that later prefetch the target instruction stream. When another branch instruction appears in the target instruction stream, the target address of the second branch is calculated and stored in the target register array 414 until the first conditional branch instruction is resolved and used. ing.

The calculated target address stored in the target register block 414 can be obtained from the target address calculation unit in the execution PC control unit 366 via the address line 382, or
Transferred from IEU 104 via absolute target address bus 346.

Prefetch PF The address value transferred through PC selector 390 is a complete 32-bit virtual address value. The page size is, in a preferred embodiment of the invention,
It is fixed at 16 Kbytes and corresponds to the maximum page offset address value [13: 0]. Therefore, if there is no change in the current prefetch virtual page address [27:14], VMU page conversion is unnecessary. The comparator in the prefetch selector 390 detects this. VMU
The translation request signal (VMXLAT) is sent to the PC via line 372 'when the virtual page address changes, either because the increment has been made across a page boundary or because the control flow has branched to another page address. Control unit 362
Sent to On the other hand, the PC control unit 362 buffers the VM VADDR address in addition to the CCU PADDR on line 324.
Unit 420 on line 326 and the appropriate control signal on VMU control lines 326, 328, 330 to provide the VM
U Indicates that a conversion from virtual pages to physical pages should be obtained. If page conversion is not required, the current physical page
The address [31:14] is held by a latch on the output side of the VMU unit 108 on the bus 122.

The virtual address transmitted on the bus 370 is incremented by the incrementer 394 in response to the signal transmitted from the increment control line 374. The incrementer 394 is a value representing the instruction set (4 instructions or 16 bytes) to select the next instruction set
Only increment. The lower 4 bits of the prefetch address passed to CCU unit 106 are zero. Thus, the actual target address instruction in the first branch target instruction set may not be located at the first instruction location. However, the lower four bits of the address are sent to the PC control unit 362 so that the IFU 102 can determine the location of the first branch instruction. The detection and processing to return the low order bits [3: 2] of the target address as a 2-bit buffer address and to select the correct first instruction to execute from the unaligned target instruction set is a new instruction It occurs only at the first prefetch of the stream, the first non-sequential instruction set address in the instruction stream. The unaligned relationship between the address of the first instruction in the instruction set and the prefetch address used in prefetching the instruction set can be ignored during the life of the current sequential instruction stream. It is neglected.

The remaining part of the functional branch shown in FIG. 4 constitutes the execution PC control unit 366. According to a preferred embodiment of the present invention, the execution PC control unit 366 has its own independently functioning program counter incrementer. At the heart of this feature is the execution selector (DPC S
EL) 430. Execution selector 430 to address bus 35
The address output on 2 'is the current execution address (DPC) of architecture 100. This execution address is sent to the addition unit 434. The increment / size control signal sent on line 380 specifies the instruction increment value from 1 to 4, which is the value of the adder unit.
434 adds to the address obtained from selector 430. Each time adder 432 performs an output latch function, the next incremented execution address is returned directly to execution selector 430 via address line 436 and used in the next instruction increment cycle.

The initial execution address and all subsequent new stream addresses are obtained from new stream register unit 438 via address line 440. The new stream register unit 438 can either pass the new current prefetch address sent from the prefetch selector 390 via the PFPC address bus 370 directly to the address bus 440, or use it for later use. You can also store it. That is, if the prefetch PC control unit 364 determines to start prefetching from a new virtual address, the new stream address is temporarily stored by the new stream register unit 438. By participating in both prefetch and execution increment cycles, the PC control unit 363 stores the new stream address in the new stream register until the execution address reaches the program execution location corresponding to the control flow instruction that started the new instruction stream. At 438. The new stream address is then output from the new stream register unit 438 and sent to the execution selector 430 to begin independently generating execution addresses in the new instruction stream.

According to a preferred embodiment of the present invention, the new stream register unit 438 has the ability to buffer two control flow instruction target addresses. By immediately extracting the new stream address, the execution PC control unit 366 can be switched from the generation of the current execution address sequence to the generation of the new execution unit stream sequence with almost no waiting time.

Finally, IF PC selector (IF (PC SEL) is finally the current IF This is for sending the PC address to the address bus 352 and sending it to the IEU 104. IF The input to the PC selector 442 is the output address obtained from the execution selector 430 or the new stream register unit 438. In most cases, IF PC selector 442 is a PC control unit
In response to the instruction of 262, the execution address output from the execution selector 430 is selected. However, to further reduce latency when switching to the new virtual address used to start execution of the new instruction stream, the selected address from the new stream register unit 438 is bypassed via bus 440. IF directly at PC selector 442
To the current IF Can be obtained as PC execution address.

The execution PC control unit 366 has a function of calculating all relative branch target addresses. Current execution point address and new stream register
The address obtained from unit 438 is transferred to address bus 35
2 ', 340 via control flow selector (CF (PC) 446
Passed to. As a result, the PC control unit 362 has great flexibility to select the correct initial address on which to calculate the target address. This initial address, the base address, is the address bus 45
It is sent via 4 to the target address ALU 450. Another value to be input to the target ALU 450 is sent from the control flow displacement calculation unit 452 via the bus 458. Relative branch instructions are
According to one hundred preferred embodiments, it includes a displacement location in the form of an immediate mode constant specifying a new relative target address. The control flow displacement calculation unit 452 receives the first operand displacement from the I decode unit operand output bus 318. Finally, the offset register value is read via line 456 to the target address AL
Sent to U450. Offset register 448 receives the offset value from PC control unit 362 via control line 378 '. The magnitude of the offset value is the address line
454 PC control unit based on address offset to current branch instruction address when calculating relative target address from base address sent on
362. In other words, the PC control unit 362
By controlling the IFIFO control logic unit 272, the instruction (CP Tracks the number of instructions currently being processed by the I-decode unit 262 and thus separating the instruction being processed by the PC logic unit 270 to determine the target address of the instruction. I do.

If the relative target address is
Once calculated by address ALU 450, the target address is written to corresponding target register 414 via address bus 382. 2) Details of PC control algorithm Main instruction stream processing: MBUF PFnP
C1.1 The address of the next main flow prefetch instruction is stored in MBUF PFnPC. 1.2 In the absence of a control flow instruction, the 32-bit incrementer adjusts the address value contained in MBUF PFnPC by 16 bytes (x16) for each prefetch cycle. 1.3 When an unconditional control flow instruction is I decoded,
All prefetch data fetched following the instruction set is flushed, and the MBUF PFnPC contains the target register unit, PF The new main instruction stream address is loaded through the PC selector and incrementer. The new address is also stored in the new stream register.

1.3.1 The target address of the relative unconditional control flow is obtained from the register data held by the IFU and the operand address placed after the control flow instruction.
Calculated by IFU from data. 1.3.2 The target address of the absolute unconditional control flow is finally calculated by the IEU from the register reference, base and index register values. 1.3.2.1 The instruction prefetch cycle stops until the target address is returned from the IEU for an absolute address control flow instruction. The instruction execution cycle continues. 1.4 The address of the next main flow prefetch instruction obtained from the unconditional control flow instruction is bypassed,
Target address register unit, PF_P
Sent via the C selector and incrementer and finally stored in the MBUF PFnPC, prefetching continues from 1.2. 2. Processing of procedure instruction stream: EBUF P
FnPC 2.1 procedural instructions are prefetched in the main or branch target instruction stream. If fetched in the target stream, the conditional control fetch instruction is resolved and prefetching of the procedure stream stops until the procedure instruction is transferred to the MBUF. This allows TBUF to be used when processing conditional control flows that appear in the procedure instruction stream. 2.1.1 Procedure instructions must not be in the procedure instruction stream. That is, procedure instructions must not be nested. Upon return from the procedural instruction, execution returns to the main instruction stream. To enable nesting, another dedicated return from the nested procedure instruction is needed. While the architecture can easily support this type of instruction, the ability to nest procedural instructions is unlikely to improve the performance of the architecture. 2.1.2 In the main instruction stream, a procedural instruction stream that includes an instruction set that includes first and second conditional control flow instructions is resolved by a conditional control flow instruction in the first instruction set; Stop prefetching for the second conditional control flow instruction set until the two conditional control flow instruction sets are transferred to the MBUF. 2.2 The procedure instruction indicates the start address of the procedure routine by the relative offset included as the immediate mode operand field of the instruction. 2.2.1 The offset value obtained from the procedure instruction is combined with the value contained in the Procedure Base Address (PBR) register maintained in the IFU. This PBR register is readable and writable through a special address and data bus when a special register move instruction is executed. 2.3 When a procedure instruction appears, the next main instruction stream IF The PC address is stored in the DPC return address register and the procedure-in-progress bi in the processor status register (PSR).
t) is set. 2.4 The starting address of the procedure stream is
From the PBR register (plus the procedure instruction operand offset value) to PF Sent to PC selector. 2.5 The starting address of the procedure stream is
Sent to the new stream register unit and incrementer at the same time, incrementing by (x16). The incremented address is then EBUFPFn
Stored in PC. 2.6 Without a control flow instruction, the 32-bit incrementer adjusts the address value in EBUF PFnPC by (x16) every procedure instruction prefetch cycle. 2.7 When an unconditional control flow instruction is I decoded,
All prefetch data fetched after the branch instruction is flushed and the EBUF PFnPC is loaded with the new procedure instruction stream address. 2.7.1 Target of relative unconditional control flow instruction
The address is calculated by the IFU from the register data held in the IFU and the operand data contained in the immediate mode operand field of the control flow instruction. 2.7.2 The target address of the absolute unconditional branch is calculated by the IEU from the register reference value, the base register value and the index register value. 2.7.2.1 Instruction Prefetch Cycles When Target Address is IE for Absolute Address Branch
Stop until returned from U. The execution cycle continues. 2.8 The address of the next procedure prefetch instruction set is stored in EBUFPFnPC, and prefetching continues from 1.2. 2.9 When the return from the procedural instruction is I-decoded, prefetching is continued from the address stored in the uPC register, then incremented by (x16), and M
Returned to BUF PFnPC register. 3 Processing of branch instruction stream: TBUF PFn
When the conditional control flow instruction that appears in the first instruction set in the PC 3.1 MBUF instruction stream is I-decoded, the target address is an absolute address by the IFU if the target address is relative to the current address. If determined by the IEU. 3.2 For "Bias to Branch": 3.2.1 If a branch is taken to an absolute address, stop the instruction prefetch cycle until the target address is returned from the IEU. The execution cycle continues. 3.2.2 Load branch target address into TBUF PFnPC by transferring via PF_PC selector and incrementer. 3.2.3 IF to execute after target instruction stream is prefetched and placed in TBUF
Sent to the IFO. When the IFIFO and TBUF are full, stop prefetching. 3.2.4 32-bit incrementer adjusts the address value in TBUF PFnPC by (x16) every prefetch cycle. 3.2.5 If the conditional control flow instruction appearing in the second instruction set in the target instruction stream is I-decoded, the prefetch operation is performed and all conditional branch instructions in the first (main) set are executed. Stop until resolved (but go ahead and calculate the relative target address and store it in the target register). 3.2.6 If the conditional branch in the first instruction set is interpreted as "taken": 3.2.6.1 when the source of the branch is the EBUF instruction set determined from the procedure in progress bit Flushes the instruction set placed after the first conditional flow instruction set in the MBUF or EBUF. 3.2.6.2 Based on the state of the procedure in progress bit, the TBUF PFnPC value is changed to the MBUF PFnP value.
Transfer to C or EBUF. 3.2.6.3 Transfer the prefetched TBUF instruction to MBUF or EBUF based on the state of the procedure in progress bit. 3.2.6.4 If the second conditional branch instruction set has not been I-decoded, continue the MBUF or EBUF prefetch operation based on the state of the procedure-in-progress bit. 3.2.6.5 If the second conditional branch instruction has been I-decoded, start processing the instruction (go to step 3.3.1). 3.2.7 If conditional control for instructions in the first conditional instruction set is interpreted as "do not perform": 3.2.7.1 IFIFO and IEU of instruction set and instructions from target instruction stream Flash. 3.2.7.2 Continue MBUF or EBUF prefetch operation. 3.3 For "Bias not taken": 3.3.1 Stop prefetching instructions into MBUF. Continue the execution cycle. 3.3.1.1 If the conditional control flow instruction in the first set of conditional instructions is relative, calculate the target address and store it in the target register. 3.3.1.2 If the conditional control flow instruction in the first set of conditional instructions is absolute, wait until the IEU calculates the target address and returns that address to the target register. 3.3.1.3 Once the I-decode of a conditional control flow instruction in the second instruction set has been performed, a prefetch operation is performed until the conditional control flow instruction in the first conditional instruction set is resolved. Stop. 3.3.2 Once the target address of the first conditional branch has been calculated, it loads into the TBUF PFnPC and begins prefetching instructions into the TBUF in parallel with the execution of the main instruction stream. The target instruction set is not loaded (therefore, a branch target instruction is provided when each conditional control flow instruction in the first instruction set is resolved). 3.3.3 If the conditional control flow instruction in the first set is interpreted as "taken": 3.3.3.1 The state of the procedure in progress bit if the source of the branch is an EBUF instruction stream Flushes the MBUF or EBUF,
Flush the IFIFO and IEU for instructions from the main stream placed after the first conditional branch instruction set. 3.3.3.2 TBUF PFnPC value is determined by MBUF as determined from the state of the procedure in progress bit.
Transfer to PFnPC or EBUF. 3.3.3.3 As determined from the state of the procedure in progress bit, the prefetched TBUF instruction is
Transfer to UF or EBUF. 3.3.3.4 Continue MBUF or EBUF prefetch operation as determined from the state of the procedure in progress bit. 3.3.3.4 If a conditional control flow instruction in the first set is parsed as "not done": 3.3.4.1 Flush instruction set TBUF from target instruction stream. 3.3.4.2 If the second conditional branch instruction was not I-decoded, continue the MBUF or EBUF prefetch operation as determined by the state of the procedure in progress bit. 3.3.4.3 If the second conditional branch instruction is I-decoded, start processing the instruction (go to step 3.4.1). 4. Interrupt, Exception and Trap Instructions 4.1 Traps broadly consist of:

4.1.1 Hardware Interrupt 4.1.1.1 Asynchronous (External) Occurring Event, Internal or External. 4.1.1.2 Generates and persists at any time. 4.1.1.3 Service is received in priority order among atomic (normal) instructions, and procedure instructions are suspended. 4.1.1.4 The start address of the interrupt handler is determined as a vector number offset to a predefined table at the entry point of the trap handler. 4.1.1.2 Software trap instruction 4.1.2.1 Asynchronous (external) generation instruction. 4.1.2.2 Software instructions executed as exceptions. 4.1.2.3 The starting address of the trap handler is determined from the trap number offset combined with the base address value stored in the TBR or FTB register. 4.1.3 Exceptions 4.1.3.1 Events that occur in synchronization with instructions. 4.1.3.2 Processed when an instruction is executed. 4.1.3.3 As a result of the exception, the expected instruction and all subsequent instructions are canceled. 4.1.3.4 The start address of the exception handler is determined from the trap number offset to the predefined table at the entry point of the trap handler. 4.2 Trap instruction stream operations are performed inline with the currently executing instruction stream. 4.3 Provided that the trap handling routine saves the xPC address before the next interruptible trap,
Traps can be nested. Otherwise, if the trap appears before the completion of the current trap operation,
The state of the machine will be broken. 5 Processing of the trap instruction stream: xPC 5.1 When a trap appears: 5.1.1 When an asynchronous interrupt occurs, the instruction being executed at that time is suspended. 5.1.2 When a synchronous exception occurs, the trap is processed when the instruction that caused the exception is executed. 5.2 When a trap is processed: 5.2.1 Interrupts are disabled. 5.2.2 Current IF The PC address is stored in the xPC trap status return address register. 5.2.3 IF The IFIFO and MBUF prefetch buffer at the PC address and subsequent addresses are flushed. 5.2.4 Address IF The executed instruction at the PC, the address following it, and the result of the instruction are flushed from the IEU. 5.2.5 MBUF PFnPC is loaded with the address of the trap handler routine. 5.2.5.1 The source of the trap is the trap determined by the trap number contained in the special register group.
The TBR or FTB register is addressed according to the type. 5.2.6 Instructions are prefetched and put into IFIFO for normal execution. 5.2.7 Trap routine instruction is executed thereafter. 5.2.7.1 The trap handling routine has the ability to save the xPC address to a predetermined location and re-enable interrupts. The xPC register is a special register move instruction, and the special register address and data
Read and write through the bus. 5.2.8 It is necessary to get out of the trap state by executing the return from the trap instruction. If you saved 5.2.8.1 or earlier, you must restore the xPC address from its predefined location and then execute a return from the trap instruction. 5.3 When return from trap instruction is executed: 5.3.1 Interrupts are enabled. 5.3.2 The xPC address is returned to the current instruction stream register MBUF or EBUF PFnPC, as determined from the state of the procedure in progress bit, and prefetching continues from that address. 5.3.3 xPC address is restored to IFPC register through new stream register. E) Handling of interrupts and exceptions 1) Overview Interrupts and exceptions, as long as they are enabled, indicate whether the processor is executing from the main instruction stream,
Processed regardless of whether it is being executed from the procedural instruction stream. Interrupts and exceptions are serviced in priority order and persist until cleared. The start address of the trap handler is
It is determined as a vector number offset to the predefined table of the handler.

In this embodiment, there are basically two types of interrupts and exceptions. That is, those that are triggered synchronously with specific instructions in the instruction stream and those that are triggered asynchronously with specific instructions in the instruction stream. Interrupts, exceptions, traps and faults (fau
The term lt) is used interchangeably herein. Non-registered interrupts are caused by on-chip or off-chip hardware that is not operating synchronously with the instruction stream. For example, an interrupt triggered by an on-chip timer / counter may be a hardware interrupt or a non-maskable interrupt (NMI) triggered off-chip
As with, it is asynchronous. When an asynchronous interrupt is triggered, the processor context is frozen (froze
n), all traps are disabled, some processor status information is stored, and the processor directs the vector to the interrupt handler corresponding to the particular interrupt received. When the interrupt handler has completed its processing, program execution continues with the instruction following the last completed instruction in the stream being executed at the time of the interrupt.

[0079] Synchronous exceptions are exceptions that are triggered in synchronization with the instructions in the instruction stream. These exceptions are raised in connection with a particular instruction and are suspended until the instruction in question is executed. In the preferred embodiment, the synchronization exception is raised during prefetch, instruction decode, or instruction execution. The prefetch exceptions include, for example, TLB mismatch and other VMU exceptions. A decode exception is triggered, for example, if the instruction being decoded is an illegal instruction or does not match the current privilege level of the processor. Execution exceptions are caused, for example, by arithmetic errors such as division by zero.
When these exceptions occur, the preferred embodiment associates the particular instruction that caused the exception with the exception, and the instruction is retired.
That state is maintained until it is retired. At that point, all previously completed instructions are saved and any trial results from the instruction that caused the exception are flushed, as are the trial results of subsequent trial-executed instructions. Thereafter, control is passed to the exception handler corresponding to the highest priority exception caused by the instruction.

The software trap instruction is CF DET 27
4 (FIG. 2) is detected at the I decode stage and processed in the same way as an unconditional call instruction or other synchronous trap. That is, the target address is calculated and prefetching continues to the current prefetch queue (EBUF or MBUF). At the same time, the exception is recorded in association with the instruction and processed when the instruction is saved. All other types of synchronous exceptions are only recorded and accumulated in association with the particular instruction that caused the exception, and are processed at run time. 2) Asynchronous interrupt Asynchronous interrupt is notified to PC logic unit 270 via interrupt line 292. As shown in FIG. 3, these lines are for notifying the interrupt logic unit 363 in the PC logic unit 270, and include an NMI line, an IRQ line, and a set of interrupt level lines (LV).
L) The NMI line signals a non-maskable interrupt and originates from an external source. This is the highest priority interrupt except for a hardware reset. IRQ
Lines also originate from an external source and signal when an external device has requested a hardware interrupt. In the preferred embodiment, up to 32 externally generated hardware interrupts can be user-defined, and the specific external device requesting the interrupt will send the interrupt number (0-31) on the interrupt level line (LVL). I do. The memory error line is activated by the MCU 110 to signal various types of memory errors. Other asynchronous interrupt lines (not shown) are also provided to notify interrupt logic unit 363. These include lines for requesting timer / counter interrupts, memory input / output (I / O) error interrupts, machine check interrupts, and performance monitor interrupts. Each of the asynchronous interrupts is associated with a corresponding predefined trap number, similar to the synchronous exceptions described below. 32 of these trap numbers are associated with 32 hardware interrupt levels. A table of these trap numbers is maintained in the interrupt logic unit 363. Generally, the higher the trap number, the higher the priority of the trap.

When one of the asynchronous interrupts is notified to the interrupt logic unit 363, the interrupt control unit 363 sends an interrupt request to the IEU 10 via the INT REQ / ACK line 340.
Send to 4. The interrupt control unit 363 also sends a prefetch suspend signal via line 343 to the PC control unit 262, causing the PC control unit 262 to stop prefetching instructions. The IEU 104 cancels all currently executing instructions, aborts all trial results, or completes some or all instructions. The preferred embodiment speeds up the response to asynchronous interrupts by canceling all currently executing instructions. In any case, the execution PC control unit 366
Within the DPC, before IEU 104 acknowledges the receipt of the interrupt,
Finally, it is completed and updated to correspond to the saved instruction. Prefetched for MBUF, EBUF, TBUF, and IF
All other instructions located in IFO 264 are also canceled.

The IEU 104 sends an interrupt acknowledgment signal back to the interrupt control unit 363 via the INT REQ / ACK line 340 only when it is ready to receive an interrupt from the interrupt handler. Upon receiving this signal, the interrupt control unit 363 dispatches to the appropriate trap handler, as described below. 3) Synchronous exception In the case of synchronous exception, the interrupt control unit 363 has one set of internal exception bits (not shown) for each instruction set, and each bit is associated with each instruction in the set. I have. The interrupt control unit 363 also maintains a trap number to notify when found in each instruction.

If the VMU reports a TLB mismatch or another VMU exception while a particular instruction set is being prefetched, this information is sent to the PC logic unit 270, in particular to the interrupt control unit 334, to the VMU control lines 332, 334. Sent via. Upon receiving this signal, the interrupt control unit 363 notifies the PC control unit 362 via the line 343 to suspend the subsequent prefetch. At the same time, the interrupt control unit 363 is associated with the prefetch buffer to which the instruction set is sent.
VM Miss or VM Set the Excp bit, whichever is applicable. Then, since none of the instructions in the instruction set are valid, the interrupt control unit 363 sets all four internal exception indicator bits corresponding to that instruction set, Store the trap number of the particular exception received for each of the instructions. Shifting and execution of instructions prior to the offending instruction will continue as usual until the offending instruction set reaches the lowest level in IFIFO 264.

Similarly, the prefetch buffer 260, I
If another synchronization exception is detected while shifting instructions through decode unit 262 or IFIFO 264, this information is also sent to interrupt control unit 363 and unit 36
3 sets the internal exception indicator bit corresponding to the instruction that caused the exception and stores the trap number corresponding to the exception. As with the prefetch synchronization exception, the shifting and execution of the instruction prior to the offending instruction will continue as usual until the instruction set in question reaches the lowest level in IFIFO 264.

In the preferred embodiment, the prefetch buffer
260, through I decode unit 262 or IFIFO 264
Exceptions detected while shifting instructions by
There is only one type of software trap instruction. soft
The wear trap instruction is CF By DET unit 274
Detected at I decode stage. In some embodiments
Indicates that another form of synchronous exception is detected in the I decode stage
Detection of other synchronous exceptions
It is preferable to wait until you arrive at 104. this
So that it happens when processing privileged instructions
Some exceptions change before instructions are effectively executed in order.
Is notified based on the processor status
Is prevented. Processor state, like illegal instruction
-Independent exceptions can be detected in the I decode stage
However, all pre-execution synchronization exceptions (except for VMU exceptions)
) With the same logic, at least
Hardware. Also, such an example
Since outside processing rarely focuses on time,
Time wasted waiting for instructions to reach execution unit 104
Nor.

As described above, the software trap instruction is CF Detected by the DET unit 274 in the I decode stage. The internal exception indicator bit corresponding to the instruction in interrupt logic unit 363 is set, and a number from 0 to 127 is assigned to the software trap number that can be specified in the immediate mode field of the software trap instruction. Stored. However, unlike the prefetch synchronous exception, the software trap is treated not only as a control flow instruction but also as a synchronous exception.
Does not notify the PC control unit 362 to suspend prefetching when a software trap instruction is detected. Instead, IFU 102 prefetches the trap handler into the MBUF instruction stream buffer at the same time that the instruction is shifted to signal IFIFO 264.

Instruction set up to the lowest level of IFIFO 264
Upon reaching, the interrupt logic unit 363 sends its instruction
SYNC as a 4-bit vector
H INT Send to IEU 104 via INFO line 341
That was previously determined to be the source of the synchronous exception in the
If there is an order, it will be notified of the order. IEU 104 is
Do not immediately respond, all instructions in the instruction set
Be scheduled in the usual way. Integer arithmetic
Other exceptions, such as arithmetic exceptions, are raised at runtime
There are cases. Exceptions caused by execution of privileged instructions
At this point, exceptions that depend on the current state of the machine
And the state of the machine is
PS to be up to date for all instructions
All instructions that may affect R (special migration
Action or return from a trap instruction)
Executed within The source of some synchronization instructions
An exception occurred only when the instruction was about to be evacuated
Is notified to the interrupt logic unit 363.

The IEU 104 is executed on a trial basis, saving all instructions that appear in the instruction stream preceding the first instruction that caused a synchronization exception, and executing on a trial basis, instructions appearing later in the instruction stream. Flush trial results from. Since the particular instruction that caused the exception is usually re-executed upon return from the trap, this instruction is also flushed. After that, the IF in the execution PC control unit 366 The PC is updated to correspond to the last instruction actually saved, and the exception is notified to the interrupt control unit 363.

When the instruction which is the source of the exception is saved,
The IEU 104 uses a new 4-bit vector to indicate which instruction caused the synchronous exception, if any, in the saved instruction set (register 224), which caused the first exception in the instruction set. SYNCH with information indicating the source IN
T Return to the interrupt logic unit 363 via INFO line 341. The information contained in the 4-bit exception vector returned from IEU 104 is an accumulation of the 4-bit exception vector passed from interrupt logic unit 363 to IEU 104 and the exceptions raised in IEU 104. If there is information already stored in the interrupt control unit 363 due to an exception detected during prefetch or I-decoding, the rest of the information returned from the IEU 104 to the interrupt control unit 363 along with that information is the interrupt It is sufficient for the control unit 363 to determine the content of the highest priority synchronization exception and its trap number. 4) Handler dispatch and return: After the interrupt acknowledgment signal is received from the IEU via line 340 or a non-zero exception vector is received via line 341, the current DPC is the special register as the return address.
412 (FIG. 4), which is temporarily stored in the xPC register. The current processor status register (PSR) is the previous PSR
The (PPSR) register is also stored, and the current state comparison register (CSR) is saved in the old state comparison register (PCSR) in the special register 412.

The address of the trap handler is calculated as the trap base register address plus an offset. PC logic unit 270 has two base registers for traps, both of which are part of special register 412 (FIG. 4) and are initialized by a previously executed special move instruction. For most traps, the base register used to calculate the address of the handler is the trap base register TB
R.

[0091] The interrupt control unit 363 is the
Determine high priority interrupts or exceptions and look-up
Table to determine the trap number associated with it.
to decide. This is the off-state to the selected base register.
One set of INT as a set Via OFFSET line 373
Is transferred to the prefetch PC control unit 364. Vect
Address uses the offset bit as the lower bit.
Only by concatenating with the upper bits obtained from the TBR register.
There is an advantage that it can be. Therefore, the adder delay
Is prevented. (In this specification, the 2 'bit is the i'th bit
It is a thing. ) For example, if the trap number is 0
If this is represented by an 8-bit value up to 255, the handler
The dress is an 8-bit trap number with a 22-bit TBR
It is required to concatenate at the end of the value. 2 for the trap number
Adding a low-order bit to a digit causes the trap handler
The dress will always be on a word boundary. this
The concatenation handler address created in this way is input 373
Prefetch selector PF as one of PC Sel 390
(Fig. 4), selected as the next address, and
The instruction is prefetched from here. Uses TBR register
And all the trap vector handler addresses
One word away. Therefore, the trap handler
The instruction at the address is
Must be a preliminary branch instruction to the chin. Only
And traps can degrade system performance.
How many things need to be handled with care to prevent
There is. For example, TLB traps need to run fast
There is. For that reason, in the preferred embodiment, the preliminary
Small trap hand without paying for the branch
A fast trap mechanism that allows you to call
It has been incorporated. In addition, the fast trap handler
Independently located in memory, for example, in on-chip ROM
The location of the ROM
Eliminates memory system problems associated with

In the preferred embodiment, the only fast traps are the VMU exceptions described above. Fast trap numbers are distinguished from other traps and range from 0-7. However, the priority is the same as the MMU exception. If the interrupt control unit 363 finds that the fast trap is the highest priority then pending, it selects the fast trap base register (FTB) from the special register (FTB) and combines it with the trap offset. Send on line 416. Prefetch selector PF via line 373 ' PC S
The resulting vector address sent to el 390 is the concatenation of the high-order 22 bits from the FTB register, followed by the three bits representing the fast trap number, followed by seven zero bits. in the process of. Thus, each fast trap address is 128 bytes or 32 words apart. When called, the processor branches to the start word and causes the program to execute in the block or branch out of it. The execution of small programs, such as standard TLB processing routines that can be implemented with 32 or fewer instructions, is faster than a normal trap because the preliminary branch to the actual execution routine is avoided. You.

In the preferred embodiment, all instructions are the same four bytes long (ie, occupy four address locations), but it should be noted that even in microprocessors where instructions are of variable length. A fast trap mechanism is available. In this case, between the fast trap vector addresses, at least two shortest instructions available to the microprocessor, preferably at least
Of course, enough space is provided to accept the 32 average size instructions. Of course, if the microprocessor has a return from trap instruction, there must be enough space between the vector addresses to place at least one other instruction in the handler at that instruction. is there.

When dispatching to the trap handler, the processor enters a kernel mode and an interrupt state. In parallel, a copy of the status compare register (CSR) is placed in the previous carry status register (PCSR) and the PSR
Is stored in the previous PSR (PPSR). The kernel and interrupt status modes are represented by bits in the processor status register (PSR). When the interrupt status bit of the current PSR is set, the shadow or trap registers RT [24] -RT [31] become visible as described above and as shown in FIG. 7 (b). The interrupt handler can only exit the kernel mode by writing the new mode to the PSR, but the only way to exit the interrupt state is to execute a return from trap (RTT) instruction.

When IEU 104 executes the RTT instruction, PCSR becomes
The interrupt status bits in the PSR are automatically cleared because the CSR register is restored and the PPSR register is restored to the PSR register. PF The PC SEL selector 390 selects the special register xPC in the special register set 412 as the next address to prefetch from. The xPC is restored to MBUF PFnPC or EBUF PFnPC, as appropriate, via incrementer 394 and bus 396. xP
The decision whether to restore C to EBUF PFnPC or to MBUF PFnPC is made according to the “procedure in progress” bit of the restored PSR.

It should be noted that the processor does not use the same special register xPC to store the return address for both trap and procedure instructions. The return address of the trap is stored in the special register xPC as described above, but the destination address after the procedure instruction returns to another special register uPC.
Stored in Thus, the interrupt state remains available while the processor is executing the emulation stream called with procedural instructions. On the other hand, the exception handling routine
It must not contain any procedure instructions because there is no special register to store the address to return to the exception handler after the stream has completed. 5) Nest: Certain processor status information is automatically dispatched to trap handlers, especially CSR, PSR, return PC, and in some sense, "A" register sets re [24] -re [31]. Is backed up, but other context information is not protected. For example, the contents of the floating-point status register (FSR) are not automatically backed up. In order for the trap handler to change these registers, it must perform its own backup.

Nesting of traps is not performed automatically because of the limited backups that are performed automatically when dispatching to a trap handler. The trap handler must back up necessary registers, clear interrupt conditions, read information required for trap processing from the system registers, and process the information appropriately. Interrupts are automatically disabled when dispatched to a trap handler. When done, the handler can restore the backed up registers, enable interrupts again, and execute the RTT instruction to return from the interrupt.

To enable nested traps,
The trap handler needs to be split into a first part and a second part. In the first part, while interrupts are disabled, copy the xPC using a special register move instruction,
It must be pushed onto the stack maintained by the trap handler. Then, using a special register move instruction, move the first address of the second part of the trap handler to the xPC, and return from the trap instruction (RTT).
Need to be run. RTT removes the interrupt status (P
Control is transferred to the address in the xPC by restoring the RSR to the PSR. The xPC contains the address of the second part of the handler. The second part can enable interrupts at this point and continue processing the exception in interrupt enabled mode. Noteworthy is the shadow register RT [24]
~ RT [31] is visible only in the first part of this handler, not in the second part. Thus, in the second part, the handler needs to reserve the value of the "A" register if the value could be changed by the handler. When the trap processing routine is finished, restore all the backed up registers and pop the original xPC from the trap handler stap,
It needs to be returned to the xPC special register using a move special register instruction and another RTT performed. This returns control to the corresponding instruction in the main or emulation instruction stream. 6) Trap list: Table I below shows the trap numbers, priorities and processing modes of the traps recognized in the preferred embodiment.

Table I @Trap number processing mode Synchronous trap name 0-127 Normal Synchronous Trap Instruction 128 Normal Synchronous FP Exception 129 Normal Synchronous Integer Arithmetic Exception 130 Normal Synchronous MMU (Excluding TLB Mismatch or Correction) 135 Normal Synchronous Unaligned Memory Address 136 Normal Synchronous Illegal Instruction 137 Normal Synchronous Privileged Instruction 138 Normal Synchronous Debug Exception 144 Normal Asynchronous Performance Monitor 145 Normal Asynchronous Timer / Counter 146 Normal Asynchronous Memory I / O Error 160-191 Normal Asynchronous Hardware Interrupt 192-253 Reserved 254 Normal Asynchronous Machine Check 255 Normal Asynchronous NMI 0 High Speed Trap Synchronous High Speed MMU TLB Mismatch 1 High Speed Trap High-speed MMU TLB correction 2-3 High-speed trap synchronization High-speed (reserved) 4-7 High-speed trap synchronization High-speed (reserved) ────────────────────────── III. Instruction Execution Unit FIG. 5 shows a control path portion and a data path portion of the IEU 104. The primary data path starts with the instruction / operand data bus from IFU 102. As a data bus, the immediate operand is sent to the operand alignment unit 470, and the register file (REG ARRA
Y) passed to 472. Register data is sent from register file 472 through bypass unit 474, through register file output bus 476, and through distribution bus 480 to a parallel array of functional computing elements (FUo-n). The data generated by functional unit 478o-n
Returned via output bus 482 to bypass unit 474 and / or register array 472 or both.

Load / Store Unit 484 by IE
The data path part of U104 is completed. The load / store unit 484 is responsible for managing data transfer between the IEU 104 and the CCU 106. Specifically, the load data retrieved from the data cache 134 of the CCU 106 is loaded by the load / store unit 484 onto the load data bus 486.
Is transferred to the register array 472 via The data stored in the data cache of the CCU 106 is received from the functional unit distribution bus 480. In the preferred embodiment of the present invention, where the control path portion of the IEU 104 is responsible for sending, managing, and processing information along the IEU data path, the IEU control path has the function of managing the parallel execution of multiple instructions. In addition, the IEU data path has the function of independently performing multiple data transfers between almost all data path elements of the IEU 104. When the IEU control path receives an instruction via the instruction / operand bus 124, it operates accordingly. Specifically, the instruction set is received by E-decode unit 490. In the preferred embodiment of the present invention, the E decode unit 490 receives and decodes both instruction sets held in IFIFO master registers 216, 224. The results of decoding of all eight instructions are the carry checker (CRY CHKR) unit 492, the dependency checker (DEP CHKR) unit 494, the register rename unit (REG RENAME) 496, and the instruction issue (ISSUEUR) unit 49.
8 and the evacuation control unit (RETIRE CLT) 500.

The carry checker unit 492 receives the signal from the E decode unit 490 via the control line 502,
Receive decoding information for the pending 8 pending instructions. The function of the carry checker 492 is to identify the pending instructions that affect the carry bit of the processor status word or are dependent on the state of the carry bit. This control information is sent to the instruction issuing unit 498 via the control line 504.
Sent to

Decoding information indicating the registers in the register file 472 used by the eight pending instructions is sent directly to the register rename unit 496 via control line 506. This information is also sent to the dependency checker unit 494. The function of the dependency checker unit 494 determines which pending instructions refer to a register as a data destination, and if so, which instructions depend on one of these destination registers. That is. Register dependent instructions are identified by control signals sent to register rename unit 496 via control line 508.

Finally, the E decode unit 490 sends control information identifying the specific contents and function of each of the eight pending instructions via the control line 510 to the instruction issuing unit 498.
Send to The instruction issuing unit 498 is responsible for determining data path resources, particularly which functional units are available for execution of pending instructions. According to a preferred embodiment of the architecture 100, the instruction issuing unit 498 executes any of the eight pending instructions out of order, subject to the availability of data path resources and constraints on carry and register dependencies. It can be so. The register renaming unit 496 sends the bit map of the appropriately unconstrained instruction to be executed to the instruction issuing unit 498 via control line 512. Instructions that have already been executed (completed) and instructions that depend on registers or carry are logically removed from the bit map.

[0104] Depending on whether the required functional units 478o-n are available, the instruction issuing unit 498 can begin executing multiple instructions each system clock cycle. The status of functional units 478o-n is sent to instruction issue unit 498 via status bus 514. Control signals for starting the execution of the instruction and for managing the execution after the start are sent from the instruction issuing unit 498 to the register renaming unit 496 via the control line 516, and optionally to the functional units 478o-n. Can be When receiving the control signal,
Register renaming unit 496 sends a register select signal on register file access control bus 518. Which register is enabled by the control signal sent on bus 518 is determined by selecting the instruction being executed and by register renaming unit 496 determining the register referenced by that particular instruction. Is done.

The bypass control unit (BYPASS CTL) 520
Generally controls the operation of bypass data routing unit 474 through control signals on control line 524. Bypass control unit 520 is functional unit 47
8o-n should be monitored and data sent from register file 472 to functional units 478o-n in connection with register references sent from register rename unit 496 via control line 522? Whether or not, the data output from the functional unit 478o-n can be immediately sent to the functional unit destination bus 480 via the bypass unit 474 and used for execution of the newly issued instruction selected by the instruction issuing unit 498. Determine whether or not. In either case, instruction issue unit 498 is replaced by functional unit 47
By selectively making special register data available to each of the 8o-n, the functional unit
Directly control sending data to 478o-n.

The remaining units on the IEU control path include an evacuation control unit 500 and a control flow control (CF CTL) unit 52.
8 and a completion control (DONE CTL) unit 536. The evacuation control unit 500 operates to invalidate or confirm execution of instructions executed out of order. If an instruction is executed out of order, and all preceding instructions have been saved,
The instruction can be confirmed or evacuated. When the identification information indicating which of the eight pending instructions in the current set has been executed is sent out on the control line 532, the evacuation control unit 500 causes the evacuation control unit 500 to output the information on the control line 534 connected to the bus 518 based on the identification information. To effectively check the result data stored in the register array 472 as a result of the preceding execution of the instruction executed out of order.

The save control unit 500 sends a PC increment / size control signal to the IFU 102 via the control line 344 when saving each instruction. Since multiple instructions can be executed out of order, and thus can be placed in a ready state to be saved simultaneously, the save control unit 500 determines the size value based on the number of instructions saved simultaneously. Finally, IF
All instructions in IFO master register 224 are executed,
If so, the evacuation control unit 500 sends an IFIFO read control signal to the IFU 102 via the control line 342 to initiate the shift operation of the IFIFO unit 264, thereby adding to the E-decoding unit 490. Four instructions are given as execution pending instructions.

Control flow control unit 528 detects the logical branch result of each conditional branch instruction.
Has specialized functions. Control flow control unit 528 receives the 8-bit vector ID of the currently pending conditional branch instruction from E-decode unit 490 via control line 510. An 8-bit vector instruction completion control signal is similarly received from completion control unit 540 via control line 538. The completion control signal allows control flow control unit 528 to determine when a conditional branch instruction has completed enough to determine a conditional control flow situation. The control flow status result of the pending conditional branch instruction is stored by control flow control unit 528 during its execution. The data required to determine the result of the conditional control flow instruction is obtained via a control line 520 from a temporary status register in register array 472.
As each conditional control flow instruction is executed, the control flow control unit sends a new control flow result signal to the control line.
Send to IFU 102 via 348. In the preferred embodiment, the control flow result signal includes two 8-bit vectors, which are the status results for each of the eight potentially pending control flow instructions by bit position. Are defined, and the corresponding status result states obtained by the bit position mapping.

Finally, the completion control unit 540 is for monitoring the execution status of each operation of the functional units 478o-n. When any of the functional units 478o-n signals the completion of the instruction execution operation,
Completion control unit 540 sends a corresponding completion control signal on control line 542 to alert the register renaming unit 496, instruction issuing unit 498, save control unit 500 and bypass control unit 520.

By making the functional units 478o-n in a parallel array configuration, the control consistency of the IEU 104 is improved.
In order to correctly recognize and schedule instructions for execution, it is necessary to inform the instruction issuing unit 498 of the characteristics of the individual functional units 478o-n. Functional unit 478o
-n is responsible for determining and performing the specific control flow operations needed to perform the required function. Therefore, other than the instruction issuing unit 498, the IEU control unit does not need to be independently informed of the control flow processing of the instruction. Instruction issuing unit 498 and functional unit 47
8o-n will jointly work with the remaining control flow management unit 496,
The functions to be performed by the 500, 520, 528, and 540 are indicated by prompts for necessary control signals. Therefore, the function unit 47
8o-n specific control flow operation changes can be
Does not affect control operations of U104. Furthermore, when enhancing the functions of the existing functional unit 478o-n, the extended-precision floating-point multiplication unit and the extended-precision floating-point ALU
Even if one or more additional functional units 478o-n, such as a fast Fourier calculation function unit and a trigonometric function calculation unit, are added, only the instruction issue unit 498 needs to be slightly changed. To make the necessary changes, it is necessary to recognize a particular instruction based on the corresponding instruction field isolated by the E-decode unit 490 and associate that instruction with the required functional unit 478o-n. . Control of register data selection, data routing, instruction completion and retraction are now consistent with the processing of all other instructions executed on all other functional units of functional unit 478o-n. I have. A) IEU Datapath Details The central element of the IEU datapath is the register file 472. However, according to the present invention, there are several parallel data paths in the IEU data path that are optimized for individual functions. There are two main data paths, integer and floating point. Within each parallel data path,
A portion of register file 472 is adapted to support data operations performed within its data path. 1) Details of the register file FIG. 6A is a schematic diagram of a preferred architecture of the data path register file 550. The data path register file 550 includes a temporary buffer 552, a register file array 564, an input selector 559, and an output selector 55.
Contains 6 The data ultimately sent to register array 564 is typically received first by temporary buffer 552 via integrated data input bus 558 '.
That is, all data sent to the datapath register file 550 is multiplexed by the input selector 559 and sent out the input buses 55 (preferably two) onto the input bus 558 '. The register select and enable control signals sent out on control bus 518 are
Select the register location of the received data in 2. When the instruction that generated the data to be stored in the temporary buffer is saved, the control signal sent out on the control bus 518 is transferred from the temporary buffer 552 to the register file array 56 again.
Data bus to logically associated registers in 4
Allow transfer of data via 560. However, before the instruction is saved, the data stored in the temporary buffer 552 transfers the data stored in the temporary buffer to the output data via the bypass portion of the data bus 560.
By sending the instruction to the selector 556, it can be used at the time of executing the subsequent instruction. Selector 556, controlled by a control signal sent via control bus 518, selects between data from registers in temporary buffer 552 and data from registers in register file array 564. The resulting data is sent out on register file output bus 564. If the instruction being executed is saved upon completion, that is, if the instruction is executed in order, the result data should be sent directly to the register array 554 via the bypass extension 558 ". Can be instructed.

In accordance with the preferred embodiment of the present invention, each datapath register file 550 is capable of performing two register operations simultaneously. Thus, two full register width data values can be written to temporary buffer 552 via input bus 558. Internally, the temporary buffer 552
Is arranged in a multiplexer array, so that input data can be sent to any two registers in the temporary buffer 552 at the same time. Similarly, any five registers of temporary buffer 552 can be selected by the internal multiplexer to output data on bus 560. Since the register file array 564 also has an input / output multiplexer, two registers can be selected to receive their data simultaneously from the bus 560, or five registers can be selected via the bus 562. You can also send it. Finally,
The register file output selector 556 is connected to buses 560 and 56
Preferably, any five of the ten register data values received from 2 are output simultaneously on register file output bus 564.

The register set in the temporary buffer is shown in FIG.
(B) shows the outline. Register set 55
2 'is 8 single word (32 bits) register I0R
D, I1RD ... I7RD. Register set 552 'consists of four double word registers I0RD, I0RD + 1
(I0RD4), I1RD, I1RD + 1 (ISRD) ... I3RD, I3RD + 1 (I7RD)
Can also be used as a set.

According to a preferred embodiment of the present invention, the register
Instead of duplicating each register in the file array 564, registers in the temporary buffer register set 552 are renamed based on the relative location of each instruction in the two IFIFO master registers 216, 224. Referenced by unit 496. Book architecture
Each instruction implemented at 100 can refer to up to two registers or one double word register as an output to destination data generated by execution of the instruction. Typically, the instruction references only one output register. Therefore, as shown in FIG. 6C, in the case of the instruction 2 (I ₂ ) which refers to one output register among the eight pending instructions, the data destination register I2RD is selected. Accept the data generated by the execution of the instruction. Instruction data generated by the instruction I ₂ is followed, for example, when used by the I _5, data stored in I2RD register is transferred via the bus 560, the resulting data is sent back to the temporary buffer 552 And stored in the register indicated by I5RD. In particular, since instruction I ₅ is determined by the instruction I _2, instruction I ₅ is, I ₂
It cannot be executed until the result data from is obtained. However, as will be appreciated, the instruction I ₅ is to lump the input data required from the data location of the instruction I ₂ of the temporary buffer 552 'can be performed before saving instruction I ₂ .

[0114] Finally, the instruction I ₂ is retracted, the register
The data from the I2RD is written to the register location in the register file array 564, judging from the logical position of the instruction at the save location. That is, the evacuation control unit 560 is connected to the E decode unit via the control line 510.
Determine the address of the destination register in the register file array from the register reference field data provided from 490. When the instruction I _0-3 is retracted, the values contained in I4RD-I7RD is shifted concurrently with the shift of the IFIFO unit 264 is transferred to I0RD-I3RD.

[0115] If a double word result value is obtained from the instruction I ₂ is further complicated. According to a preferred embodiment of the present invention, a combination of location I2RD and I6RD is either the instruction I ₂ is retracted, or otherwise until canceled, is used to keep stores the result data from the instruction .
In the preferred embodiment, execution of instruction _{I4 + 7} is suspended if a reference to the double word output by any of instructions I0-3 is detected by register rename unit 496.
This allows the entire temporary buffer 552 'to be double-word
It can be used as a single rank of registers. When instructions I _{0 -3} are saved, the temporary buffer 552 'can be used again as two ranks of a single word register. In addition, the execution of any instruction I _{4 + 7} will require a double word output register if
Hold until the instruction is shifted to the corresponding I _0-3 .

The logical organization of the register file array 564 is shown in FIGS. 7 (a) and 7 (b). According to a preferred embodiment of the present invention, the register file array 564 for the integer data path is comprised of 40 32-bit wide registers. This register set is register set "A"
From the top set consisting of the base register set re [0..23] 565, general-purpose register re [24..31] 566, and eight general-purpose trap registers re [24..31]. Organized as a shadow register set. In normal operation, general-purpose register re [0..31] 565,
566 comprises the active "A" register set of the register file array for the integer data path.

As shown in FIG. 7B, if the trap register re [24..31] 567 is moved to the swapped active register set "A", the register re [0..23] 56
It is possible to access 5 active base sets together. This configuration of the "A" register set is selected upon receipt of an interrupt or execution of an exception trap handling routine. This state of register set "A" is maintained until it explicitly returns to the state shown in FIG. 7 (a) by executing an interrupt enable instruction or executing a return instruction from a trap.

In the preferred embodiment of the present invention implemented by architecture 100, the floating point data path is an extended precision register file array as outlined in FIG.
Use 572. The register file array 572 includes 32 registers rf [0..31] 5 each having a 64-bit width. The floating-point register file 572 can be logically referred to as the "B" set of the integer register rb [0..31] 5. In architecture 100, this "B" set of registers corresponds to the lower 32 bits of each of the floating point registers rf [0..31].

To represent the third data path, a Boolean operator register set 574 is provided as shown in FIG. It stores the logical result of a Boolean operation. This "C" register set 574 consists of 32 1-bit
It consists of registers rc [0..31]. The operation of Boolean register set 574 is unique in that the result of the Boolean operation can be sent to any instruction select register of Boolean register set 574. This is in contrast to using a single processor status word register that stores one bit flags that represent conditions such as equal, unequal, greater, and other simple Boolean status values.

Both the floating point register set 572 and the Boolean register set 574 are complemented by a temporary buffer of the same architecture as the integer temporary buffer 552 shown in FIG. The basic difference is that the width of the temporary buffer register is defined to be the same as the width of the complemented register file arrays 572,574. In the preferred embodiment, the widths are 64 bits and 1 bit, respectively.

A number of additional special registers are at least logically present in the register array 472. FIG. 7 (c)
As shown in the figure, the registers physically present in the register array 472 are the kernel stack pointer (Kernel stack pointer).
pointer) 568, a processor status register (PSR) 569, an old processor status register (PPSR) 570, and an array (tPSR [0..7]) 571 of eight temporary processor status registers. The remaining special registers are distributed throughout the architecture 100. Special address and data bus 354
Is for selecting data and transferring it between special registers and the "A" and "B" register sets. The special register move instruction selects a register from the "A" or "B" register set, selects the transfer direction, and specifies the address ID of the special register.

The kernel stack pointer register and the processor status register are different from other special registers. The kernel stack pointer, when in kernel state, is accessible by executing standard inter-register move instructions. The temporary processor status register cannot be accessed directly. Instead, the register array is used to implement an inheritance mechanism that propagates the value of the processor state register and makes it available to instructions executed out of order. The initial propagation value is the value of the processor status register. That is, the value obtained from the last saved instruction. This initial value is propagated omni-directionally from the temporary processor status register to allow instructions executed out of order to access the value in the temporary processor status register at the corresponding location. The condition code bits on which an instruction depends and which can be changed are defined by the characteristics of the instruction. Register dependency checker unit 494 and carry dependency checker 492 indicate that the instruction is not constrained by dependencies, registers or condition codes.
The instructions can be executed out of order if determined by. Changes in the condition code bits of the processor status register are indicated in the logically corresponding temporary processor status register. In particular, only bits that may change are applied to the value in the temporary processor status register and propagated to all higher order temporary processor status registers. As a result, all instructions executed out of order are executed from the processor state register values appropriately modified by the intervening PSR modification instructions. When an instruction is evacuated, only the corresponding temporary processor state register value is transferred to PSR register 569. Other special registers are described in Table II.

Table II { Special Register Special Move Register R / W Description PCR Program Counter: Generally, the PC stores the next address of the currently executing program instruction stream. IF PC R / W IFU program counter: IF The PC stores the exact next execution address. PFnPC R Prefetch Program Counter: MBUF, TBUF and EBUF PFnPC stores the next prefetch instruction address of each prefetch instruction stream. uPC R / W Micro program counter: Stores the address of the instruction following the procedure instruction. This is the address of the first instruction to be executed when the procedure instruction returns. xPC R / W Interrupt / Exception Program Counter: Stores the interrupt or exception (or both) return addresses. The return address is the IF at the time of the trap PC address. TBR W Trap Base Address: Base address of the vector table used when dispatching to trap processing routines. Each entry is one word long. The trap number given from the interrupt logic unit 363 is used as an index to the table pointed to by this address. FTB W Fast Trap Base Register: Base register for immediate trap handling routine table. Each table entry is 32 words and is used to execute trap processing routines directly. The value obtained by multiplying the trap number given by the interrupt logic unit 363 by 32 is used as an offset to the table pointed to by this address. PBR W Procedure Base Register: Base address of the vector table used when dispatching to procedure routines. Each entry is one word long and is aligned on a four word boundary. The procedure number given as the procedure instruction field is used as an index to the table pointed to by this address. PSR R / W Processor Status Register: Stores the processor status word. Status data bits include carry, overflow, zero, negative, processor mode, current interrupt level, running procedure routine, divide by zero, overflow exception, hardware function interrupt enabled, and procedure interrupt enabled. There are bits that can be interrupted. PPSR R / W Old Processor Status Register: Loaded from PSR when the instruction completes successfully or an interrupt or trap is triggered. CSR R / W State Compare (Boolean) Register: A set of Boolean registers accessible as a single word. PCSR R / W Old State Compare Register: Loaded from the CSR when the instruction completes successfully or an interrupt or trap is triggered. 2) Details of Integer Data Path The integer data path of IEU 104 configured according to the preferred embodiment of the present invention is shown in FIG. For purposes of explanation, a number of control paths connected to integer data path 580 are not shown. These connection relationships are as described with reference to FIG.

The input data on the data path 580 is obtained from the alignment units 582, 584 and the integer load / store unit 586. The integer immediate data value is initially provided as an instruction embedded data field and is obtained from the operand unit 470 via bus 588. Alignment unit 582 isolates the integer data value and sends the resulting value to multiplexer 592 via output bus 590. Another input to multiplexer 592 is a special register address and data bus 35
4

The immediate value (immedia) obtained from the instruction stream
te) Operands are also available from operand unit 570 via data bus 594. These values are
Before being sent out on 596, it is right justified again by the alignment unit 584.

Integer load / store unit 586 interacts with CCU 106 via external data bus 598 in both directions. Inbound data to IEU 104 is transferred from integer load / store unit 586 to input latch 602 via input data bus 600. Multiplexer 59
2 and the output data from latch 602
8 multiplexer input buses 604,606. Data from the functional unit output bus 482 'is also sent to the multiplexer 608. The multiplexer 608, in the preferred embodiment of the architecture 100, has two paths to send data to the output multiplexer bus 610 simultaneously. In addition, the data transfer through multiplexer 608 is
Can be completed within each half cycle of the system clock. Most instructions implemented in the present architecture 100 utilize a single destination register so that up to four instructions can send data to the temporary buffer 612 during each system clock cycle.

The data from the temporary buffer 612 is sent to the integer register file array 614 via the temporary register output bus 616, or an alternative temporary buffer register bus.
It can be forwarded to output multiplexer 620 via 618. Integer register array output bus 622 can transfer integer register data to multiplexer 620. Temporary buffer 612 and integer register file array 61
The output bus connected to 4 allows each of the five register values to be output simultaneously. That is, two instructions referring to a total of up to five source registers can be issued simultaneously. Temporary buffer 612, register file array 614, and multiplexer 620 allow for the transfer of outbound register data to occur every half system clock cycle. Thus, up to four integer and floating point instructions can be issued during each clock cycle.

Multiplexer 620 converts outbound register data values from register file array 614 to
Alternatively, it serves to select directly from the temporary buffer 612. This allows the IEU 104 to execute out-of-order execution instructions that depend on previously executed out-of-order instructions. This maximizes the execution throughput capability of the IEU integer data path by executing pending instructions out of order and accurately reconstructs out-of-order data results from data results from executed and evacuated instructions. The two goals of separation can be easily achieved. When an interrupt or other exceptional condition occurs that requires the correct state of the machine to be restored, the present invention allows the data values present in temporary buffer 612 to be easily cleared. Thus, register file array 614 has completed prior to the occurrence of an interrupt or other exceptional condition, and remains accurately populated with data values obtained only by execution of the saved instruction.

During each half-system cycle operation of multiplexer 620, up to five selected register data values are sent to integer bypass unit 626 via multiplexer output bus 624. This bypass unit 626 basically consists of a parallel arrangement of multiplexers, which can send data appearing at any of its inputs to any of its outputs. The input of bypass unit 626 is connected to the output bus from multiplexer 592.
Special register addressing data value or immediate integer value via 604, up to 5 register data values sent out on bus 624, load from integer load / store unit 586 via double integer bus 600 It consists of operand data, its immediate Oberland value obtained from the alignment unit 584 via its output bus 596, and finally the bypass data path from the functional unit output bus 482. This bypass path and data bus 482 can simultaneously transfer four register values every system clock cycle.

Data is passed from the bypass unit 626 to the integer bypass bus 62 connected to the floating point data bus.
8 Two operand data buses output on and capable of simultaneously transferring up to five register data values and a store data bus used to send data to the integer load / store unit 586. Sent to data bus 632.

The functional unit distribution bus 480 is implemented through the operation of the router unit 634. Router unit 634 also receives 5
This is realized by a parallel multiplexer arrangement which allows the sending of register values to functional units provided in the integer data path. Specifically, the router unit 63
4 is the five register data values sent from the bypass unit 626 via the bus 630, and the address bus
Current IF sent via 352 A PC address value, determined by the PC control unit 362, receives the control flow offset value sent out on line 378 '. Router
Unit 634 may also receive, via data bus 636, operand data values retrieved from a bypass unit provided in the floating point data path (optional).

The register data values received by the router unit 634 are transferred over the special register address and data bus 354 to the functional units 640,
Sent to 642, 644. Specifically, router unit 6
34 transfers up to three register operand values via the router output buses 646, 648, 640 to the functional unit 640.
, 642, and 644. According to the general architecture of the present architecture 100, up to two instructions may be simultaneously executed by the functional units 640, 642, 644.
Is possible. According to a preferred embodiment of the present invention, the three dedicated integer functional units can each have a programmable shift function and two arithmetic logic unit functions.

ALU0 function unit 644, ALU1 function unit
642 and shifter functional unit 640 send their respective output registers / outputs onto functional unit bus 482 '.
The output data from ALU0 and shifter function units 644, 640 is also sent on a shared integer function unit bus 650 connected to the floating point data path. A similar floating point functional unit output value data bus 652 is provided from the floating point data path to the functional unit output bus 482 '.

ALU0 functional unit 644 is also used to generate virtual address values to support both IFU 102 prefetch operations and integer load / store unit 586 data operations. The virtual address value calculated by the ALU0 functional unit 644 is sent out on an output bus 654 connected to both the target address bus 346 of the IFU 102 and the CCU 106, and the physical address of the execution unit
(EX PADDR) is obtained. Latch 646 is for storing the virtualized portion of the address generated by ALU0 functional unit 644. This virtualized portion of the address is sent out on output bus 658 and sent to VMU 108. 3) Details of the floating-point data path Next, FIG. 11 shows the floating-point data path. The initial data is again the immediate integer operand
Received from multiple sources, including bus 588, immediate operand bus 594, and special register address data bus 354. The ultimate source of external data is a floating point load / store unit 622 connected to CCU 106 via external data bus 598.

The immediate integer operand is received by the alignment unit 664, which serves to right justify the integer data field before passing to the multiplexer 666 via the alignment output data bus 668. Multiplexer 666 also receives special register address data bus 354. Immediate operand is the second alignment unit
Sent to 670, right justified and sent out on output bus 672. Inbound data from the floating point load / store unit 662 is received by the latch 674 from the load data bus 676. Data from multiplexer 666, latch 674, and functional unit data return bus 482 "is received from the input of multiplexer 678. Multiplexer 678 has a selectable data path and provides two register data values for the system clock. Every half cycle of the multiplexor buffer 680 via the multiplexer output bus 682.
It has the same register set as the temporary buffer 552 'shown in FIG. Temporary buffer 680 further reads up to five register data values from temporary buffer 680 and provides a floating point register file array 684 via data bus 686 and an output data bus 690.
To the output multiplexer 688. Multiplexer 688 also receives up to five register data values from floating point file array 684 via data bus 692 at the same time. Multiplexer 68
8 serves to select up to five register data values and simultaneously transfer them to the bypass unit 694 via the data bus 696. Bypass unit 694 is
The immediate value provided by the alignment unit 670 via the data bus 672, the output data bus 698 from the multiplexer 666, the load data bus 676 and the bypass extension of the functional unit data return bus 482 ". Operand value is also received.Bypass unit 694
Selects simultaneously up to five register operand data values to provide a bypass unit output bus 700, a store data bus 702 connected to a floating point load / store unit 662, and an integer data path 580. Floating-point bypass connected to router unit 634
Operates to output to bus 636.

The floating point router unit 704 includes a bypass unit output bus 700, an integer data path bypass bus 628, and respective functional units 712, 714, 716.
And a function for simultaneously selecting a data path between the function unit input buses 706, 708, and 710 connected to the function unit. Input bus 70 according to the preferred embodiment of architecture 100
6, 708, 710 are each capable of simultaneously transferring up to three register operand data values to each of the functional units 712, 714, 716. The output bus of these functional units 712, 714, 716
Data return bus 482 "is coupled to return data to register file input multiplexer 678. Integer data path functional unit output bus 650.
Can be provided to connect to the functional unit data return bus 482 ". According to the architecture 100 of the present invention, the multiplexer functional unit 712
ALU 714 functional unit output bus via floating point data path functional unit bus 652 via integer data path 500 functional unit data return bus
482 'can be connected. 4) Details of Boolean Register Data Path The Boolean data path 720 is shown in FIG. This data path 720 is basically used to support the execution of two types of instructions. The first type is an operand compare instruction, in which two operands selected from the set of integer registers and the set of floating-point registers or provided as immediate operands are converted to integers in one of the ALU functional units. And by subtracting the floating point data path. This comparison is
The subtraction is performed by one of the ALU functional units 642, 644, 714, 716, and the resulting sign and zero status bits are sent to the input selector and comparison operator combining unit 722. When unit 722 receives an instruction specifying a control signal from E-decode unit 490, it selects the output of ALU functional units 642, 644, 714, 716, combines the sign and zero bits, and sets the Boolean comparison result value. Is extracted. The result of the comparison operation can be simultaneously transferred to input multiplexer 726 and bypass unit 742 via output bus 723. As with the integer and floating point data paths, the bypass unit 742 is implemented as a parallel multiplexer array, and multiple data paths can be selected between the inputs of the bypass unit 742 to connect to multiple outputs. The other inputs of bypass unit 742 comprise a Boolean result return data bus 724 and two Boolean operands on data bus 744.
The bypass unit 742 converts Boolean operands representing up to two concurrently executing Boolean instructions to the Boolean operation unit 746 via the operand bus 748.
Can be transferred to Also, bypass unit 74
6 controls up to two single-bit Boolean operand bits (CF0, CF1).
0 and 752 can be transferred simultaneously.

The remainder of the Boolean data path includes an input multiplexer 726 that receives as input its comparison and Boolean result values output on comparison result bus 723 and Boolean result bus 724. This bus 724 muxes up to two Boolean result bits simultaneously.
726. Further, up to two comparison result bits are transferred to the multiplexer 72 via the bus 724.
6 can be forwarded. Multiplexer 726 can transfer any two signal bits appearing at the input of the multiplexer to the Boolean temporary buffer 728 at each half cycle of the system clock via the output of the multiplexer. Temporary buffer 728 is logically the same as temporary buffer 752 'shown in FIG. 6 (b), except for two important differences. The first difference is that each register entry in temporary buffer 728 is a single
Consists of bits. The second difference is that only one register is provided for each of the eight pending instruction slots. This is because the entire result of a Boolean operation is defined by one result bit by definition.

The temporary buffer 728 simultaneously outputs up to four output operand values. This allows two Boolean instructions, each requiring access to two source registers, to be executed simultaneously. The four Boolean register values are sent out on operand bus 736 at each half cycle of the system clock and multiplexer 73
8 or via the Boolean operand data bus 734 to the Boolean register file array 732. Boolean register file array 732
Is a single 32-bit wide data register, as logically shown in FIG. 9, and stores up to four single-bit locations in any combination.
8 and can be read from the Boolean register file array 732 and sent out on the output bus 740 every half cycle of the system clock. Multiplexer 738 sends any pair of Boolean operands received from its outputs on buses 736 and 740 onto operand output bus 744 for bypass unit 742.
Transfer to

The Boolean operation unit 746 has a function of performing a Boolean operation on two source values in a wide range. For compare instructions, the source value is a pair of operands from either the integer and floating-point register set and any immediate operands sent to the IEU 104; for Boolean instructions, the Boolean register operand Are any two of Tables III and IV show the logical comparison operations in the preferred embodiment of the architecture 100 of the present invention. Table V illustrates direct Boolean operations in a preferred embodiment of the architecture 100 of the present invention. table
The instruction condition codes and function codes shown in III-V represent the corresponding instruction segments. The instruction also specifies a pair of source operand registers and a destination Boolean register for storing the corresponding Boolean result.

Table III { Integer Comparison Instruction Conditions ^* Symbol Condition Code rs1 is Greater Than rs2> 0000 rs1 is greater than or equal to rs2> = 0001 rs1 is less than or equal to rs2 <0010 rs1 is less than or equal to rs2 <= 0011 rs1 is not equal to rs2 {0100 rs1 is equal to rs2 == 0101 Reserved 0110 unconditional 1111} ─────────────────────────── * rs = register source Table IV ─────────────── ────────────── compare instruction condition symbol condition code rs1 floating point atmospheric> 0000 rs1 is greater than or equal to rs2 than rs2> = 0001 rs1 is small <0010 rs1 than rs2 rs Less than or equal to <= 0011 rs1 is not equal to rs2 ≠ 0100 rs1 == 0101 unordered equals rs2? 1000 Unordered or rs1 greater than rs2? > 1001 unordered, rs1 is greater than or equal to rs2? > = 1010 unordered or rs1 less than rs2? <1011 unordered, rs1 is less than or equal to rs2? <= 1100 unordered or rs1 equals rs2? = 1101 Reserved 1110-1111 ─────────────────────────────── Table V ─────────── ───────────────── Boolean operation instruction operation * Symbol function code 0 Zero 0000 bs1 & bs2 AND 0001 bs1 & -bs2 ANN2 0010 bs1 bs1 0011 -bs1 & bs2 ANN1 0100 bs2 bs2 0101 bs1 ^- bs2 XOR 0110 bs1 bs2 OR 0111 -bs1 & -bs2 NOR 1000 -bs1 - bs2 XNOR 1001 -bs2 NOT2 1010 bs1 -bs2 ORN2 1011 -bs1 NOT1 1100 -bs1 bs2 ORN1 1101 -bs1 -bs2 NAND 1110 1 ONE 1111 ────── ─── ─────────────────── * bs = Boolean source register B) Load / store / control unit Figure 13 shows an example of load / store unit 760 It is. Although shown separately in data paths 580, 660, load / store units 586, 662 are preferably implemented as one shared load / store unit 760. The interfaces from the respective data paths 580, 660 are via address bus 762 and load and store data buses 764 (600, 676), 766 (632, 702).

The address used by the load / store unit 760 is a physical address, as opposed to the virtual address used in the IFU 102 and the rest of the IEU 104. IFU 102 runs on virtual IFU 102 and CCU 106
The IEU 104 generates a physical address, while the load / store unit 760
Must operate directly in physical address mode. This requirement is necessary if there are instructions that are executed out of order, causing the store operation to overlap the physical address data, and
This is to maintain data integrity if there is an out-of-order data return from CCU 106 to load / store unit 760. To maintain data integrity, load /
Store unit 760 buffers data from the store instruction until the store instruction is saved by IEU 104. As a result, the load / store unit 76
Only one store data buffered by zero can exist in the load / store unit 760. The execution of a load instruction that refers to the same physical address as the executed but not saved store instruction is delayed until the store instruction is actually saved. At that point, store data is loaded from the load / store unit 760 to the CCU 10
6 and can be immediately loaded back by performing a CCU data load operation.

Specifically, the entire physical address is UMU 108
From the load / store address bus 762. Load address is, in general, is stored in the load address register 768 _0-3. Store address is latched into store address registers 770 _3-0.
The load / store control unit 774 is an instruction issuing unit 49
Actuated in response to a control signal received from 8 to adjust the latching load addresses and store address registers 768 _3-0, 770 _3-0. Load / store control unit
774 sends a control signal to latch the load address on control line 778 and sends a control signal to latch the store address on control line 780. Store data is stored data register set 782
_The store address is latched at the same time as the store address is latched in the logically corresponding slot of _3-0 . 4x4x32 bit wide address comparator unit 772, load and store address registers 768 _3-0, each of the addresses contained in 770 _3-0 are force simultaneously. Performing a full matrix address comparison during each half cycle of the system clock
Load / store control unit 77 via control line 776
Controlled by four. The presence and logical location of the load address that matches the store address is sent to the load / store control unit 774 via control line 776.

If the load address is provided by the VMU 108 and there are no pending stores, the load address is read from the bus at the beginning of the CCU load operation.
762 bypasses directly to address selector 786. However, if store data is pending,
The load address is latched to the available load address latch 768 _0-3. Upon receiving a control signal from the save control unit 500 that the corresponding store data instruction is saved, the load / store control unit 774 initiates a CCU data transfer operation, and the CCU 10
Arbitrate access to 6. CCU 106 is ready
y), the load / store control unit 774
Instructs selector 786 to send the CU physical address onto CCU PADDR address bus 788. This address can be obtained from the store register 770 _3-0 corresponding via the address bus 790. Data from the corresponding store data register 782 _3-0 is sent out on the CCU data bus 792.

When a load instruction is issued from the instruction issuing unit 498, the load / store control unit 774 causes the load / store
One of the address latches 768 _3-0 allows to latch the requested load address. Particular latch 768 _0-3 selected corresponds logically to the position of the load instruction related instruction set. Instruction issue unit 498 passes to load / store control unit 774 a 5-bit vector indicating a load instruction in either of the two possibly pending instruction sets. If comparator 772 does not indicate a matching store address, the load address is sent to selector 786 via address bus 794 and output on CCU PADR address bus 788. The address is provided by the load / store control unit 774 and the CCU
This is done according to the CCU request and ready control signal exchanged between the 106. An execution ID value (ExID value) is also prepared by the load / store control unit 774 and issued to the CCU 106 to identify the load request when the CCU 106 subsequently returns request data including the ExID value. This ID value consists of 4-bit vector, which specifies the respective load address latch 768 _0-3 that issued the current load request unique bits. The fifth bit is used to identify the instruction set containing the load instruction. This ID value is therefore the same as the bit vector sent with the load request from the instruction issue unit 498.

The availability of the preceding request load data is indicated by the CCU 106 to the load / store control unit 77.
4, the load / store control unit 774
Allows the alignment unit to receive data and send it out on the load data bus 764. Alignment unit 798 serves to right justify the load data.

At the same time as the data is returned from CCU 106, load / store control unit 774 sends ExI from CCU 106.
Receive the D value. On the other hand, the load / store control unit 774
Sends a control signal indicating that the load data is sent out on the load data bus 764 to the instruction issuing unit 49.
8 and return a bit vector indicating for which load instruction the load data is returned. C) Details of the IEU Control Path Referring again to FIG. 5, the operation of the IEU control path will be described with reference to the timing diagram shown in FIG. The execution timing of the instruction shown in FIG. 14 is an example of the operation of the present invention, and it is needless to say that the execution timing can be changed to various modes.

The timing diagram of FIG. 14 shows the sequence of the processor system clock cycle _P0-6 . Each processor cycle begins with the internal T cycle T _0. In the architecture 100 according to the preferred embodiment of the present invention, each processor cycle consists of two T cycles.

In processor cycle 0, IFU 10
2 and VMU 108 operate to generate a physical address. This physical address is sent to the CCU 106, and an instruction cache access operation is started. If the requested instruction set is in the instruction cache 132, the instruction set is
Returned to 2. Thereafter, IFU 102 manages the transfer of the instruction set via prefetch unit 260 and IFIFO 264, and the transferred instruction set is first passed to IEU 104 for execution. 1) Details of E Decode Unit E decode unit 490 receives the entire instruction set in parallel and decodes before processor cycle 1 is completed. E-decode unit 490 is implemented in preferred architecture 100 as a logic block based on permutational combinatorial logic with the ability to directly decode all valid instructions received via bus 124 in parallel. The instructions recognized by architecture 100 are:
For each type, the instructions, register requirements, and required resource specifications are provided in Table VI.

Table VI { Instruction / Specification Instruction Control and Operand Information * Movement between registers Logical / arithmetic operation function code: Addition, subtraction, multiplication, shift, etc. Designation of destination register PSR only Source register 1 Source register 2 or immediate constant value Register set A / B selection Immediate value to register Destination register move Immediate integer or floating-point constant register set A / B selection Load / store register Operation function code: Specify load or store, use immediate, base and immediate, or use base and offset Source / destination register Base register Index register Register or immediate constant value Register set A / B selection Immediate call Signed immediate displacement control Control flow Operation function code: Specification of branch type and trigger condition Base register Index register, immediate constant displacement value, or trap number Register set A / B selection Special register move Operation function code: Special / integer register Transfer specification Special register / address identifier Source / destination register Register set A / B selection Integer conversion movement Operation function code: Specification of floating-point to integer conversion type Source / destination register Register set A / B selection Boolean function Boolean function code: Specification of AND, OR, etc. Destination Boolean register Source register 1 Source register 2 Register set A / B selection Extended procedure Procedure specifier: Address from procedure base value Specifying offset Operation: Passing a value to a procedure routine Atomic procedure Procedure specifier: Specifying an address value ─────────────────────────── * * -Instructions contain these fields in addition to the fields that are decoded to identify the instruction.

E-decode unit 490 decodes each instruction of the instruction set in parallel. Identification of the resulting instruction,
Instruction decode, register references and functional requirements are E-decoded
Obtained from the output of unit 490. This information is regenerated and E-decoded for each half-cycle of the processor cycle until all instructions in the
Latched by unit 490. Thus, information about all eight pending instructions is stored in the E decode unit.
It is constantly available from the 490 output. This information is represented in the form of an 8-element bit vector, with the bits or subfields of each vector logically corresponding to the physical location of the corresponding instruction in the two pending instruction sets. Accordingly, eight vectors are sent to carry checker 492 via control line 502. In this case, each vector specifies whether the corresponding instruction affects or depends on the carry bit of the processor status word. Eight vectors are sent via control line 510 to indicate the specific content and functional unit requirements of each instruction. Eight vectors are sent via control line 506, specifying the register references used by each of the eight pending instructions. These vectors are sent before the end of processor cycle 1. 2) Carry checker unit details Carry checker unit 492 operates in parallel with dependency check unit 494 during the data dependency phase of the operation shown in FIG. Carry checker unit 492 is implemented in preferred architecture 100 using logic based on permutational combinatorial logic. Thus, at each iteration of the operation by carry checker unit 492, all eight instructions are considered as to whether the instruction has changed the carry flag in the processor status register. This is needed because
This is to allow instructions that depend on the status of the carry bit set by the previous instruction to be executed out of order. The control signals issued on control line 504 allow carry checker unit 492 to identify a particular instruction that relies on the execution of the preceding instruction on the carry flag.

Further, carry checker unit 49
2 has a temporary copy of the carry bit for each of the eight pending instructions. For instructions that do not change the carry bit, carry checker unit 492 passes the carry bit to the next instruction in the order of the program instruction stream. Thus, it is possible to cause an instruction that is executed out of order to change the carry bit to be executed, and that subsequent instructions that depend on the instruction being executed out of order also execute instructions that change the carry bit. It can be executed even if it is placed after. In addition, the carry bit is the carry checker
Because the carry checker unit only needs to clear the internal temporary carry bit register when an exception occurs before these instructions are saved, as maintained by unit 492, it must be executed out of order. Becomes easier. As a result, the processor status register
Unaffected by execution of instructions executed out of order.
The temporary carry bit register maintained by carry checker unit 492 is updated as each instruction executed out of order is completed. When instructions executed out of order are saved, the carry bit corresponding to the last saved instruction in the program instruction stream is transferred to the carry bit location of the processor status register. 3) Details of the data dependency checker unit The data dependency checker unit 494
Eight register reference identification vectors are received from unit 490 via control line 506. Reference of each register is
A 5-bit value suitable for identifying 32 registers one at a time and a 2-bit value identifying a register bank located in an "A", "B" or Boolean register set It is shown. The floating point register set is also called the "B" register set. Each instruction is up to 3
It can have up to three register reference fields.
Two source register fields and one destination register field. Certain instructions, especially inter-register move instructions, may specify a destination register, but the instruction bit field recognized by the E-decode unit 490 has no output data actually created. May mean. Rather, execution of the instruction is only intended to determine a change in the value of the processor status register.

The data dependency checker 494 is also a pure combinational logic (pure co
mbinatorial logic), which simultaneously determines the dependency between the source register reference of an instruction that appears later in the program instruction stream and the destination register reference of the instruction that precedes it. Works.
The bit array is created by a data dependency checker 494 that identifies not only which instructions depend on other instructions, but also on which register each dependency originated. The dependency between carry and register data is determined immediately after the start of the second processor cycle. 4) Register Renaming Unit Details Register renaming unit 496 receives the IDs of the register references for all eight pending instructions via control line 506 and the register dependencies via control line 508. 8
Matrices from the individual elements are also received via control line 542. These elements indicate which instruction in the current set of pending instructions has been executed (completed). From this information, the register renaming unit 496 converts the 8-element array of control signals to the control line 512
To the instruction issuing unit 498 via The control information sent in this manner provides a register renaming unit 496 which of the currently pending instructions that have not been executed, when the data dependencies of the current set are determined, can be executed. Reflects the decisions made. The register renaming unit 496 sends a selection control signal identifying up to six instructions issued simultaneously for execution on line 51.
Receive via 6. That is, two integer instructions, two floating point instructions and two Boolean instructions.

The register renaming unit 496 has another function of selecting, via control signals sent to the register file array 472 via the bus 418, the source register to be accessed when executing the identified instruction. It has. The destination register of the out-of-order executed instruction is selected as being located in the temporary buffer 612, 680, 728 of the corresponding data path. Instructions executed in sequence are saved upon completion, and the resulting data is stored in register files 614, 684, 732. The choice of source register depends on whether the register was previously selected as the destination and the corresponding previous instruction has not yet been saved. In such a case, the source
The registers are selected from the corresponding temporary buffers 612, 680, 728. If the previous instruction has been saved, the corresponding register file 614, 684, 732 register is selected. As a result, the register renaming unit 496
For instructions that are executed out of order, it operates to effectively replace the reference to the register file register with the reference to the temporary buffer register.

According to the architecture 100, the temporary buffers 612, 680, 728 do not overlap with the register structure of the corresponding register file array. Rather, one destination register slot is provided for each of the eight pending instructions. As a result, the replacement of the temporary buffer destination register reference is determined by the location of the corresponding instruction in the pending register set. The source after that
The register reference is identified by the data dependency checker 494 for the instruction in which the source dependency occurred. Thus, the destination slot in the temporary buffer register can be easily determined by the register renaming unit 496. 5) Instruction issuing unit details The instruction issuing unit 498 sets the set of instructions that can be issued to the output of the register
Is determined based on the functional requirements of the instruction identified by. Instruction issuing unit 498 makes this determination based on the status of each of functional units 4780 _-n reported via control line 514. Therefore, the instruction issuing unit 498 registers the available instruction set to be issued in the register renaming unit 49.
Start operation when receiving from 6. Assuming that access to the register file is required to execute each instruction, instruction issuing unit 498 expects the functional units 4980 _-n currently executing the instruction to be available. To minimize the delay in determining which instruction to issue to register rename unit 496, instruction issue unit 498 is implemented with dedicated combinational logic.

[0155] When it is determined to be issued instruction, the register rename unit 496 initiates access to the register file, this access is continued until the third processor cycle P ₂ ends. If processor cycle P ₃ is started, the instruction issue unit 498 starts operation according to one or more functional units 478 ₀ -n as indicated by "Execute 0", the register file array 47
Receives and processes the source data sent from 2.

Typically, most instructions processed by architecture 100 are executed through functional units in one processor cycle. However, some instructions
As indicated by "Execute 1", multiple processor cycles are required to complete a simultaneously issued instruction.
The Execute 0 and Execute 1 instructions are, for example,
It can be executed by the ALU and the floating-point multiplication function unit. As shown in FIG.
Generates output data at the processor cycle, the output data just previously latched, it can be used to perform another instruction during the fifth processor cycle P _4. Preferably, the floating point multiplication function unit is an internal pipelined function unit. Thus, another floating point instruction can be issued in the next processor cycle. However, the result of the first instruction is not available for a data-dependent number of processor cycles.
The instruction shown in FIG. 14 requires three processor cycles to complete processing in a functional unit.

During each processor cycle, the function of instruction issue unit 498 is repeated. As a result, the status of the current pending instruction set and the availability of the entire set of functional units 4780 _-n is reevaluated during each processor cycle. Thus, under optimal conditions, the preferred architecture 100 can execute up to six instructions during a processor cycle. However, the total average number of executed instructions from a typical instruction mix is between 1.5 and 2.0 per processor cycle.

A final consideration in the function of the instruction issuing unit 498 is that it is involved in processing trap conditions and executing specific instructions. In order to generate a trap condition, all instructions that have not been
Must clear from IEU 104. Such a situation may be caused by receiving an external interrupt from either of the functional units 4780 _-n in response to an arithmetic error, or from the E-decode unit 490 when decoding an illegal instruction, for example, Occurs in response to being relayed to IEU 104 via request / acknowledgement control line 340. When a trap condition occurs, instruction issue unit 498 is responsible for aborting or invalidating all non-evacuated instructions currently pending in IEU 104. All instructions that cannot be saved at the same time are invalidated. This result is essential for accurately generating interrupts over conventional schemes of executing the program instruction stream in order. When IEU 104 is ready to begin executing the trap handler routine, instruction issue unit 498
Confirms receipt of the interrupt by the return control signal via control line 340. Also, in order to prevent the possibility of an exception condition for an instruction being recognized based on a changed program state bit before the execution of the instruction in a conventional purely in-order routine, the instruction issue unit 498 may Responsible for ensuring that all instructions that may change the PSR (such as special moves and returns from traps) are executed in strict order.

Certain instructions that alter the flow of program control are not identified by I-decode unit 262. Such instructions include a return from a subroutine return procedure instruction and a return from a trap. The instruction issuing unit 498 sends a discrimination control signal to the IFU 102 via the IEU return control line 350. The corresponding one of the special registers 412 is selected, and the IF that exists at the time of aging of the call instruction, at the time of occurrence of the trap, or at the time of appearance of the procedure instruction is selected. Output PC execution address. 6) Details of Completion Control Unit Completion control unit 540 monitors functional units 478o-n to check the completion status of the current operation. In the preferred architecture 100, the completion control unit 540 anticipates completion of the operation by each functional unit, and generates a completion vector indicating the execution status of each instruction in the currently pending instruction set by the instruction unit 478o-n. Is sent to the register renaming unit 496, the bypass control unit 520, and the evacuation control unit 500 about half a processor cycle before the completion of the execution. Thereby, the instruction issuing unit 49
8, through register rename unit 496, can consider functional units that complete execution as available resources for the next instruction issue cycle. The bypass control unit 520 can prepare to bypass the output from the functional unit through the bypass stream 474. Finally, the evacuation control unit 500
At the same time as transferring data from the functional unit 478o-n to the register file array 472, the corresponding instruction is saved. 7) Details of the evacuation control unit In addition to the instruction completion vector sent from the completion control unit 540, the evacuation control unit 500 is an E-decode unit.
Monitor the oldest instruction set output from the 490.
Completion control unit 54 for each instruction in the instruction stream order
When marked complete by a 0, the evacuation control unit 500 sends the register data from the temporary buffer slot through the control signal sent on the control line 534.
The corresponding instruction in file array 472 indicates to transfer data to the specified file register location. If one or more instructions are evacuated simultaneously,
A PCInc / Size control signal is sent out on control line 344. Up to four instructions can be saved in each processor cycle. When the entire instruction set has been retired, an IFIFO read control signal is issued on control line 342 to advance IFIFO 264. 8) Control Flow Control Unit Details The control flow control unit 528 determines whether the control flow instructions in the current pending instruction set have been resolved, and
Information that specifies whether the branch was taken
It works to give it to IFU 102 constantly. The control flow control unit 528 acquires the identification information of the control flow branch instruction by the E decode unit 490 via the control line 510. The current set of register dependencies is sent from the data dependency checker unit 494 via the control line 536 to the control flow control unit 528, so that the control flow control unit 528 ties the results of the branch instruction to the dependencies. Can be determined whether or not it is known. Register references sent from register rename unit 496 via bus 518 are monitored by control flow control unit 528 to determine the Boolean registers that define branch decisions. Therefore, the branch decision can be determined even before execution of the out-of-order control flow instruction.

Simultaneously with the execution of the control flow instruction, the bypass unit 472 sends the result of the control flow to the control flow control unit 538 via the control line 530 including the control lines 750 and 752 of the control flow 1 and the control flow 2. You will be instructed to send it. Finally, the control flow control unit 528
Continuously sends two vectors, each of 8 bits, to IFU 102 via control line 348. These vectors define whether the instruction located at the logical location corresponding to the bit in the vector has been resolved, and whether a branch has taken place as a result. In the preferred architecture 100, the control flow control unit 528 is implemented as combinational logic that operates continuously upon receiving input control signals to the control unit 528. 9) Details of the Bypass Control Unit The instruction issuing unit 498 works closely with the bypass control unit 520 to control the routing of data between the register file array 472 and the functional units 478o-n. The bypass control unit 520 operates in conjunction with the register file access, output and store phases of the operation shown in FIG. During register file access, bypass control unit 520
Can access via control line 522 the access of a destination register in register file array 472 that is being written during the output phase of execution of the instruction. In this case, bypass control unit 520 instructs to select the output sent on functional unit output bus 482 to bypass and return to functional unit distribution bus 480. Control over bypass unit 520 is provided by instruction issue unit 498 via control line 542. IV. The interface definition of the virtual memory control unit VMU 108 is shown in FIG. VMU 108 is mainly VMU control logic unit 800
And content addressable memory (CAM) 802
It is composed of The general functions of the VMU 108 are shown in a block diagram in FIG. In the figure, the display of the virtual address is represented by the space ID (sID [31:28]) and the virtual page number (V
ADDR [27:14]), page offset (PADDR [13: 4]), and request ID (rID [3: 0]). The algorithm for generating the physical address uses the space ID to select one of the 16 registers in the space table 842. Selected space
The contents of the register and the virtual page number are combined and used as an address when accessing the table look-up buffer (TLB) 844. The 34-bit address serves as a content address tag and is used to specify the corresponding buffer register in buffer 844. If a match is found for the tag, an 18-bit wide register value is obtained as the upper 18 bits of the physical address 846. The page offset and request ID are obtained as the lower 14 bits of the physical address 846.

If no tag match is found in the table index buffer 844, a VMU mismatch is reported. In this case, it is necessary to execute a VMU fast trap processing routine employing the conventional hash algorithm 848 which accesses the complete page table data structure maintained in the MAU 112. This page table 850 contains entries for all memory pages currently in use by the architecture 100. Hash algorithm 848 determines the page table entries needed to satisfy the current virtual page translation operation. These page table entries are loaded from MAU 112 into the trap registers of register set "A" and then transferred to table look-up buffer 844 by a special register move instruction. When returning from the exception handling routine, the VM
The instruction that caused the U mismatch exception is re-executed by IEU 104. The virtual to physical address translation operation should complete without raising an exception.

The VMU control logic 800 includes the IFU 102 and the IE
Dual interface with U104. The ready signal is sent to IEU 104 via control line 822 and the VMU 10
Signals that 8 is available for address translation. In the preferred embodiment, VMU 108 is always ready to accept IFU 102 conversion requests. IFU 102 and IEU104
Can submit the request via control lines 328 and 804. In the preferred architecture 100,
The IFU can access the VMU 108 with priority.
As a result, only one busy (in use) control line 820
Output to IEU 104.

IFU 102 and IEU 104 are both spaces.
The ID and virtual page number fields are sent to VMU control logic 800 via control lines 326 and 808, respectively. In addition, IEU 104 applies read / write control signals to control signals 80
Output with 6. This control signal defines, as necessary, whether the address should be used for a load operation or a store operation to change the memory access protection attribute of the referenced virtual memory. The space ID and virtual page fields of the virtual address are passed to the CAM unit 802, where the actual translation operation is performed. The page offset and ExID fields are ultimately sent directly from the IEU 104 to the CCU 106. The physical page and request ID fields are sent to CAM unit 802 via address line 836. When a match is found in the table index buffer, the VMU control logic unit is routed via the hit line and control output line 830.
800 will be notified. The resulting 18-bit physical address is output on address output line 824.

The VMU control logic unit 800 receives a hit and control output control signal from line 830,
Virtual memory mismatch and virtual memory exception control signal on line 33
4, output on 332 The virtual memory translation mismatch means that the page table ID in the table index buffer 844 does not match. All other translation errors are reported as virtual memory exceptions.

Finally, the data table in the CAM unit 802 can be changed by the IEU 104 executing a special register move instruction. Read / write, register select, reset, load and clear control signals are IEU
The signal is output from the control line 104 via control lines 810, 812, 814, 816, 818. The output to be written to the CAM unit register is received by the VMU control logic unit 800 from the IEU 104 via the address bus 808 connected to the special register data bus 354. This data is transferred to the CAM unit 802 via the bus 836 at the same time as control signals for controlling initialization, register selection, and read / write control signals. As a result, the data registers in the CAM unit 802 store the dynamic operations of the architecture 100, including reads for stores needed when processing context switches defined in higher-level operating systems. Can be exported immediately if needed. V. The control on the data interface for the cache control unit CCU 106 is shown in FIG. Again, the interface is IFU 10
2 and IEU 104 are provided separately. In addition, a logically separate interface is provided on the CCU 106 to
Command and data transfer is performed with U 110. The IFU interface sends out the physical page address on address line 324 and the physical page address on address line 824
It consists of a VMU translation page address and a request ID that is separately transferred on control lines 294 and 296. The unidirectional data transfer bus 114 is for transferring the entire instruction set in parallel with the IFU 102. Finally, read / busy (r
ead / busy and ready control signals are sent to the CCU 106 via control lines 298,300,302.

Similarly, the complete physical address is sent from IEU 102 via physical address bus 788. Request Ex
The ID is sent to and received from the IEU 104 load / store unit separately via control line 796. An 80-bit wide unidirectional data bus is provided in the CCU 106 and connected to the IEU 104. However, in the preferred embodiment of architecture 100, only the lower 64 bits are used by IEU 104. The full 80-bit data transfer bus was provided and supported in the CCU 106 by modifying the floating point data path 660 to enable future implementation of the architecture 100 that supports floating point operation in accordance with IEEE Standard 754. To support.

The IEU control interface is established through request, busy, prepare, read / write and control signals 784 and is substantially the same as the corresponding control signals used by IFU 102. However, the difference is that a read / write control signal is provided to distinguish the load operation / store operation. The width control signal is IEU 104
Each time the CCU 106 is accessed, the number of bytes transferred during that time is specified. On the other hand, instruction cache 13
Each of the two accesses has a fixed 128-bit data width.
This is a fetch operation.

The CCU 106 implements a substantially conventional cache control function for the instruction cache 132 and the data cache 134. In the preferred architecture 100, the instruction cache 132 is a high speed memory capable of storing 256 128-bit wide instruction sets. The data cache 134 can store 1024 32-bit wide data words. Instructions and data requests that cannot be immediately satisfied from the contents of the instruction cache 132 and the data cache 134 are delivered to the MCU 110. If the instruction cache does not match (miss), a 28-bit wide physical address is sent to the MCU 110 via the address bus 860. The request ID and additional control signals for coordinating the operation of CCU 106 and MCU 100
2 Sent up. When the MCU 110 coordinates the required read access of the MAU 112, two consecutive 64-bit wide data transfers are made from the MAU 112 directly to the instruction cache 132. Assuming that data bus 136 is 64 bits wide in preferred architecture 100, two transfers are required. When the requested data is returned via MCU 110, the request ID held during the time the request operation was pending is also returned via control line 862 to CCU 106.
Will be returned to

The data transfer operation between the data cache 134 and the MCU 110 is almost the same as the operation in the case of the instruction cache. Since data load and store operations can reference a single byte, the full 32-bit wide physical address is sent to MCU 110 via address bus 864. The interface control signal and the request ExID are transferred via the control line 866. Cache bus for data for bidirectional 64-bit data transfer
Via 138.

[0170]

As described above, according to the present invention, the instructions can be executed out of order, the prefetch instruction transfer paths for the main and target instruction streams are separately provided, and the procedure instruction confirmation and dedicated prefetch paths are provided. Can be provided. The instruction execution unit is optimized so that it can support integer, floating point and Boolean operations in multiple optimized data processing paths,
Further, since each temporary register file is provided, out-of-order execution and instruction cancellation can be easily performed while accurately maintaining the easily set machine state.

Therefore, although the above description discloses the preferred embodiment of the present invention, it is obvious that those skilled in the art can make various changes and improvements within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a simplified block diagram illustrating the microprocessor architecture of the present invention.

FIG. 2 is a detailed block diagram showing an instruction fetch unit of the present invention.

FIG. 3 shows the program counter logic of the present invention.
It is a block diagram showing a unit.

FIG. 4 is another detailed block diagram showing program counter data and control path logic.

FIG. 5 is a simplified block diagram showing an instruction execution unit of the present invention.

FIG. 6 is a diagram illustrating a register file and an instruction set.

FIG. 7 illustrates the reconfigurable states of a primary integer register set.

FIG. 8 illustrates a floating point and secondary integer register set.

FIG. 9 illustrates a tertiary bull register set.

FIG. 10 is a detailed block diagram showing a primary integer processing data path portion of the instruction execution unit.

FIG. 11 is a detailed block diagram showing a primary floating-point data path portion of the instruction execution unit.

FIG. 12 is a detailed block diagram showing a bull operation data path portion of the instruction execution unit.

FIG. 13 is a detailed block diagram showing a load / store unit.

FIG. 14 is a timing chart showing an operation sequence when executing a plurality of instructions.

FIG. 15 is a simplified block diagram showing a virtual memory control unit.

FIG. 16 is a diagram showing a virtual memory control algorithm in graphic form.

FIG. 17 is a simplified block diagram showing a cache control unit.

[Explanation of symbols]

100: Outline of architecture, 102: Instruction fetch unit (IFU) 104: Instruction execution unit (IE)
U), 106: Cache control unit (CUU), 1
08: virtual memory unit (VMU), 110: memory control unit (MCU), 112: memory array
Unit (MAU).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 9/32 310 G06F 9/32 310J 9/355 9/36 320 (72) Inventor Miyayama, Yoshiyuki United States 95050 Santa Clara, California Rancho McCormick Boulevard 2171 (72) Inventor Garg, Sanjib United States 94539 Fremont, Sentinel Drive, California 46820 (72) Inventor Hagiwara, Yasuki United States 95050 Santa Clara, Monroe Street 2250, California Apartment 274 (274) 72) Inventor One, Johannes United States 94062 Redwood City, California King Street 25 (72) Inventor Lau , Tiri United States 94306 Palo Alto College Avenue 411, California 411 Apartment E (72) Inventor Tran, Kwan H. United States 95130 San Jose Mayfield Avenue, California 2045

Claims (20)

[Claims] 1. A superscalar processing system for executing instructions in a specified program order, comprising: a register file including a temporary buffer for storing register data corresponding to an instruction set and a register file array; Irrespective of the designated program order, a plurality of functional units for executing a plurality of operations corresponding to the instruction set and generating a plurality of results corresponding to the instruction set upon completion of the operation; and A first means for simultaneously transferring to the plurality of functional units; and a second means for simultaneously distributing the plurality of results, wherein the predetermined one of the operations is performed out of a designated program order. When said temporary buffer stores one of said results corresponding to a predetermined one of said operations from said second means. Taking, when said predetermined one of said operations is completed according to a specified program order, said register file array receiving said result of said predetermined one of said operations from said second means and bypassing said temporary buffer means. Characterized super scalar processing system. 2. The register file includes an integer register file and a floating point register file, the functional unit includes an integer functional unit and a floating point functional unit, and the first means transfers data from the floating point register file to the integer functional unit. The super scalar processing system according to claim 1, wherein the data is transferred to a super scalar processing system. 3. A superscalar processing system for executing instructions in a designated program order, comprising: an instruction fetch unit for simultaneously fetching a plurality of instructions from an instruction store; and an instruction set fetched by the instruction fetch unit. A register file including a register file array and a temporary buffer for storing register data corresponding to the above, executing a plurality of operations corresponding to the instruction set regardless of a designated program order, and upon completion of the plurality of operations, A plurality of functional units for generating a plurality of results corresponding to the instruction set; a register file output bus for simultaneously transferring the register data from the register file to the plurality of functional units; an input selecting unit; Output bus for simultaneously distributing the result of And when the predetermined one of the operations is performed out of a designated program order, the temporary buffer receives one of the results corresponding to the predetermined one of the operations from the input selection means, The register file array receives the result of the predetermined one of the operations from the input selection means when the predetermined one of the operations is completed according to a specified program order, and bypasses the temporary buffer means. Super scalar processing system. 4. The superscalar processing system according to claim 3, wherein said plurality of instructions are fetched out of said designated program order. 5. After the conditional branch instruction is fetched,
4. A superscalar processing system according to claim 3, wherein said instruction fetch means fetches two possible instruction streams. 6. The control method according to claim 3, further comprising a decoder for simultaneously decoding a plurality of instructions in a designated program order, and providing control information for identifying a special property and function of each of the plurality of instructions. Super scalar processing system. 7. The superscalar processing system according to claim 3, wherein said instruction store is an instruction cache. 8. The superscalar processing system according to claim 3, wherein said instruction fetch means fetches four instructions from said instruction store at the same time. 9. The superscalar processing system according to claim 3, further comprising an instruction buffer, wherein said instruction fetched by said instruction fetch means is stored. 10. A superscalar processing system for executing instructions in a specified program order, comprising: a register file including a temporary buffer for storing register data corresponding to an instruction set and a register file array; Irrespective of the designated program order, a plurality of functional units for executing a plurality of operations corresponding to the instruction set and generating a plurality of results corresponding to the instruction set upon completion of the operation; and A register file output bus for simultaneous transfer to the plurality of functional units; and an output bus for simultaneously distributing the plurality of results, wherein the predetermined one of the operations is performed out of a designated program order. Means that the temporary buffer is
Receiving one of said results corresponding to one of said operations and said register file array receiving said result of said predetermined one of said operations when said predetermined one of said operations is completed according to a specified program order. A super scalar processing system characterized by bypassing a buffer means. 11. The register file includes an integer register file and a floating point register file, the functional unit includes an integer functional unit and a floating point functional unit, and the register file output bus transfers register data from the floating point register file. The super scalar processing system according to claim 10, wherein the transfer is performed to the integer functional unit. 12. The system of claim 11, further comprising a load / store unit, wherein said output bus further distributes results to said load / store unit, said load / store unit storing said distribution results in a memory device. Item 11. A superscalar processing system according to item 10. 13. The load / store unit buffers the allocation result before storing the allocation result in the memory device to ensure data integrity (consistency, integrity). The super scalar processing system according to claim 12, wherein 14. A data processing method in a superscalar processing system for executing instructions in a designated program order, the method comprising: storing register data corresponding to an instruction set in a register file including a temporary buffer and a register file array; Simultaneously transferring register data to a plurality of functional units; executing a plurality of operations corresponding to the instruction set using the plurality of functional units, independently of the designated program order; Generating a plurality of results corresponding to the instruction set when the work is completed; allocating the plurality of results simultaneously; and when a predetermined one of the works is performed out of a specified program order, Storing in the temporary buffer a result corresponding to a predetermined one of the tasks; One of, when performed in accordance with specified program order, a data processing method comprising the step of storing a result corresponding to a given one of the tasks in the register file array. 15. The method of claim 14, further comprising the step of distributing the results to load / store units. 16. The data processing method according to claim 15, further comprising the step of buffering the distribution result in the load / store unit. 17. The data processing method according to claim 16, further comprising storing the distribution result in a memory unit. 18. The data processing method according to claim 14, further comprising the step of simultaneously fetching a set of instructions from an instruction store. 19. The method of claim 18, wherein the set of instructions is fetched out of order with respect to the specified program order. 20. The method of claim 14, further comprising fetching two possible instruction streams after the conditional branch instruction.