JP2000122748A - Abnormal state detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect abnormality while suppressing power consumption even if the operation state of the abnormal state detecting circuit changes owing to an external factor and a clock stops by storing the change of a register which controls the operation stop of oscillation when the register become abnormal and no write signal is inputted. SOLUTION: If the value of the oscillation control register 51 varies although a write enable signal 52 is '0', that means that the value of the oscillation control register 51 varies owing to a factor such as external noise. For the purpose, this is detected by D type flip-flop circuits 55 and 56 and an abnormal state detection signal is outputted through an OR circuit 58. When the write enable signal is '1', there is the possibility that the value of the oscillation control register 51 varies and an AND circuit 54 cuts off it so as to prevent its detection. The D type flip-flop circuits 55 and 56 detect the oscillation control register changing from '0' to '1' and from '1' to '0' respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormal state detection circuit having an oscillation circuit for activating / stopping oscillation by the output of a register, the operation state of which is changed by an external factor.
The present invention relates to an abnormal state detection circuit having a function of detecting an abnormality even when a clock stops.

[0002]

2. Description of the Related Art In recent years, microcomputers have become widespread. Since the microcomputer operates by the clock, if the clock stops due to an abnormality, the operation of the microcomputer also stops, and it is difficult to detect the abnormality.

Therefore, in order to detect such an abnormality, a dedicated circuit independent of a clock is generally added.

FIG. 1 shows a conventional circuit for detecting that a clock has stopped due to an abnormality. 17 is an oscillation circuit, 24 is a resistor, 25 is a capacitor, 22 is a switching element, and 26 is a switching element.
Is a decision circuit, 23 is an internal node, 18 is a clock, 27
Is an abnormal state detection signal.

[0005] The operation of the abnormal state detection circuit configured as described above will be described below.

First, when the clock 18 is operating normally, the switching element 22 is turned "ON" and "OFF".
repeat. The switching element 22 is generated by the clock 18.
Is in the "OFF" state, the capacitor 25 is charged from the power supply line via the resistor 24, but the internal node 23 is charged.
Until the level of the capacitor 25 reaches the determination reference potential.
, The abnormal state detection signal 27 does not change. On the other hand, when the oscillation clock 18 input from the oscillation circuit 17 is stopped and fixed at the “L” level, the switching element 22 is turned “OFF” and the resistance 2
4, the capacitor 25 is charged, and the level of the internal node 23 reaches the determination criterion, and outputs the abnormal state detection signal 27.

[0007]

However, in the above-mentioned conventional method, there is a problem that the power consumption of the abnormal state detecting circuit is increased because charging and discharging are repeated by a resistor and a capacitor as shown in FIG. . The present invention solves such a problem, and an abnormal state detection circuit that can detect an abnormality while suppressing power consumption even when the operation state of the abnormal state detection circuit changes due to an external factor and the clock stops. The purpose is to provide.

[0008]

SUMMARY OF THE INVENTION In order to solve this problem, according to the present invention, the value of the oscillation control register is set to "" even though there is no write enable signal to the oscillation control register.
The change from "0" to "1" or "1" to "0" is detected by two flip-flop circuits and an abnormal state detection signal is output.

Further, according to the present invention, the value of the oscillation control register is stored in the flip-flop circuit, and the value stored in the flip-flop circuit and the value of the oscillation control register are stored even though there is no write enable signal to the oscillation control register. If the value of becomes different, an abnormal state detection signal is output.

[0010]

Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 3 is a block diagram of an abnormality detection circuit according to Embodiment 1 of the present invention. Reference numeral 50 denotes an oscillation circuit for generating a clock, and 51 denotes an oscillation control for controlling the oscillation of the oscillation circuit 50. 52, a write enable signal for the oscillation control register 51; 53, 57 an inverting circuit for inverting and outputting an input signal; 54, an AND circuit;
Reference numerals 5 and 56 denote D-type flip-flop circuits, and reference numeral 58 denotes an OR circuit for calculating a logical sum.

In the first embodiment, although the write enable signal 52 is not set to "1", the oscillation control register 51 sets "0" to "1" or "1" to "1".
The D-type flip-flop circuit 55,
At 56, an abnormal state detection signal is generated.

More specifically, the write enable signal 52
Is set to "1", the value of the oscillation control register 51 may change. Therefore, in order to prevent the D-type flip-flop circuits 55 and 56 from detecting this, the AND circuit 54 cuts off this. . The D-type flip-flop circuit 55 detects that the oscillation control register 51 changes from “0” to “1”, and the D-type flip-flop circuit 56 detects that the oscillation control register 51 changes from “1” to “0”. are doing.

Next, the operation will be specifically described with reference to the timing chart of FIG. First, as a premise, the oscillation circuit 50 oscillates when the value of the oscillation control register 51 is "1" (timing t2), and stops oscillation when the value of the oscillation control register 51 is "0" (timing t2). t1). The value of the oscillation control register 51 can be rewritten by setting the write enable signal 52 to “1” and supplying write data.

Under such a premise, if the value of the oscillation control register 51 changes (timing t3) even though the write enable signal 52 is "0", the oscillation control is performed due to external noise or the like. Since this means that the value of the register 51 has changed, this is detected by a D-type flip-flop circuit, and an abnormal state detection signal is output. In FIG. 4, since the value of the oscillation control register 51 changes from “1” to “0” even though the write enable signal 52 is “0”, the output of the D-type flip-flop circuit 56 becomes “1”. "And output as an abnormal state detection signal via the OR circuit 58.

(Embodiment 2) FIG. 5 is a block diagram of an abnormal state detection circuit according to Embodiment 2; 60 is an EXOR circuit for calculating exclusive OR, 61 is an AND circuit for calculating logical product, and 62 is This is an inverting circuit that inverts and outputs an input signal, and the same components as those in FIG. 3 are denoted by the same reference numerals.

In the second embodiment, the value to be written to the oscillation control register 51 is stored by the D-type flip-flop circuit 55, and the EXOR circuit 60 determines when the value of the oscillation control register 51 changes due to abnormality. It detects and outputs an abnormal state detection signal. The AND circuit 61 has a role equivalent to that of the AND circuit 54 of FIG. 3, and detects that the value of the oscillation control register 51 has changed despite the write enable signal 52 being "0". Thus, an abnormal state can be detected by a simpler circuit than in the first embodiment.

The operation is the same as that shown in FIG. 4 and will not be described. (Embodiment 3) FIG. 6 is a block diagram of an abnormal state detecting circuit according to Embodiment 3 and differs from FIG. 5 in that an inverting circuit 63 is provided instead of the inverting circuit 62.

The third embodiment is almost similar to the second embodiment. However, since the value currently written in the oscillation control register 51 is input to the D-type flip-flop circuit, the inversion circuit is used. At 63, the value of the oscillation control register 51 is stored in the D-type flip-flop circuit 55 at the falling edge of the write enable signal 52, and the timing is adjusted.

The operation is the same as that shown in FIG.

[0021]

As described above, according to the present invention, when an abnormality occurs in the register for controlling the stop of the oscillation operation and the write signal to the register is not input, the change in the register is stored. Thus, it is possible to realize an abnormal state detection circuit capable of transmitting an oscillation abnormality to the outside.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional abnormal state detection circuit.

FIG. 2 is a timing chart of a conventional abnormal state detection circuit.

FIG. 3 is a block diagram of an abnormal state detection circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart according to the first embodiment of the present invention.

FIG. 5 is a block diagram of an abnormal state detection circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram of an abnormal state detection circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 17 Oscillation circuit 18 Clock 22 Switching element 23 Internal node 24 Resistance 25 Capacitor 26 Judgment circuit 27 Abnormal state detection signal 50 Oscillation circuit 51 Oscillation control register 52 Write enable signal 53, 57, 62, 63 Inversion circuit 54, 61 AND circuit 55, 56 D-type flip-flop circuit 58 OR circuit 60 EXOR circuit

Claims (3)

[Claims] An abnormality detection circuit for detecting an abnormality of an oscillation circuit whose oscillation is controlled by a value of an oscillation control register, wherein the abnormality detection circuit detects that the value of the oscillation control register has changed from “0” to “1”. 1 flip-flop circuit, a second flip-flop circuit for detecting that the value of the oscillation control register has changed from "1" to "0", and a write enable signal to the oscillation control register being absent. An abnormal state detection circuit which outputs an abnormal state detection signal when an output of the first or second flip-flop circuit is received. 2. An abnormality detection circuit for detecting an abnormality of an oscillation circuit whose oscillation is controlled by a value of an oscillation control register, wherein: a flip-flop circuit for storing a value to be written to the oscillation control register; Outputting an abnormal state detection signal when the value stored in the flip-flop circuit and the value of the oscillation control register become different despite the absence of the write enable signal of State detection circuit. 3. An abnormality detection circuit for detecting an abnormality of an oscillation circuit whose oscillation is controlled by a value of an oscillation control register, a flip-flop circuit for storing the value of the oscillation control register, and a write enable to the oscillation control register. An abnormal state detection circuit for outputting an abnormal state detection signal when a value stored in the flip-flop circuit and a value of the oscillation control register are different from each other despite no signal; .