JP2000121698A5 - - Google Patents

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Publication number
JP2000121698A5
JP2000121698A5 JP1999290333A JP29033399A JP2000121698A5 JP 2000121698 A5 JP2000121698 A5 JP 2000121698A5 JP 1999290333 A JP1999290333 A JP 1999290333A JP 29033399 A JP29033399 A JP 29033399A JP 2000121698 A5 JP2000121698 A5 JP 2000121698A5
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JP
Japan
Prior art keywords
subset
node
nodes
configuration
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999290333A
Other languages
English (en)
Japanese (ja)
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JP2000121698A (ja
Filing date
Publication date
Priority claimed from US09/169,421 external-priority patent/US6467051B1/en
Application filed filed Critical
Publication of JP2000121698A publication Critical patent/JP2000121698A/ja
Publication of JP2000121698A5 publication Critical patent/JP2000121698A5/ja
Pending legal-status Critical Current

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JP11290333A 1998-10-09 1999-10-12 アクセスを制限した回路テストのためのテストポイントのノ―ドを選択する方法及び装置 Pending JP2000121698A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US169421 1998-10-09
US09/169,421 US6467051B1 (en) 1998-10-09 1998-10-09 Method and apparatus for selecting test point nodes of a group of components having both accessible and inaccessible nodes for limited access circuit test

Publications (2)

Publication Number Publication Date
JP2000121698A JP2000121698A (ja) 2000-04-28
JP2000121698A5 true JP2000121698A5 (enExample) 2006-11-30

Family

ID=22615615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11290333A Pending JP2000121698A (ja) 1998-10-09 1999-10-12 アクセスを制限した回路テストのためのテストポイントのノ―ドを選択する方法及び装置

Country Status (4)

Country Link
US (1) US6467051B1 (enExample)
EP (1) EP0994360B1 (enExample)
JP (1) JP2000121698A (enExample)
DE (1) DE69926587T2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1364286B1 (de) * 2001-02-20 2009-08-19 Siemens Aktiengesellschaft Verfahren und anordnung zur ermittlung einer gesamtfehlerbeschreibung zumindest eines teils eines technischen systems, computer programm-element und computerlesbares speichermedium
JP2007041670A (ja) * 2005-08-01 2007-02-15 Matsushita Electric Ind Co Ltd 半導体集積回路の設計データ構造、設計装置および設計方法
US10042741B2 (en) * 2011-02-28 2018-08-07 Synopsys, Inc. Determining a subset of tests
US11132235B2 (en) * 2017-02-16 2021-09-28 Hitachi, Ltd. Data processing method, distributed data processing system and storage medium
KR102688659B1 (ko) * 2024-02-14 2024-07-25 주식회사 알세미 인공신경망 모델을 이용한 회로 평가 방법 및 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172377A (en) * 1990-09-07 1992-12-15 Genrad, Inc. Method for testing mixed scan and non-scan circuitry
US5513188A (en) * 1991-09-10 1996-04-30 Hewlett-Packard Company Enhanced interconnect testing through utilization of board topology data
US5448166A (en) * 1992-01-03 1995-09-05 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
US5323108A (en) * 1992-01-23 1994-06-21 Hewlett-Packard Company Method for generating functional tests for printed circuit boards based on pattern matching of models
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5808919A (en) 1993-11-23 1998-09-15 Hewlett-Packard Company Diagnostic system

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